From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Rahul Pathak <rpathak@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 04/12] target/riscv: Remove sideleg and sedeleg
Date: Fri, 23 Sep 2022 14:06:56 +1000 [thread overview]
Message-ID: <20220923040704.428285-5-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220923040704.428285-1-alistair.francis@opensource.wdc.com>
From: Rahul Pathak <rpathak@ventanamicro.com>
sideleg and sedeleg csrs are not part of riscv isa spec
anymore, these csrs were part of N extension which
is removed from the riscv isa specification.
These commits removed all traces of these csrs from
riscv spec (https://github.com/riscv/riscv-isa-manual) -
commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)")
commit b6cade07034d ("Remove N extension chapter for now")
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 2 --
disas/riscv.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7be12cac2e..b762807e4e 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -190,8 +190,6 @@
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
-#define CSR_SEDELEG 0x102
-#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
diff --git a/disas/riscv.c b/disas/riscv.c
index 489c2ae5e8..f107d94c4c 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1304,8 +1304,6 @@ static const char *csr_name(int csrno)
case 0x0043: return "utval";
case 0x0044: return "uip";
case 0x0100: return "sstatus";
- case 0x0102: return "sedeleg";
- case 0x0103: return "sideleg";
case 0x0104: return "sie";
case 0x0105: return "stvec";
case 0x0106: return "scounteren";
--
2.37.3
next prev parent reply other threads:[~2022-09-23 4:13 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-23 4:06 [PULL 00/12] riscv-to-apply queue Alistair Francis
2022-09-23 4:06 ` [PULL 01/12] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Alistair Francis
2022-09-23 4:06 ` [PULL 02/12] hw/ssi: ibex_spi: update reg addr Alistair Francis
2022-09-23 4:06 ` [PULL 03/12] docs/system: clean up code escape for riscv virt platform Alistair Francis
2022-09-23 4:06 ` Alistair Francis [this message]
2022-09-23 4:06 ` [PULL 05/12] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} Alistair Francis
2022-09-23 4:06 ` [PULL 06/12] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml Alistair Francis
2022-09-23 4:06 ` [PULL 07/12] target/riscv: remove fixed numbering from GDB xml feature files Alistair Francis
2022-09-23 4:07 ` [PULL 08/12] target/riscv: Set the CPU resetvec directly Alistair Francis
2022-09-23 4:07 ` [PULL 09/12] hw/riscv: opentitan: Fixup resetvec Alistair Francis
2022-09-23 4:07 ` [PULL 10/12] hw/riscv: opentitan: Expose the resetvec as a SoC property Alistair Francis
2022-09-23 4:07 ` [PULL 11/12] target/riscv: Check the correct exception cause in vector GDB stub Alistair Francis
2022-09-23 4:07 ` [PULL 12/12] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Alistair Francis
2022-09-26 19:28 ` [PULL 00/12] riscv-to-apply queue Stefan Hajnoczi
2022-09-26 20:59 ` Alistair Francis
2022-09-26 21:04 ` Stefan Hajnoczi
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