From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Wilfred Mallawa <wilfred.mallawa@wdc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 02/12] hw/ssi: ibex_spi: update reg addr
Date: Fri, 23 Sep 2022 14:06:54 +1000 [thread overview]
Message-ID: <20220923040704.428285-3-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220923040704.428285-1-alistair.francis@opensource.wdc.com>
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Updates the `EVENT_ENABLE` register to offset `0x34` as per
OpenTitan spec [1].
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220823061201.132342-5-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/ssi/ibex_spi_host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
index 601041d719..94d7da9cc2 100644
--- a/hw/ssi/ibex_spi_host.c
+++ b/hw/ssi/ibex_spi_host.c
@@ -93,7 +93,7 @@ REG32(ERROR_STATUS, 0x30)
FIELD(ERROR_STATUS, CMDINVAL, 3, 1)
FIELD(ERROR_STATUS, CSIDINVAL, 4, 1)
FIELD(ERROR_STATUS, ACCESSINVAL, 5, 1)
-REG32(EVENT_ENABLE, 0x30)
+REG32(EVENT_ENABLE, 0x34)
FIELD(EVENT_ENABLE, RXFULL, 0, 1)
FIELD(EVENT_ENABLE, TXEMPTY, 1, 1)
FIELD(EVENT_ENABLE, RXWM, 2, 1)
--
2.37.3
next prev parent reply other threads:[~2022-09-23 4:13 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-23 4:06 [PULL 00/12] riscv-to-apply queue Alistair Francis
2022-09-23 4:06 ` [PULL 01/12] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Alistair Francis
2022-09-23 4:06 ` Alistair Francis [this message]
2022-09-23 4:06 ` [PULL 03/12] docs/system: clean up code escape for riscv virt platform Alistair Francis
2022-09-23 4:06 ` [PULL 04/12] target/riscv: Remove sideleg and sedeleg Alistair Francis
2022-09-23 4:06 ` [PULL 05/12] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} Alistair Francis
2022-09-23 4:06 ` [PULL 06/12] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml Alistair Francis
2022-09-23 4:06 ` [PULL 07/12] target/riscv: remove fixed numbering from GDB xml feature files Alistair Francis
2022-09-23 4:07 ` [PULL 08/12] target/riscv: Set the CPU resetvec directly Alistair Francis
2022-09-23 4:07 ` [PULL 09/12] hw/riscv: opentitan: Fixup resetvec Alistair Francis
2022-09-23 4:07 ` [PULL 10/12] hw/riscv: opentitan: Expose the resetvec as a SoC property Alistair Francis
2022-09-23 4:07 ` [PULL 11/12] target/riscv: Check the correct exception cause in vector GDB stub Alistair Francis
2022-09-23 4:07 ` [PULL 12/12] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Alistair Francis
2022-09-26 19:28 ` [PULL 00/12] riscv-to-apply queue Stefan Hajnoczi
2022-09-26 20:59 ` Alistair Francis
2022-09-26 21:04 ` Stefan Hajnoczi
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