From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
qemu-ppc@nongnu.org, "Aurelien Jarno" <aurelien@aurel32.net>,
"Yoshinori Sato" <ysato@users.sourceforge.jp>,
"Antony Pavlov" <antonynpavlov@gmail.com>,
"BALATON Zoltan" <balaton@eik.bme.hu>,
"Alistair Francis" <alistair@alistair23.me>,
"Bin Meng" <bin.meng@windriver.com>,
"Kevin Wolf" <kwolf@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jan Kiszka" <jan.kiszka@web.de>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Hanna Reitz" <hreitz@redhat.com>,
qemu-arm@nongnu.org, "Magnus Damm" <magnus.damm@gmail.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
qemu-block@nongnu.org, "Bernhard Beschow" <shentey@gmail.com>,
"Bin Meng" <bmeng.cn@gmail.com>
Subject: [PATCH v4 4/7] hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*
Date: Tue, 18 Oct 2022 23:01:43 +0200 [thread overview]
Message-ID: <20221018210146.193159-5-shentey@gmail.com> (raw)
In-Reply-To: <20221018210146.193159-1-shentey@gmail.com>
The device model's functions start with "usdhc_", so rename the defines
accordingly for consistency.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
hw/sd/sdhci.c | 66 +++++++++++++++++++++++++--------------------------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 6da5e2c781..306070c872 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1577,24 +1577,24 @@ static const TypeInfo sdhci_bus_info = {
/* --- qdev i.MX eSDHC --- */
-#define ESDHC_MIX_CTRL 0x48
+#define USDHC_MIX_CTRL 0x48
-#define ESDHC_VENDOR_SPEC 0xc0
-#define ESDHC_IMX_FRC_SDCLK_ON (1 << 8)
+#define USDHC_VENDOR_SPEC 0xc0
+#define USDHC_IMX_FRC_SDCLK_ON (1 << 8)
-#define ESDHC_DLL_CTRL 0x60
+#define USDHC_DLL_CTRL 0x60
-#define ESDHC_TUNING_CTRL 0xcc
-#define ESDHC_TUNE_CTRL_STATUS 0x68
-#define ESDHC_WTMK_LVL 0x44
+#define USDHC_TUNING_CTRL 0xcc
+#define USDHC_TUNE_CTRL_STATUS 0x68
+#define USDHC_WTMK_LVL 0x44
/* Undocumented register used by guests working around erratum ERR004536 */
-#define ESDHC_UNDOCUMENTED_REG27 0x6c
+#define USDHC_UNDOCUMENTED_REG27 0x6c
-#define ESDHC_CTRL_4BITBUS (0x1 << 1)
-#define ESDHC_CTRL_8BITBUS (0x2 << 1)
+#define USDHC_CTRL_4BITBUS (0x1 << 1)
+#define USDHC_CTRL_8BITBUS (0x2 << 1)
-#define ESDHC_PRNSTS_SDSTB (1 << 3)
+#define USDHC_PRNSTS_SDSTB (1 << 3)
static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
{
@@ -1615,11 +1615,11 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
- hostctl1 |= ESDHC_CTRL_8BITBUS;
+ hostctl1 |= USDHC_CTRL_8BITBUS;
}
if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
- hostctl1 |= ESDHC_CTRL_4BITBUS;
+ hostctl1 |= USDHC_CTRL_4BITBUS;
}
ret = hostctl1;
@@ -1630,21 +1630,21 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
case SDHC_PRNSTS:
/* Add SDSTB (SD Clock Stable) bit to PRNSTS */
- ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
+ ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB;
if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
- ret |= ESDHC_PRNSTS_SDSTB;
+ ret |= USDHC_PRNSTS_SDSTB;
}
break;
- case ESDHC_VENDOR_SPEC:
+ case USDHC_VENDOR_SPEC:
ret = s->vendor_spec;
break;
- case ESDHC_DLL_CTRL:
- case ESDHC_TUNE_CTRL_STATUS:
- case ESDHC_UNDOCUMENTED_REG27:
- case ESDHC_TUNING_CTRL:
- case ESDHC_MIX_CTRL:
- case ESDHC_WTMK_LVL:
+ case USDHC_DLL_CTRL:
+ case USDHC_TUNE_CTRL_STATUS:
+ case USDHC_UNDOCUMENTED_REG27:
+ case USDHC_TUNING_CTRL:
+ case USDHC_MIX_CTRL:
+ case USDHC_WTMK_LVL:
ret = 0;
break;
}
@@ -1660,18 +1660,18 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
uint32_t value = (uint32_t)val;
switch (offset) {
- case ESDHC_DLL_CTRL:
- case ESDHC_TUNE_CTRL_STATUS:
- case ESDHC_UNDOCUMENTED_REG27:
- case ESDHC_TUNING_CTRL:
- case ESDHC_WTMK_LVL:
+ case USDHC_DLL_CTRL:
+ case USDHC_TUNE_CTRL_STATUS:
+ case USDHC_UNDOCUMENTED_REG27:
+ case USDHC_TUNING_CTRL:
+ case USDHC_WTMK_LVL:
break;
- case ESDHC_VENDOR_SPEC:
+ case USDHC_VENDOR_SPEC:
s->vendor_spec = value;
switch (s->vendor) {
case SDHCI_VENDOR_IMX:
- if (value & ESDHC_IMX_FRC_SDCLK_ON) {
+ if (value & USDHC_IMX_FRC_SDCLK_ON) {
s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
} else {
s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
@@ -1740,12 +1740,12 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
* Second, split "Data Transfer Width" from bits 2 and 1 in to
* bits 5 and 1
*/
- if (value & ESDHC_CTRL_8BITBUS) {
+ if (value & USDHC_CTRL_8BITBUS) {
hostctl1 |= SDHC_CTRL_8BITBUS;
}
- if (value & ESDHC_CTRL_4BITBUS) {
- hostctl1 |= ESDHC_CTRL_4BITBUS;
+ if (value & USDHC_CTRL_4BITBUS) {
+ hostctl1 |= USDHC_CTRL_4BITBUS;
}
/*
@@ -1768,7 +1768,7 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
sdhci_write(opaque, offset, value, size);
break;
- case ESDHC_MIX_CTRL:
+ case USDHC_MIX_CTRL:
/*
* So, when SD/MMC stack in Linux tries to write to "Transfer
* Mode Register", ESDHC i.MX quirk code will translate it
--
2.38.0
next prev parent reply other threads:[~2022-10-18 21:14 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-18 21:01 [PATCH v4 0/7] ppc/e500: Add support for two types of flash, cleanup Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 1/7] docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s) Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 2/7] hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power of two Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 3/7] hw/sd/sdhci-internal: Unexport ESDHC defines Bernhard Beschow
2022-10-18 21:01 ` Bernhard Beschow [this message]
2022-10-18 21:01 ` [PATCH v4 5/7] hw/ppc/e500: Implement pflash handling Bernhard Beschow
2022-10-26 17:03 ` Daniel Henrique Barboza
2022-10-27 21:11 ` Philippe Mathieu-Daudé
2022-10-28 15:09 ` Daniel Henrique Barboza
2022-10-28 16:03 ` B
2022-10-28 22:42 ` Philippe Mathieu-Daudé
2022-10-29 9:29 ` Daniel Henrique Barboza
2022-10-29 11:24 ` Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 6/7] hw/sd/sdhci: Implement Freescale eSDHC device model Bernhard Beschow
2022-10-27 21:40 ` Philippe Mathieu-Daudé
2022-10-29 11:33 ` Bernhard Beschow
2022-10-29 13:04 ` Bernhard Beschow
2022-10-29 18:28 ` Bernhard Beschow
2022-10-29 23:10 ` Philippe Mathieu-Daudé
2022-10-30 11:46 ` Bernhard Beschow
2022-10-31 12:11 ` Philippe Mathieu-Daudé
2022-11-01 10:49 ` Bernhard Beschow
2022-12-16 14:38 ` Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 7/7] hw/ppc/e500: Add Freescale eSDHC to e500plat Bernhard Beschow
2022-10-26 17:11 ` Daniel Henrique Barboza
2022-10-27 21:12 ` Philippe Mathieu-Daudé
2022-10-23 8:36 ` [PATCH v4 0/7] ppc/e500: Add support for two types of flash, cleanup Bernhard Beschow
2022-10-26 17:18 ` Daniel Henrique Barboza
2022-10-26 19:51 ` B
2022-10-26 21:40 ` Daniel Henrique Barboza
2022-10-31 12:13 ` Philippe Mathieu-Daudé
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