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From: Bernhard Beschow <shentey@gmail.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Yoshinori Sato" <ysato@users.sourceforge.jp>,
	"Antony Pavlov" <antonynpavlov@gmail.com>,
	"BALATON Zoltan" <balaton@eik.bme.hu>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Kevin Wolf" <kwolf@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Jan Kiszka" <jan.kiszka@web.de>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Hanna Reitz" <hreitz@redhat.com>,
	qemu-arm@nongnu.org, "Magnus Damm" <magnus.damm@gmail.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	qemu-block@nongnu.org
Subject: Re: [PATCH v4 6/7] hw/sd/sdhci: Implement Freescale eSDHC device model
Date: Sun, 30 Oct 2022 12:46:05 +0100	[thread overview]
Message-ID: <CAG4p6K5qvJFRihrZV3Gku_fYsxWFzEN4UfGf4xySQyfzkv9q0g@mail.gmail.com> (raw)
In-Reply-To: <45be44c0-766b-07c6-be8a-c21d46da7f72@linaro.org>

[-- Attachment #1: Type: text/plain, Size: 14932 bytes --]

On Sun, Oct 30, 2022 at 1:10 AM Philippe Mathieu-Daudé <philmd@linaro.org>
wrote:

> On 29/10/22 20:28, Bernhard Beschow wrote:
> > Am 29. Oktober 2022 13:04:00 UTC schrieb Bernhard Beschow <
> shentey@gmail.com>:
> >> Am 29. Oktober 2022 11:33:51 UTC schrieb Bernhard Beschow <
> shentey@gmail.com>:
> >>> Am 27. Oktober 2022 21:40:01 UTC schrieb "Philippe Mathieu-Daudé" <
> philmd@linaro.org>:
> >>>> Hi Bernhard,
> >>>>
> >>>> On 18/10/22 23:01, Bernhard Beschow wrote:
> >>>>> Will allow e500 boards to access SD cards using just their own
> devices.
> >>>>>
> >>>>> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> >>>>> ---
> >>>>>    hw/sd/sdhci.c         | 120
> +++++++++++++++++++++++++++++++++++++++++-
> >>>>>    include/hw/sd/sdhci.h |   3 ++
> >>>>>    2 files changed, 122 insertions(+), 1 deletion(-)
>
> >>>> So now, I'd create 1 UNIMP region for ESDHC_WML and map it
> >>>> into SDHC_REGISTERS_MAP (s->iomem) with priority 1, and add
> >>>> another UNIMP region of ESDHC_REGISTERS_MAP_SIZE -
> SDHC_REGISTERS_MAP_SIZE (= 0x310) and map it normally at offset
> >>>> 0x100 (SDHC_REGISTERS_MAP_SIZE). Look at create_unimp() in
> >>>> hw/arm/bcm2835_peripherals.c.
> >>>>
> >>>> But the ESDHC_WML register has address 0x44 and fits inside the
> >>>> SDHC_REGISTERS_MAP region, so likely belong there. 0x44 is the
> >>>> upper part of the SDHC_CAPAB register. These bits are undefined
> >>>> on the spec v2, which I see you are setting in esdhci_init().
> >>>> So this register should already return 0, otherwise we have
> >>>> a bug. Thus we don't need to handle this ESDHC_WML particularly.
> >>
> >> My idea here was to catch this unimplemented case in order to indicate
> this clearly to users. Perhaps it nudges somebody to provide a patch?
> >>
> >>>>
> >>>> And your model is reduced to handling create_unimp() in
> esdhci_realize().
> >>>>
> >>>> Am I missing something?
> >>>
> >>> The mmio ops are big endian and need to be aligned to a 4-byte
> boundary. It took me quite a while to debug this. So shall I just create an
> additional memory region for the region above SDHC_REGISTERS_MAP_SIZE for
> ESDHC_DMA_SYSCTL?
> >>
> >> All in all I currently don't have a better idea than keeping the custom
> i/o ops for the standard region and adding an additional unimplemented
> region for ESDHC_DMA_SYSCTL. I think I'd have to dynamically allocate
> memory for it where I still need to figure out how not to leak it.
> >
> > By simply reusing sdhci_{read,write} in eSDHC's io_ops struct I was able
> to remove the custom implementations while having big endian and the
> alignments proper. However, I don't see a way of adding two memory regions
> - with or without a container. With a container I'd have to somehow
> preserve the mmio attribute which is initialized by the parent class,
> re-initialize it with the container, and add the preserved memory region as
> child. This seems very fragile, esp. since the parent class has created an
> alias for mmio in sysbus. Without a container, one would have two memory
> regions that both have to be mapped separately by the caller, i.e. it
> burdens the caller with an implementation detail.
> >
> > Any suggestions?
>
> Can you share branch and how to test?
>

QEMU branch: https://github.com/shentok/qemu/tree/e500-flash

How to test:
1. `git clone -b e500 https://github.com/shentok/buildroot.git`
2. `cd buildroot`
3. `make qemu_ppc_e500mc_defconfig`
4. `make`
5. `cd output/images`
6. `dd if=/dev/zero of=root.img bs=1M count=64 && dd if=rootfs.ext2
of=root.img bs=1M conv=notrunc`
7. `qemu-system-ppc -M ppce500 -cpu e500mc -m 256 -kernel uImage -append
"console=ttyS0 rootwait root=/dev/mmcblk0" -device sd-card,drive=mydrive
-drive id=mydrive,if=none,file=root.img,format=raw`

Note that step 6 might be required every time before qemu-system-ppc is
started, otherwise this may cause an fsck. The output on the boot console
will look something along these lines (note that no errors are reported):

  Memory CAM mapping: 16/16/16/16/64/64/64 Mb, residual: 0Mb
  Activating Kernel Userspace Access Protection
  Activating Kernel Userspace Execution Prevention
  Linux version 5.17.7 (zcone-pisint@osoxes)
(powerpc-buildroot-linux-gnu-gcc.br_real (Buildroot
2022.08-655-gf8a0d1480a) 11.3.0, GNU ld (GNU Binutils) 2.38) #1 SMP Sat Oct
29 12:49:54 CEST 2022
  Using QEMU e500 machine description
  printk: bootconsole [udbg0] enabled
  CPU maps initialized for 1 thread per core
  -----------------------------------------------------
  phys_mem_size     = 0x10000000
  dcache_bsize      = 0x40
  icache_bsize      = 0x40
  cpu_features      = 0x0000000000000194
    possible        = 0x000000000001039c
    always          = 0x0000000000000100
  cpu_user_features = 0x8c008000 0x08000000
  mmu_features      = 0x000a0010
  -----------------------------------------------------
  qemu_e500_setup_arch()
  barrier-nospec: using isync; sync as speculation barrier
  Zone ranges:
    Normal   [mem 0x0000000000000000-0x000000000fffffff]
    HighMem  empty
  Movable zone start for each node
  Early memory node ranges
    node   0: [mem 0x0000000000000000-0x000000000fffffff]
  Initmem setup node 0 [mem 0x0000000000000000-0x000000000fffffff]
  MMU: Allocated 1088 bytes of context maps for 255 contexts
  percpu: Embedded 16 pages/cpu s33804 r8192 d23540 u65536
  Built 1 zonelists, mobility grouping on.  Total pages: 65024
  Kernel command line: console=ttyS0 rootwait root=/dev/mmcblk0 nokaslr
  Unknown kernel command line parameters "nokaslr", will be passed to user
space.
  Dentry cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  Inode-cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
  mem auto-init: stack:off, heap alloc:off, heap free:off
  Kernel virtual memory layout:
    * 0xffa5f000..0xfffff000  : fixmap
    * 0xff800000..0xffa00000  : highmem PTEs
    * 0xd1000000..0xff800000  : vmalloc & ioremap
  Memory: 174608K/262144K available (12680K kernel code, 1080K rwdata,
3552K rodata, 396K init, 238K bss, 87536K reserved, 0K cma-reserved, 0K
highmem)
  SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  rcu: Hierarchical RCU implementation.
  rcu: RCU event tracing is enabled.
  rcu: RCU restricting CPUs from NR_CPUS=24 to nr_cpu_ids=1.
  rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
  rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  NR_IRQS: 512, nr_irqs: 512, preallocated irqs: 16
  mpic: Setting up MPIC " OpenPIC  " version 1.2 at fe0040000, max 1 CPUs
  mpic: ISU size: 256, shift: 8, mask: ff
  mpic: Initializing for 256 sources
  random: get_random_u32 called from start_kernel+0x524/0x6b0 with
crng_init=0
  clocksource: timebase: mask: 0xffffffffffffffff max_cycles: 0x5c4093a7d1,
max_idle_ns: 440795210635 ns
  clocksource: timebase mult[2800000] shift[24] registered
  Console: colour dummy device 80x25
  pid_max: default: 32768 minimum: 301
  Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  e500 family performance monitor hardware support registered
  rcu: Hierarchical SRCU implementation.
  smp: Bringing up secondary CPUs ...
  smp: Brought up 1 node, 1 CPU
  devtmpfs: initialized
  clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff,
max_idle_ns: 7645041785100000 ns
  futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  NET: Registered PF_NETLINK/PF_ROUTE protocol family
  audit: initializing netlink subsys (disabled)

  Found FSL PCI host bridge at 0x0000000fe0008000. Firmware bus number:
0->255
  PCI host bridge /pci@fe0008000 (primary) ranges:
   MEM 0x0000000c00000000..0x0000000c1fffffff -> 0x00000000e0000000
    IO 0x0000000fe1000000..0x0000000fe100ffff -> 0x0000000000000000
  /pci@fe0008000: PCICSRBAR @ 0xdff00000
  setup_pci_atmu: end of DRAM 10000000
  Machine: QEMU ppce500
  SoC family: QorIQ
  SoC ID: svr:0x00000000, Revision: 0.0
  audit: type=2000 audit(0.092:1): state=initialized audit_enabled=0 res=1
  fsl-pamu: fsl_pamu_init: could not find a PAMU node
  software IO TLB: tearing down default memory pool
  PCI: Probing PCI hardware
  fsl-pci fe0008000.pci: PCI host bridge to bus 8000:00
  pci_bus 8000:00: root bus resource [io  0x0000-0xffff]
  pci_bus 8000:00: root bus resource [mem 0xc00000000-0xc1fffffff] (bus
address [0xe0000000-0xffffffff])
  pci_bus 8000:00: root bus resource [bus 00-ff]
  pci_bus 8000:00: busn_res: [bus 00-ff] end is updated to ff
  pci 8000:00:00.0: [1957:0030] type 00 class 0x0b2000
  pci 8000:00:00.0: reg 0x10: [mem 0xdff00000-0xdfffffff]
  pci 8000:00:01.0: [1af4:1000] type 00 class 0x020000
  pci 8000:00:01.0: reg 0x10: [io  0x0000-0x001f]
  pci 8000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
  pci 8000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
  pci 8000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
  pci_bus 8000:00: busn_res: [bus 00-ff] end is updated to 00
  pci 8000:00:01.0: BAR 6: assigned [mem 0xc00000000-0xc0003ffff pref]
  pci 8000:00:01.0: BAR 4: assigned [mem 0xc00040000-0xc00043fff 64bit pref]
  pci 8000:00:01.0: BAR 1: assigned [mem 0xc00044000-0xc00044fff]
  pci 8000:00:01.0: BAR 0: assigned [io  0x1000-0x101f]
  pci_bus 8000:00: resource 4 [io  0x0000-0xffff]
  pci_bus 8000:00: resource 5 [mem 0xc00000000-0xc1fffffff]
  HugeTLB registered 4.00 MiB page size, pre-allocated 0 pages
  HugeTLB registered 16.0 MiB page size, pre-allocated 0 pages
  HugeTLB registered 64.0 MiB page size, pre-allocated 0 pages
  HugeTLB registered 256 MiB page size, pre-allocated 0 pages
  HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
  Freescale Elo series DMA driver
  iommu: Default domain type: Translated
  iommu: DMA domain TLB invalidation policy: strict mode
  vgaarb: loaded
  SCSI subsystem initialized
  usbcore: registered new interface driver usbfs
  usbcore: registered new interface driver hub
  usbcore: registered new device driver usb
  pps_core: LinuxPPS API ver. 1 registered
  pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <
giometti@linux.it>
  PTP clock support registered
  Advanced Linux Sound Architecture Driver Initialized.
  clocksource: Switched to clocksource timebase
  NET: Registered PF_INET protocol family
  IP idents hash table entries: 4096 (order: 3, 32768 bytes, linear)
  tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes,
linear)
  TCP established hash table entries: 2048 (order: 1, 8192 bytes, linear)
  TCP bind hash table entries: 2048 (order: 2, 16384 bytes, linear)
  TCP: Hash tables configured (established 2048 bind 2048)
  UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  NET: Registered PF_UNIX/PF_LOCAL protocol family
  RPC: Registered named UNIX socket transport module.
  RPC: Registered udp transport module.
  RPC: Registered tcp transport module.
  RPC: Registered tcp NFSv4.1 backchannel transport module.
  PCI: CLS 0 bytes, default 64
  workingset: timestamp_bits=30 max_order=16 bucket_order=0
  squashfs: version 4.0 (2009/01/31) Phillip Lougher
  NFS: Registering the id_resolver key type
  Key type id_resolver registered
  Key type id_legacy registered
  Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
  ntfs: driver 2.1.32 [Flags: R/O].
  jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
  io scheduler mq-deadline registered
  io scheduler kyber registered
  virtio-pci 8000:00:01.0: enabling device (0000 -> 0003)
  Serial: 8250/16550 driver, 6 ports, IRQ sharing enabled
  printk: console [ttyS0] disabled
  serial8250.0: ttyS0 at MMIO 0xfe0004500 (irq = 42, base_baud = 25000000)
is a 16550A
  printk: console [ttyS0] enabled
  printk: console [ttyS0] enabled
  printk: bootconsole [udbg0] disabled
  printk: bootconsole [udbg0] disabled
  ePAPR hypervisor byte channel driver
  brd: module loaded
  loop: module loaded
  st: Version 20160209, fixed bufsize 32768, s/g segs 256
  ucc_geth_driver: QE UCC Gigabit Ethernet Controller
  e1000: Intel(R) PRO/1000 Network Driver
  e1000: Copyright (c) 1999-2006 Intel Corporation.
  e1000e: Intel(R) PRO/1000 Network Driver
  e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  igb: Intel(R) Gigabit Ethernet Network Driver
  igb: Copyright (c) 2007-2014 Intel Corporation.
  ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
  ehci-pci: EHCI PCI platform driver
  ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
  ohci-pci: OHCI PCI platform driver
  ehci-fsl: Freescale EHCI Host controller driver
  usbcore: registered new interface driver usb-storage
  i2c_dev: i2c /dev entries driver
  mpc-i2c fe0003000.i2c: timeout 1000000 us
  rtc-ds1307 0-0068: registered as rtc0
  rtc-ds1307 0-0068: setting system clock to 2022-10-30T11:27:44 UTC
(1667129264)
  sdhci: Secure Digital Host Controller Interface driver
  sdhci: Copyright(c) Pierre Ossman
  sdhci-pltfm: SDHCI platform and OF driver helper
  Freescale hypervisor management driver
  fsl-hv: no hypervisor found
  mmc0 bounce up to 128 segments into one, max segment size 65536 bytes
  ipip: IPv4 and MPLS over IPv4 tunneling driver
  Initializing XFRM netlink socket
  NET: Registered PF_INET6 protocol family
  Segment Routing with IPv6
  In-situ OAM (IOAM) with IPv6
  sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  NET: Registered PF_PACKET protocol family
  NET: Registered PF_KEY protocol family
  Key type dns_resolver registered
  drmem: No dynamic reconfiguration memory found
  mmc0: SDHCI controller on fe002e000.sdhc [fe002e000.sdhc] using DMA
  ALSA device list:
    No soundcards found.
  Waiting for root device /dev/mmcblk0...
  mmc0: new high speed SD card at address 4567
  mmcblk0: mmc0:4567 QEMU! 64.0 MiB
  EXT4-fs (mmcblk0): mounted filesystem without journal. Quota mode:
disabled.
  VFS: Mounted root (ext4 filesystem) readonly on device 179:0.
  devtmpfs: mounted
  Freeing unused kernel image (initmem) memory: 396K
  Run /sbin/init as init process
  EXT4-fs (mmcblk0): re-mounted. Quota mode: disabled.
  Starting syslogd: OK
  Starting klogd: OK
  Running sysctl: OK
  Saving random seed: random: dd: uninitialized urandom read (512 bytes
read)
  OK
  Starting network: udhcpc: started, v1.35.0
  udhcpc: broadcasting discover
  udhcpc: broadcasting select for 10.0.2.15, server 10.0.2.2
  random: fast init done
  udhcpc: lease of 10.0.2.15 obtained from 10.0.2.2, lease time 86400
  deleting routers
  adding dns 10.0.2.3
  OK

  Welcome to Buildroot
  buildroot login:


Best regards,
Bernhard

[-- Attachment #2: Type: text/html, Size: 21064 bytes --]

  reply	other threads:[~2022-10-30 11:47 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-18 21:01 [PATCH v4 0/7] ppc/e500: Add support for two types of flash, cleanup Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 1/7] docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s) Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 2/7] hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power of two Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 3/7] hw/sd/sdhci-internal: Unexport ESDHC defines Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 4/7] hw/sd/sdhci: Rename ESDHC_* defines to USDHC_* Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 5/7] hw/ppc/e500: Implement pflash handling Bernhard Beschow
2022-10-26 17:03   ` Daniel Henrique Barboza
2022-10-27 21:11   ` Philippe Mathieu-Daudé
2022-10-28 15:09   ` Daniel Henrique Barboza
2022-10-28 16:03     ` B
2022-10-28 22:42     ` Philippe Mathieu-Daudé
2022-10-29  9:29       ` Daniel Henrique Barboza
2022-10-29 11:24         ` Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 6/7] hw/sd/sdhci: Implement Freescale eSDHC device model Bernhard Beschow
2022-10-27 21:40   ` Philippe Mathieu-Daudé
2022-10-29 11:33     ` Bernhard Beschow
2022-10-29 13:04       ` Bernhard Beschow
2022-10-29 18:28         ` Bernhard Beschow
2022-10-29 23:10           ` Philippe Mathieu-Daudé
2022-10-30 11:46             ` Bernhard Beschow [this message]
2022-10-31 12:11               ` Philippe Mathieu-Daudé
2022-11-01 10:49                 ` Bernhard Beschow
2022-12-16 14:38                   ` Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 7/7] hw/ppc/e500: Add Freescale eSDHC to e500plat Bernhard Beschow
2022-10-26 17:11   ` Daniel Henrique Barboza
2022-10-27 21:12   ` Philippe Mathieu-Daudé
2022-10-23  8:36 ` [PATCH v4 0/7] ppc/e500: Add support for two types of flash, cleanup Bernhard Beschow
2022-10-26 17:18 ` Daniel Henrique Barboza
2022-10-26 19:51   ` B
2022-10-26 21:40     ` Daniel Henrique Barboza
2022-10-31 12:13   ` Philippe Mathieu-Daudé

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