From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Bernhard Beschow <shentey@gmail.com>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, "Aurelien Jarno" <aurelien@aurel32.net>,
"Yoshinori Sato" <ysato@users.sourceforge.jp>,
"Antony Pavlov" <antonynpavlov@gmail.com>,
"BALATON Zoltan" <balaton@eik.bme.hu>,
"Alistair Francis" <alistair@alistair23.me>,
"Bin Meng" <bin.meng@windriver.com>,
"Kevin Wolf" <kwolf@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jan Kiszka" <jan.kiszka@web.de>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Hanna Reitz" <hreitz@redhat.com>,
qemu-arm@nongnu.org, "Magnus Damm" <magnus.damm@gmail.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
qemu-block@nongnu.org
Subject: Re: [PATCH v4 6/7] hw/sd/sdhci: Implement Freescale eSDHC device model
Date: Thu, 27 Oct 2022 23:40:01 +0200 [thread overview]
Message-ID: <f9dd1e1e-65b6-c74d-d957-43774393c2a4@linaro.org> (raw)
In-Reply-To: <20221018210146.193159-7-shentey@gmail.com>
Hi Bernhard,
On 18/10/22 23:01, Bernhard Beschow wrote:
> Will allow e500 boards to access SD cards using just their own devices.
>
> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> ---
> hw/sd/sdhci.c | 120 +++++++++++++++++++++++++++++++++++++++++-
> include/hw/sd/sdhci.h | 3 ++
> 2 files changed, 122 insertions(+), 1 deletion(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 306070c872..8d8ad9ff24 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -1369,6 +1369,7 @@ void sdhci_initfn(SDHCIState *s)
> s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
>
> s->io_ops = &sdhci_mmio_ops;
> + s->io_registers_map_size = SDHC_REGISTERS_MAP_SIZE;
> }
>
> void sdhci_uninitfn(SDHCIState *s)
> @@ -1392,7 +1393,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp)
> s->fifo_buffer = g_malloc0(s->buf_maxsz);
>
> memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci",
> - SDHC_REGISTERS_MAP_SIZE);
> + s->io_registers_map_size);
I don't think we want to change this region size. [see below]
> void sdhci_common_unrealize(SDHCIState *s)
> @@ -1575,6 +1576,122 @@ static const TypeInfo sdhci_bus_info = {
> .class_init = sdhci_bus_class_init,
> };
>
> +/* --- qdev Freescale eSDHC --- */
> +
> +/* Watermark Level Register */
> +#define ESDHC_WML 0x44
> +
> +/* Control Register for DMA transfer */
> +#define ESDHC_DMA_SYSCTL 0x40c
> +
> +#define ESDHC_REGISTERS_MAP_SIZE 0x410
My preferred approach would be to create a container region with a
size of ESDHC_REGISTERS_MAP_SIZE. Map the SDHC_REGISTERS_MAP region
in the container at offset 0, priority -1. Add 2 register regions
for ESDHC_WML and ESDHC_DMA_SYSCTL, and map them with priority 1 in
the container. ...
> +static uint64_t esdhci_read(void *opaque, hwaddr offset, unsigned size)
> +{
> + uint64_t ret;
> +
> + switch (offset) {
> + case SDHC_SYSAD:
> + case SDHC_BLKSIZE:
> + case SDHC_ARGUMENT:
> + case SDHC_TRNMOD:
> + case SDHC_RSPREG0:
> + case SDHC_RSPREG1:
> + case SDHC_RSPREG2:
> + case SDHC_RSPREG3:
> + case SDHC_BDATA:
> + case SDHC_PRNSTS:
> + case SDHC_HOSTCTL:
> + case SDHC_CLKCON:
> + case SDHC_NORINTSTS:
> + case SDHC_NORINTSTSEN:
> + case SDHC_NORINTSIGEN:
> + case SDHC_ACMD12ERRSTS:
> + case SDHC_CAPAB:
> + case SDHC_SLOT_INT_STATUS:
> + ret = sdhci_read(opaque, offset, size);
> + break;
... Then you don't need these cases.
> + case ESDHC_WML:
> + case ESDHC_DMA_SYSCTL:
> + ret = 0;
> + qemu_log_mask(LOG_UNIMP, "ESDHC rd @0x%02" HWADDR_PRIx
> + " not implemented\n", offset);
But then I realize you only treat these 2 registers as UNIMP.
So now, I'd create 1 UNIMP region for ESDHC_WML and map it
into SDHC_REGISTERS_MAP (s->iomem) with priority 1, and add
another UNIMP region of ESDHC_REGISTERS_MAP_SIZE -
SDHC_REGISTERS_MAP_SIZE (= 0x310) and map it normally at offset
0x100 (SDHC_REGISTERS_MAP_SIZE). Look at create_unimp() in
hw/arm/bcm2835_peripherals.c.
But the ESDHC_WML register has address 0x44 and fits inside the
SDHC_REGISTERS_MAP region, so likely belong there. 0x44 is the
upper part of the SDHC_CAPAB register. These bits are undefined
on the spec v2, which I see you are setting in esdhci_init().
So this register should already return 0, otherwise we have
a bug. Thus we don't need to handle this ESDHC_WML particularly.
And your model is reduced to handling create_unimp() in esdhci_realize().
Am I missing something?
Regards,
Phil.
next prev parent reply other threads:[~2022-10-27 21:42 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-18 21:01 [PATCH v4 0/7] ppc/e500: Add support for two types of flash, cleanup Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 1/7] docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s) Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 2/7] hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power of two Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 3/7] hw/sd/sdhci-internal: Unexport ESDHC defines Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 4/7] hw/sd/sdhci: Rename ESDHC_* defines to USDHC_* Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 5/7] hw/ppc/e500: Implement pflash handling Bernhard Beschow
2022-10-26 17:03 ` Daniel Henrique Barboza
2022-10-27 21:11 ` Philippe Mathieu-Daudé
2022-10-28 15:09 ` Daniel Henrique Barboza
2022-10-28 16:03 ` B
2022-10-28 22:42 ` Philippe Mathieu-Daudé
2022-10-29 9:29 ` Daniel Henrique Barboza
2022-10-29 11:24 ` Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 6/7] hw/sd/sdhci: Implement Freescale eSDHC device model Bernhard Beschow
2022-10-27 21:40 ` Philippe Mathieu-Daudé [this message]
2022-10-29 11:33 ` Bernhard Beschow
2022-10-29 13:04 ` Bernhard Beschow
2022-10-29 18:28 ` Bernhard Beschow
2022-10-29 23:10 ` Philippe Mathieu-Daudé
2022-10-30 11:46 ` Bernhard Beschow
2022-10-31 12:11 ` Philippe Mathieu-Daudé
2022-11-01 10:49 ` Bernhard Beschow
2022-12-16 14:38 ` Bernhard Beschow
2022-10-18 21:01 ` [PATCH v4 7/7] hw/ppc/e500: Add Freescale eSDHC to e500plat Bernhard Beschow
2022-10-26 17:11 ` Daniel Henrique Barboza
2022-10-27 21:12 ` Philippe Mathieu-Daudé
2022-10-23 8:36 ` [PATCH v4 0/7] ppc/e500: Add support for two types of flash, cleanup Bernhard Beschow
2022-10-26 17:18 ` Daniel Henrique Barboza
2022-10-26 19:51 ` B
2022-10-26 21:40 ` Daniel Henrique Barboza
2022-10-31 12:13 ` Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f9dd1e1e-65b6-c74d-d957-43774393c2a4@linaro.org \
--to=philmd@linaro.org \
--cc=alistair@alistair23.me \
--cc=antonynpavlov@gmail.com \
--cc=aurelien@aurel32.net \
--cc=balaton@eik.bme.hu \
--cc=bin.meng@windriver.com \
--cc=edgar.iglesias@gmail.com \
--cc=f4bug@amsat.org \
--cc=hreitz@redhat.com \
--cc=jan.kiszka@web.de \
--cc=kwolf@redhat.com \
--cc=magnus.damm@gmail.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-block@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=shentey@gmail.com \
--cc=ysato@users.sourceforge.jp \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).