* [PULL 00/17] x86 queue, 2020-12-17
@ 2020-12-17 18:46 Eduardo Habkost
2020-12-17 18:46 ` [PULL 01/17] i386: move kvm accel files into kvm/ Eduardo Habkost
` (17 more replies)
0 siblings, 18 replies; 26+ messages in thread
From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, Eduardo Habkost, Richard Henderson
Note that this is using my new gitlab.com repository URL, which
was updated on commit f953c100693d ("MAINTAINERS: Update my git
repository URLs").
The following changes since commit af3f37319cb1e1ca0c42842ecdbd1bcfc64a4b6f:
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-12-15 21:24:31 +0000)
are available in the Git repository at:
https://gitlab.com/ehabkost/qemu.git tags/x86-next-pull-request
for you to fetch changes up to 9fb75013d864489a91ba05e6009ed79c250d4064:
cpu: Remove unnecessary noop methods (2020-12-16 15:50:33 -0500)
----------------------------------------------------------------
x86 queue, 2020-12-17
Features:
* AVX512_FP16 feature (Cathy Zhang)
Cleanups:
* accel code cleanup (Claudio Fontana)
* hyperv initialization cleanup (Vitaly Kuznetsov)
----------------------------------------------------------------
Cathy Zhang (1):
x86/cpu: Add AVX512_FP16 cpu feature
Claudio Fontana (8):
i386: move kvm accel files into kvm/
i386: move whpx accel files into whpx/
i386: move hax accel files into hax/
i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
i386: move TCG accel files into tcg/
i386: move cpu dump out of helper.c into cpu-dump.c
i386: move TCG cpu class initialization to tcg/
i386: tcg: remove inline from cpu_load_eflags
Eduardo Habkost (4):
tcg: cpu_exec_{enter,exit} helpers
tcg: make CPUClass.cpu_exec_* optional
tcg: Make CPUClass.debug_excp_handler optional
cpu: Remove unnecessary noop methods
Vitaly Kuznetsov (4):
i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()
i386: move hyperv_interface_id initialization to x86_cpu_realizefn()
i386: move hyperv_version_id initialization to x86_cpu_realizefn()
i386: move hyperv_limits initialization to x86_cpu_realizefn()
hw/core/cpu.c | 13 -
target/i386/cpu.h | 97 +---
target/i386/{ => hax}/hax-cpus.h | 0
target/i386/{ => hax}/hax-i386.h | 6 +-
target/i386/{ => hax}/hax-interface.h | 0
target/i386/{ => hax}/hax-posix.h | 0
target/i386/{ => hax}/hax-windows.h | 0
target/i386/{ => kvm}/hyperv-proto.h | 0
target/i386/{ => kvm}/hyperv.h | 0
target/i386/{ => kvm}/kvm_i386.h | 0
target/i386/kvm/trace.h | 1 +
target/i386/{ => tcg}/cc_helper_template.h | 0
target/i386/tcg/helper-tcg.h | 95 ++++
target/i386/tcg/tcg-cpu.h | 15 +
target/i386/{ => whpx}/whp-dispatch.h | 0
target/i386/{ => whpx}/whpx-cpus.h | 0
MAINTAINERS | 11 +-
accel/tcg/cpu-exec.c | 34 +-
hw/i386/fw_cfg.c | 2 +-
hw/i386/intel_iommu.c | 2 +-
hw/i386/kvm/apic.c | 2 +-
hw/i386/kvm/clock.c | 2 +-
hw/i386/microvm.c | 2 +-
hw/i386/pc.c | 2 +-
hw/i386/x86.c | 2 +-
meson.build | 1 +
target/i386/cpu-dump.c | 537 ++++++++++++++++++++
target/i386/cpu.c | 75 ++-
target/i386/{ => hax}/hax-all.c | 0
target/i386/{ => hax}/hax-cpus.c | 0
target/i386/{ => hax}/hax-mem.c | 0
target/i386/{ => hax}/hax-posix.c | 0
target/i386/{ => hax}/hax-windows.c | 0
target/i386/hax/meson.build | 7 +
target/i386/helper.c | 539 +--------------------
target/i386/{ => kvm}/hyperv-stub.c | 0
target/i386/{ => kvm}/hyperv.c | 0
target/i386/{ => kvm}/kvm-stub.c | 0
target/i386/{ => kvm}/kvm.c | 70 ++-
target/i386/kvm/meson.build | 3 +
target/i386/kvm/trace-events | 7 +
target/i386/machine.c | 4 +-
target/i386/meson.build | 33 +-
target/i386/{ => tcg}/bpt_helper.c | 1 +
target/i386/{ => tcg}/cc_helper.c | 1 +
target/i386/{ => tcg}/excp_helper.c | 1 +
target/i386/{ => tcg}/fpu_helper.c | 39 +-
target/i386/{ => tcg}/int_helper.c | 1 +
target/i386/{ => tcg}/mem_helper.c | 1 +
target/i386/tcg/meson.build | 14 +
target/i386/{ => tcg}/misc_helper.c | 14 +
target/i386/{ => tcg}/mpx_helper.c | 1 +
target/i386/{ => tcg}/seg_helper.c | 1 +
target/i386/{ => tcg}/smm_helper.c | 2 +
target/i386/{ => tcg}/svm_helper.c | 1 +
target/i386/tcg/tcg-cpu.c | 71 +++
target/i386/{ => tcg}/tcg-stub.c | 0
target/i386/{ => tcg}/translate.c | 1 +
target/i386/trace-events | 6 -
target/i386/whpx/meson.build | 5 +
target/i386/{ => whpx}/whpx-all.c | 0
target/i386/{ => whpx}/whpx-apic.c | 0
target/i386/{ => whpx}/whpx-cpus.c | 0
63 files changed, 956 insertions(+), 766 deletions(-)
rename target/i386/{ => hax}/hax-cpus.h (100%)
rename target/i386/{ => hax}/hax-i386.h (95%)
rename target/i386/{ => hax}/hax-interface.h (100%)
rename target/i386/{ => hax}/hax-posix.h (100%)
rename target/i386/{ => hax}/hax-windows.h (100%)
rename target/i386/{ => kvm}/hyperv-proto.h (100%)
rename target/i386/{ => kvm}/hyperv.h (100%)
rename target/i386/{ => kvm}/kvm_i386.h (100%)
create mode 100644 target/i386/kvm/trace.h
rename target/i386/{ => tcg}/cc_helper_template.h (100%)
create mode 100644 target/i386/tcg/helper-tcg.h
create mode 100644 target/i386/tcg/tcg-cpu.h
rename target/i386/{ => whpx}/whp-dispatch.h (100%)
rename target/i386/{ => whpx}/whpx-cpus.h (100%)
create mode 100644 target/i386/cpu-dump.c
rename target/i386/{ => hax}/hax-all.c (100%)
rename target/i386/{ => hax}/hax-cpus.c (100%)
rename target/i386/{ => hax}/hax-mem.c (100%)
rename target/i386/{ => hax}/hax-posix.c (100%)
rename target/i386/{ => hax}/hax-windows.c (100%)
create mode 100644 target/i386/hax/meson.build
rename target/i386/{ => kvm}/hyperv-stub.c (100%)
rename target/i386/{ => kvm}/hyperv.c (100%)
rename target/i386/{ => kvm}/kvm-stub.c (100%)
rename target/i386/{ => kvm}/kvm.c (98%)
create mode 100644 target/i386/kvm/meson.build
create mode 100644 target/i386/kvm/trace-events
rename target/i386/{ => tcg}/bpt_helper.c (99%)
rename target/i386/{ => tcg}/cc_helper.c (99%)
rename target/i386/{ => tcg}/excp_helper.c (99%)
rename target/i386/{ => tcg}/fpu_helper.c (99%)
rename target/i386/{ => tcg}/int_helper.c (99%)
rename target/i386/{ => tcg}/mem_helper.c (99%)
create mode 100644 target/i386/tcg/meson.build
rename target/i386/{ => tcg}/misc_helper.c (97%)
rename target/i386/{ => tcg}/mpx_helper.c (99%)
rename target/i386/{ => tcg}/seg_helper.c (99%)
rename target/i386/{ => tcg}/smm_helper.c (99%)
rename target/i386/{ => tcg}/svm_helper.c (99%)
create mode 100644 target/i386/tcg/tcg-cpu.c
rename target/i386/{ => tcg}/tcg-stub.c (100%)
rename target/i386/{ => tcg}/translate.c (99%)
create mode 100644 target/i386/whpx/meson.build
rename target/i386/{ => whpx}/whpx-all.c (100%)
rename target/i386/{ => whpx}/whpx-apic.c (100%)
rename target/i386/{ => whpx}/whpx-cpus.c (100%)
--
2.28.0
^ permalink raw reply [flat|nested] 26+ messages in thread* [PULL 01/17] i386: move kvm accel files into kvm/ 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 02/17] i386: move whpx accel files into whpx/ Eduardo Habkost ` (16 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Eduardo Habkost, Richard Henderson, Claudio Fontana, Paolo Bonzini, Alex Bennée, Richard Henderson From: Claudio Fontana <cfontana@suse.de> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-2-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.h | 2 +- target/i386/{ => kvm}/hyperv-proto.h | 0 target/i386/{ => kvm}/hyperv.h | 0 target/i386/{ => kvm}/kvm_i386.h | 0 target/i386/kvm/trace.h | 1 + MAINTAINERS | 2 +- hw/i386/fw_cfg.c | 2 +- hw/i386/intel_iommu.c | 2 +- hw/i386/kvm/apic.c | 2 +- hw/i386/kvm/clock.c | 2 +- hw/i386/microvm.c | 2 +- hw/i386/pc.c | 2 +- hw/i386/x86.c | 2 +- meson.build | 1 + target/i386/cpu.c | 2 +- target/i386/helper.c | 2 +- target/i386/{ => kvm}/hyperv-stub.c | 0 target/i386/{ => kvm}/hyperv.c | 0 target/i386/{ => kvm}/kvm-stub.c | 0 target/i386/{ => kvm}/kvm.c | 0 target/i386/kvm/meson.build | 3 +++ target/i386/kvm/trace-events | 7 +++++++ target/i386/machine.c | 4 ++-- target/i386/meson.build | 4 +--- target/i386/trace-events | 6 ------ 25 files changed, 26 insertions(+), 22 deletions(-) rename target/i386/{ => kvm}/hyperv-proto.h (100%) rename target/i386/{ => kvm}/hyperv.h (100%) rename target/i386/{ => kvm}/kvm_i386.h (100%) create mode 100644 target/i386/kvm/trace.h rename target/i386/{ => kvm}/hyperv-stub.c (100%) rename target/i386/{ => kvm}/hyperv.c (100%) rename target/i386/{ => kvm}/kvm-stub.c (100%) rename target/i386/{ => kvm}/kvm.c (100%) create mode 100644 target/i386/kvm/meson.build create mode 100644 target/i386/kvm/trace-events diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c4a49c06a8..d6bb053837 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -22,7 +22,7 @@ #include "sysemu/tcg.h" #include "cpu-qom.h" -#include "hyperv-proto.h" +#include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" diff --git a/target/i386/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h similarity index 100% rename from target/i386/hyperv-proto.h rename to target/i386/kvm/hyperv-proto.h diff --git a/target/i386/hyperv.h b/target/i386/kvm/hyperv.h similarity index 100% rename from target/i386/hyperv.h rename to target/i386/kvm/hyperv.h diff --git a/target/i386/kvm_i386.h b/target/i386/kvm/kvm_i386.h similarity index 100% rename from target/i386/kvm_i386.h rename to target/i386/kvm/kvm_i386.h diff --git a/target/i386/kvm/trace.h b/target/i386/kvm/trace.h new file mode 100644 index 0000000000..46b75c6942 --- /dev/null +++ b/target/i386/kvm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_i386_kvm.h" diff --git a/MAINTAINERS b/MAINTAINERS index d5ea7fbb8f..a77553833a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -426,7 +426,7 @@ M: Paolo Bonzini <pbonzini@redhat.com> M: Marcelo Tosatti <mtosatti@redhat.com> L: kvm@vger.kernel.org S: Supported -F: target/i386/kvm.c +F: target/i386/kvm/ F: scripts/kvm/vmxcap Guest CPU Cores (other accelerators) diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index b87f0e5070..e48a54fa36 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -21,7 +21,7 @@ #include "hw/timer/hpet.h" #include "hw/nvram/fw_cfg.h" #include "e820_memory_layout.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include CONFIG_DEVICES struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0cc71e4057..b4f5094259 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -37,7 +37,7 @@ #include "sysemu/kvm.h" #include "sysemu/sysemu.h" #include "hw/i386/apic_internal.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "trace.h" diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index b226b674e8..3dbff2be2e 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -17,7 +17,7 @@ #include "hw/pci/msi.h" #include "sysemu/hw_accel.h" #include "sysemu/kvm.h" -#include "target/i386/kvm_i386.h" +#include "kvm/kvm_i386.h" static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic, int reg_id, uint32_t val) diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 24fe5091b6..2d8a366369 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -20,7 +20,7 @@ #include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "sysemu/hw_accel.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "hw/sysbus.h" #include "hw/kvm/clock.h" diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index f111ef87d8..edf2b0f061 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -51,7 +51,7 @@ #include "cpu.h" #include "elf.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "hw/xen/start_info.h" #define MICROVM_QBOOT_FILENAME "qboot.rom" diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 640fb5b0b7..5458f61d10 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -61,7 +61,7 @@ #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "hw/xen/xen.h" #include "hw/xen/start_info.h" #include "ui/qemu-spice.h" diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 49e1d419b2..6329f90ef9 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -54,7 +54,7 @@ #include "elf.h" #include "standard-headers/asm-x86/bootparam.h" #include CONFIG_DEVICES -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" /* Physical Address of PVH entry point read from kernel ELF NOTE */ static size_t pvh_start_addr; diff --git a/meson.build b/meson.build index fba6413056..372576f82c 100644 --- a/meson.build +++ b/meson.build @@ -1497,6 +1497,7 @@ trace_events_subdirs += [ 'target/arm', 'target/hppa', 'target/i386', + 'target/i386/kvm', 'target/mips', 'target/ppc', 'target/riscv', diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ca997a68cd..77f0e44df8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -31,7 +31,7 @@ #include "sysemu/cpus.h" #include "sysemu/xen.h" #include "sysemu/whpx.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "sev_i386.h" #include "qemu/error-report.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 034f46bcc2..a1b3367ab2 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -24,7 +24,7 @@ #include "qemu/qemu-print.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" diff --git a/target/i386/hyperv-stub.c b/target/i386/kvm/hyperv-stub.c similarity index 100% rename from target/i386/hyperv-stub.c rename to target/i386/kvm/hyperv-stub.c diff --git a/target/i386/hyperv.c b/target/i386/kvm/hyperv.c similarity index 100% rename from target/i386/hyperv.c rename to target/i386/kvm/hyperv.c diff --git a/target/i386/kvm-stub.c b/target/i386/kvm/kvm-stub.c similarity index 100% rename from target/i386/kvm-stub.c rename to target/i386/kvm/kvm-stub.c diff --git a/target/i386/kvm.c b/target/i386/kvm/kvm.c similarity index 100% rename from target/i386/kvm.c rename to target/i386/kvm/kvm.c diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build new file mode 100644 index 0000000000..1d66559187 --- /dev/null +++ b/target/i386/kvm/meson.build @@ -0,0 +1,3 @@ +i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) +i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) +i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c')) diff --git a/target/i386/kvm/trace-events b/target/i386/kvm/trace-events new file mode 100644 index 0000000000..b4e2d9e4ea --- /dev/null +++ b/target/i386/kvm/trace-events @@ -0,0 +1,7 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# kvm.c +kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI %" PRIu32 +kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d" +kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d" +kvm_x86_update_msi_routes(int num) "Updated %d MSI routes" diff --git a/target/i386/machine.c b/target/i386/machine.c index 233e46bb70..1614e8c2f8 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -3,9 +3,9 @@ #include "exec/exec-all.h" #include "hw/isa/isa.h" #include "migration/cpu.h" -#include "hyperv.h" +#include "kvm/hyperv.h" #include "hw/i386/x86.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "sysemu/kvm.h" #include "sysemu/tcg.h" diff --git a/target/i386/meson.build b/target/i386/meson.build index fc3ee80386..5363757131 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -18,7 +18,6 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files( 'smm_helper.c', 'svm_helper.c', 'translate.c'), if_false: files('tcg-stub.c')) -i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c')) i386_softmmu_ss = ss.source_set() @@ -28,8 +27,6 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c')) -i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', 'whpx-cpus.c', @@ -43,6 +40,7 @@ i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c')) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c')) +subdir('kvm') subdir('hvf') target_arch += {'i386': i386_ss} diff --git a/target/i386/trace-events b/target/i386/trace-events index 246158ae1f..a22ab24e21 100644 --- a/target/i386/trace-events +++ b/target/i386/trace-events @@ -1,11 +1,5 @@ # See docs/devel/tracing.txt for syntax documentation. -# kvm.c -kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI %" PRIu32 -kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d" -kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d" -kvm_x86_update_msi_routes(int num) "Updated %d MSI routes" - # sev.c kvm_sev_init(void) "" kvm_memcrypt_register_region(void *addr, size_t len) "addr %p len 0x%zx" -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 02/17] i386: move whpx accel files into whpx/ 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost 2020-12-17 18:46 ` [PULL 01/17] i386: move kvm accel files into kvm/ Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 03/17] i386: move hax accel files into hax/ Eduardo Habkost ` (15 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Eduardo Habkost, Richard Henderson, Claudio Fontana, Paolo Bonzini, Alex Bennée, Richard Henderson From: Claudio Fontana <cfontana@suse.de> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-3-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/{ => whpx}/whp-dispatch.h | 0 target/i386/{ => whpx}/whpx-cpus.h | 0 MAINTAINERS | 6 +----- target/i386/meson.build | 6 +----- target/i386/whpx/meson.build | 5 +++++ target/i386/{ => whpx}/whpx-all.c | 0 target/i386/{ => whpx}/whpx-apic.c | 0 target/i386/{ => whpx}/whpx-cpus.c | 0 8 files changed, 7 insertions(+), 10 deletions(-) rename target/i386/{ => whpx}/whp-dispatch.h (100%) rename target/i386/{ => whpx}/whpx-cpus.h (100%) create mode 100644 target/i386/whpx/meson.build rename target/i386/{ => whpx}/whpx-all.c (100%) rename target/i386/{ => whpx}/whpx-apic.c (100%) rename target/i386/{ => whpx}/whpx-cpus.c (100%) diff --git a/target/i386/whp-dispatch.h b/target/i386/whpx/whp-dispatch.h similarity index 100% rename from target/i386/whp-dispatch.h rename to target/i386/whpx/whp-dispatch.h diff --git a/target/i386/whpx-cpus.h b/target/i386/whpx/whpx-cpus.h similarity index 100% rename from target/i386/whpx-cpus.h rename to target/i386/whpx/whpx-cpus.h diff --git a/MAINTAINERS b/MAINTAINERS index a77553833a..6f29b37834 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -452,11 +452,7 @@ F: include/sysemu/hvf.h WHPX CPUs M: Sunil Muthuswamy <sunilmut@microsoft.com> S: Supported -F: target/i386/whpx-all.c -F: target/i386/whpx-apic.c -F: target/i386/whpx-cpus.c -F: target/i386/whp-dispatch.h -F: accel/stubs/whpx-stub.c +F: target/i386/whpx/ F: include/sysemu/whpx.h Guest CPU Cores (Xen) diff --git a/target/i386/meson.build b/target/i386/meson.build index 5363757131..62cd042915 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -27,11 +27,6 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( - 'whpx-all.c', - 'whpx-cpus.c', - 'whpx-apic.c', -)) i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( 'hax-all.c', 'hax-mem.c', @@ -41,6 +36,7 @@ i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-po i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c')) subdir('kvm') +subdir('whpx') subdir('hvf') target_arch += {'i386': i386_ss} diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build new file mode 100644 index 0000000000..d8aa683999 --- /dev/null +++ b/target/i386/whpx/meson.build @@ -0,0 +1,5 @@ +i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( + 'whpx-all.c', + 'whpx-apic.c', + 'whpx-cpus.c', +)) diff --git a/target/i386/whpx-all.c b/target/i386/whpx/whpx-all.c similarity index 100% rename from target/i386/whpx-all.c rename to target/i386/whpx/whpx-all.c diff --git a/target/i386/whpx-apic.c b/target/i386/whpx/whpx-apic.c similarity index 100% rename from target/i386/whpx-apic.c rename to target/i386/whpx/whpx-apic.c diff --git a/target/i386/whpx-cpus.c b/target/i386/whpx/whpx-cpus.c similarity index 100% rename from target/i386/whpx-cpus.c rename to target/i386/whpx/whpx-cpus.c -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 03/17] i386: move hax accel files into hax/ 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost 2020-12-17 18:46 ` [PULL 01/17] i386: move kvm accel files into kvm/ Eduardo Habkost 2020-12-17 18:46 ` [PULL 02/17] i386: move whpx accel files into whpx/ Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 04/17] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Eduardo Habkost ` (14 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Eduardo Habkost, Richard Henderson, Claudio Fontana, Paolo Bonzini, Alex Bennée, Richard Henderson From: Claudio Fontana <cfontana@suse.de> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-4-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/{ => hax}/hax-cpus.h | 0 target/i386/{ => hax}/hax-i386.h | 6 +++--- target/i386/{ => hax}/hax-interface.h | 0 target/i386/{ => hax}/hax-posix.h | 0 target/i386/{ => hax}/hax-windows.h | 0 MAINTAINERS | 2 +- target/i386/{ => hax}/hax-all.c | 0 target/i386/{ => hax}/hax-cpus.c | 0 target/i386/{ => hax}/hax-mem.c | 0 target/i386/{ => hax}/hax-posix.c | 0 target/i386/{ => hax}/hax-windows.c | 0 target/i386/hax/meson.build | 7 +++++++ target/i386/meson.build | 8 +------- 13 files changed, 12 insertions(+), 11 deletions(-) rename target/i386/{ => hax}/hax-cpus.h (100%) rename target/i386/{ => hax}/hax-i386.h (95%) rename target/i386/{ => hax}/hax-interface.h (100%) rename target/i386/{ => hax}/hax-posix.h (100%) rename target/i386/{ => hax}/hax-windows.h (100%) rename target/i386/{ => hax}/hax-all.c (100%) rename target/i386/{ => hax}/hax-cpus.c (100%) rename target/i386/{ => hax}/hax-mem.c (100%) rename target/i386/{ => hax}/hax-posix.c (100%) rename target/i386/{ => hax}/hax-windows.c (100%) create mode 100644 target/i386/hax/meson.build diff --git a/target/i386/hax-cpus.h b/target/i386/hax/hax-cpus.h similarity index 100% rename from target/i386/hax-cpus.h rename to target/i386/hax/hax-cpus.h diff --git a/target/i386/hax-i386.h b/target/i386/hax/hax-i386.h similarity index 95% rename from target/i386/hax-i386.h rename to target/i386/hax/hax-i386.h index 48c4abe14e..efbb346238 100644 --- a/target/i386/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -84,13 +84,13 @@ void hax_memory_init(void); #ifdef CONFIG_POSIX -#include "target/i386/hax-posix.h" +#include "hax-posix.h" #endif #ifdef CONFIG_WIN32 -#include "target/i386/hax-windows.h" +#include "hax-windows.h" #endif -#include "target/i386/hax-interface.h" +#include "hax-interface.h" #endif diff --git a/target/i386/hax-interface.h b/target/i386/hax/hax-interface.h similarity index 100% rename from target/i386/hax-interface.h rename to target/i386/hax/hax-interface.h diff --git a/target/i386/hax-posix.h b/target/i386/hax/hax-posix.h similarity index 100% rename from target/i386/hax-posix.h rename to target/i386/hax/hax-posix.h diff --git a/target/i386/hax-windows.h b/target/i386/hax/hax-windows.h similarity index 100% rename from target/i386/hax-windows.h rename to target/i386/hax/hax-windows.h diff --git a/MAINTAINERS b/MAINTAINERS index 6f29b37834..e03615d76c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -492,7 +492,7 @@ W: https://github.com/intel/haxm/issues S: Maintained F: accel/stubs/hax-stub.c F: include/sysemu/hax.h -F: target/i386/hax-* +F: target/i386/hax/ Hosts ----- diff --git a/target/i386/hax-all.c b/target/i386/hax/hax-all.c similarity index 100% rename from target/i386/hax-all.c rename to target/i386/hax/hax-all.c diff --git a/target/i386/hax-cpus.c b/target/i386/hax/hax-cpus.c similarity index 100% rename from target/i386/hax-cpus.c rename to target/i386/hax/hax-cpus.c diff --git a/target/i386/hax-mem.c b/target/i386/hax/hax-mem.c similarity index 100% rename from target/i386/hax-mem.c rename to target/i386/hax/hax-mem.c diff --git a/target/i386/hax-posix.c b/target/i386/hax/hax-posix.c similarity index 100% rename from target/i386/hax-posix.c rename to target/i386/hax/hax-posix.c diff --git a/target/i386/hax-windows.c b/target/i386/hax/hax-windows.c similarity index 100% rename from target/i386/hax-windows.c rename to target/i386/hax/hax-windows.c diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build new file mode 100644 index 0000000000..77ea431b30 --- /dev/null +++ b/target/i386/hax/meson.build @@ -0,0 +1,7 @@ +i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( + 'hax-all.c', + 'hax-mem.c', + 'hax-cpus.c', +)) +i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c')) +i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c')) diff --git a/target/i386/meson.build b/target/i386/meson.build index 62cd042915..284d52ab81 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -27,15 +27,9 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( - 'hax-all.c', - 'hax-mem.c', - 'hax-cpus.c', -)) -i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c')) -i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c')) subdir('kvm') +subdir('hax') subdir('whpx') subdir('hvf') -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 04/17] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (2 preceding siblings ...) 2020-12-17 18:46 ` [PULL 03/17] i386: move hax accel files into hax/ Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 05/17] i386: move TCG accel files into tcg/ Eduardo Habkost ` (13 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Eduardo Habkost, Roman Bolshakov, Claudio Fontana, Paolo Bonzini, Alex Bennée, Richard Henderson From: Claudio Fontana <cfontana@suse.de> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201212155530.23098-5-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index e03615d76c..1e7c8f0488 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -445,7 +445,6 @@ M: Cameron Esfahani <dirty@apple.com> M: Roman Bolshakov <r.bolshakov@yadro.com> W: https://wiki.qemu.org/Features/HVF S: Maintained -F: accel/stubs/hvf-stub.c F: target/i386/hvf/ F: include/sysemu/hvf.h -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 05/17] i386: move TCG accel files into tcg/ 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (3 preceding siblings ...) 2020-12-17 18:46 ` [PULL 04/17] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 06/17] i386: move cpu dump out of helper.c into cpu-dump.c Eduardo Habkost ` (12 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Eduardo Habkost, Richard Henderson, Claudio Fontana, Paolo Bonzini, Alex Bennée, Richard Henderson From: Claudio Fontana <cfontana@suse.de> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: moved cc_helper_template.h to tcg/ too] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20201212155530.23098-6-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/{ => tcg}/cc_helper_template.h | 0 target/i386/meson.build | 14 +------------- target/i386/{ => tcg}/bpt_helper.c | 0 target/i386/{ => tcg}/cc_helper.c | 0 target/i386/{ => tcg}/excp_helper.c | 0 target/i386/{ => tcg}/fpu_helper.c | 0 target/i386/{ => tcg}/int_helper.c | 0 target/i386/{ => tcg}/mem_helper.c | 0 target/i386/tcg/meson.build | 13 +++++++++++++ target/i386/{ => tcg}/misc_helper.c | 0 target/i386/{ => tcg}/mpx_helper.c | 0 target/i386/{ => tcg}/seg_helper.c | 0 target/i386/{ => tcg}/smm_helper.c | 0 target/i386/{ => tcg}/svm_helper.c | 0 target/i386/{ => tcg}/tcg-stub.c | 0 target/i386/{ => tcg}/translate.c | 0 16 files changed, 14 insertions(+), 13 deletions(-) rename target/i386/{ => tcg}/cc_helper_template.h (100%) rename target/i386/{ => tcg}/bpt_helper.c (100%) rename target/i386/{ => tcg}/cc_helper.c (100%) rename target/i386/{ => tcg}/excp_helper.c (100%) rename target/i386/{ => tcg}/fpu_helper.c (100%) rename target/i386/{ => tcg}/int_helper.c (100%) rename target/i386/{ => tcg}/mem_helper.c (100%) create mode 100644 target/i386/tcg/meson.build rename target/i386/{ => tcg}/misc_helper.c (100%) rename target/i386/{ => tcg}/mpx_helper.c (100%) rename target/i386/{ => tcg}/seg_helper.c (100%) rename target/i386/{ => tcg}/smm_helper.c (100%) rename target/i386/{ => tcg}/svm_helper.c (100%) rename target/i386/{ => tcg}/tcg-stub.c (100%) rename target/i386/{ => tcg}/translate.c (100%) diff --git a/target/i386/cc_helper_template.h b/target/i386/tcg/cc_helper_template.h similarity index 100% rename from target/i386/cc_helper_template.h rename to target/i386/tcg/cc_helper_template.h diff --git a/target/i386/meson.build b/target/i386/meson.build index 284d52ab81..750471c9f3 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -5,19 +5,6 @@ i386_ss.add(files( 'helper.c', 'xsave_helper.c', )) -i386_ss.add(when: 'CONFIG_TCG', if_true: files( - 'bpt_helper.c', - 'cc_helper.c', - 'excp_helper.c', - 'fpu_helper.c', - 'int_helper.c', - 'mem_helper.c', - 'misc_helper.c', - 'mpx_helper.c', - 'seg_helper.c', - 'smm_helper.c', - 'svm_helper.c', - 'translate.c'), if_false: files('tcg-stub.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c')) i386_softmmu_ss = ss.source_set() @@ -32,6 +19,7 @@ subdir('kvm') subdir('hax') subdir('whpx') subdir('hvf') +subdir('tcg') target_arch += {'i386': i386_ss} target_softmmu_arch += {'i386': i386_softmmu_ss} diff --git a/target/i386/bpt_helper.c b/target/i386/tcg/bpt_helper.c similarity index 100% rename from target/i386/bpt_helper.c rename to target/i386/tcg/bpt_helper.c diff --git a/target/i386/cc_helper.c b/target/i386/tcg/cc_helper.c similarity index 100% rename from target/i386/cc_helper.c rename to target/i386/tcg/cc_helper.c diff --git a/target/i386/excp_helper.c b/target/i386/tcg/excp_helper.c similarity index 100% rename from target/i386/excp_helper.c rename to target/i386/tcg/excp_helper.c diff --git a/target/i386/fpu_helper.c b/target/i386/tcg/fpu_helper.c similarity index 100% rename from target/i386/fpu_helper.c rename to target/i386/tcg/fpu_helper.c diff --git a/target/i386/int_helper.c b/target/i386/tcg/int_helper.c similarity index 100% rename from target/i386/int_helper.c rename to target/i386/tcg/int_helper.c diff --git a/target/i386/mem_helper.c b/target/i386/tcg/mem_helper.c similarity index 100% rename from target/i386/mem_helper.c rename to target/i386/tcg/mem_helper.c diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build new file mode 100644 index 0000000000..02794226c2 --- /dev/null +++ b/target/i386/tcg/meson.build @@ -0,0 +1,13 @@ +i386_ss.add(when: 'CONFIG_TCG', if_true: files( + 'bpt_helper.c', + 'cc_helper.c', + 'excp_helper.c', + 'fpu_helper.c', + 'int_helper.c', + 'mem_helper.c', + 'misc_helper.c', + 'mpx_helper.c', + 'seg_helper.c', + 'smm_helper.c', + 'svm_helper.c', + 'translate.c'), if_false: files('tcg-stub.c')) diff --git a/target/i386/misc_helper.c b/target/i386/tcg/misc_helper.c similarity index 100% rename from target/i386/misc_helper.c rename to target/i386/tcg/misc_helper.c diff --git a/target/i386/mpx_helper.c b/target/i386/tcg/mpx_helper.c similarity index 100% rename from target/i386/mpx_helper.c rename to target/i386/tcg/mpx_helper.c diff --git a/target/i386/seg_helper.c b/target/i386/tcg/seg_helper.c similarity index 100% rename from target/i386/seg_helper.c rename to target/i386/tcg/seg_helper.c diff --git a/target/i386/smm_helper.c b/target/i386/tcg/smm_helper.c similarity index 100% rename from target/i386/smm_helper.c rename to target/i386/tcg/smm_helper.c diff --git a/target/i386/svm_helper.c b/target/i386/tcg/svm_helper.c similarity index 100% rename from target/i386/svm_helper.c rename to target/i386/tcg/svm_helper.c diff --git a/target/i386/tcg-stub.c b/target/i386/tcg/tcg-stub.c similarity index 100% rename from target/i386/tcg-stub.c rename to target/i386/tcg/tcg-stub.c diff --git a/target/i386/translate.c b/target/i386/tcg/translate.c similarity index 100% rename from target/i386/translate.c rename to target/i386/tcg/translate.c -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 06/17] i386: move cpu dump out of helper.c into cpu-dump.c 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (4 preceding siblings ...) 2020-12-17 18:46 ` [PULL 05/17] i386: move TCG accel files into tcg/ Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() Eduardo Habkost ` (11 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Eduardo Habkost, Richard Henderson, Claudio Fontana, Paolo Bonzini, Alex Bennée, Richard Henderson From: Claudio Fontana <cfontana@suse.de> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-7-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.h | 1 + target/i386/cpu-dump.c | 537 ++++++++++++++++++++++++++++++++++++++++ target/i386/helper.c | 514 -------------------------------------- target/i386/meson.build | 1 + 4 files changed, 539 insertions(+), 514 deletions(-) create mode 100644 target/i386/cpu-dump.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d6bb053837..343e51baab 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2236,6 +2236,7 @@ void enable_compat_apic_id_mode(void); #define APIC_DEFAULT_ADDRESS 0xfee00000 #define APIC_SPACE_SIZE 0x100000 +/* cpu-dump.c */ void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); /* cpu.c */ diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c new file mode 100644 index 0000000000..aac21f1f60 --- /dev/null +++ b/target/i386/cpu-dump.c @@ -0,0 +1,537 @@ +/* + * i386 CPU dump to FILE + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/qemu-print.h" +#ifndef CONFIG_USER_ONLY +#include "hw/i386/apic_internal.h" +#endif + +/***********************************************************/ +/* x86 debug */ + +static const char *cc_op_str[CC_OP_NB] = { + "DYNAMIC", + "EFLAGS", + + "MULB", + "MULW", + "MULL", + "MULQ", + + "ADDB", + "ADDW", + "ADDL", + "ADDQ", + + "ADCB", + "ADCW", + "ADCL", + "ADCQ", + + "SUBB", + "SUBW", + "SUBL", + "SUBQ", + + "SBBB", + "SBBW", + "SBBL", + "SBBQ", + + "LOGICB", + "LOGICW", + "LOGICL", + "LOGICQ", + + "INCB", + "INCW", + "INCL", + "INCQ", + + "DECB", + "DECW", + "DECL", + "DECQ", + + "SHLB", + "SHLW", + "SHLL", + "SHLQ", + + "SARB", + "SARW", + "SARL", + "SARQ", + + "BMILGB", + "BMILGW", + "BMILGL", + "BMILGQ", + + "ADCX", + "ADOX", + "ADCOX", + + "CLR", +}; + +static void +cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, + const char *name, struct SegmentCache *sc) +{ +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name, + sc->selector, sc->base, sc->limit, + sc->flags & 0x00ffff00); + } else +#endif + { + qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector, + (uint32_t)sc->base, sc->limit, + sc->flags & 0x00ffff00); + } + + if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) + goto done; + + qemu_fprintf(f, " DPL=%d ", + (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); + if (sc->flags & DESC_S_MASK) { + if (sc->flags & DESC_CS_MASK) { + qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : + ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); + qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-', + (sc->flags & DESC_R_MASK) ? 'R' : '-'); + } else { + qemu_fprintf(f, (sc->flags & DESC_B_MASK + || env->hflags & HF_LMA_MASK) + ? "DS " : "DS16"); + qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-', + (sc->flags & DESC_W_MASK) ? 'W' : '-'); + } + qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); + } else { + static const char *sys_type_name[2][16] = { + { /* 32 bit mode */ + "Reserved", "TSS16-avl", "LDT", "TSS16-busy", + "CallGate16", "TaskGate", "IntGate16", "TrapGate16", + "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", + "CallGate32", "Reserved", "IntGate32", "TrapGate32" + }, + { /* 64 bit mode */ + "<hiword>", "Reserved", "LDT", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", + "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", + "Reserved", "IntGate64", "TrapGate64" + } + }; + qemu_fprintf(f, "%s", + sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] + [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]); + } +done: + qemu_fprintf(f, "\n"); +} + +#ifndef CONFIG_USER_ONLY + +/* ARRAY_SIZE check is not required because + * DeliveryMode(dm) has a size of 3 bit. + */ +static inline const char *dm2str(uint32_t dm) +{ + static const char *str[] = { + "Fixed", + "...", + "SMI", + "...", + "NMI", + "INIT", + "...", + "ExtINT" + }; + return str[dm]; +} + +static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer) +{ + uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT; + qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s", + name, lvt, + lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi", + lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge", + lvt & APIC_LVT_MASKED ? "masked" : "", + lvt & APIC_LVT_DELIV_STS ? "pending" : "", + !is_timer ? + "" : lvt & APIC_LVT_TIMER_PERIODIC ? + "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ? + "tsc-deadline" : "one-shot", + dm2str(dm)); + if (dm != APIC_DM_NMI) { + qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK); + } else { + qemu_printf("\n"); + } +} + +/* ARRAY_SIZE check is not required because + * destination shorthand has a size of 2 bit. + */ +static inline const char *shorthand2str(uint32_t shorthand) +{ + const char *str[] = { + "no-shorthand", "self", "all-self", "all" + }; + return str[shorthand]; +} + +static inline uint8_t divider_conf(uint32_t divide_conf) +{ + uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3); + + return divide_val == 7 ? 1 : 2 << divide_val; +} + +static inline void mask2str(char *str, uint32_t val, uint8_t size) +{ + while (size--) { + *str++ = (val >> size) & 1 ? '1' : '0'; + } + *str = 0; +} + +#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16 + +static void dump_apic_icr(APICCommonState *s, CPUX86State *env) +{ + uint32_t icr = s->icr[0], icr2 = s->icr[1]; + uint8_t dest_shorthand = \ + (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT; + bool logical_mod = icr & APIC_ICR_DEST_MOD; + char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1]; + uint32_t dest_field; + bool x2apic; + + qemu_printf("ICR\t 0x%08x %s %s %s %s\n", + icr, + logical_mod ? "logical" : "physical", + icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge", + icr & APIC_ICR_LEVEL ? "assert" : "de-assert", + shorthand2str(dest_shorthand)); + + qemu_printf("ICR2\t 0x%08x", icr2); + if (dest_shorthand != 0) { + qemu_printf("\n"); + return; + } + x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; + dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT; + + if (!logical_mod) { + if (x2apic) { + qemu_printf(" cpu %u (X2APIC ID)\n", dest_field); + } else { + qemu_printf(" cpu %u (APIC ID)\n", + dest_field & APIC_LOGDEST_XAPIC_ID); + } + return; + } + + if (s->dest_mode == 0xf) { /* flat mode */ + mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8); + qemu_printf(" mask %s (APIC ID)\n", apic_id_str); + } else if (s->dest_mode == 0) { /* cluster mode */ + if (x2apic) { + mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16); + qemu_printf(" cluster %u mask %s (X2APIC ID)\n", + dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str); + } else { + mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4); + qemu_printf(" cluster %u mask %s (APIC ID)\n", + dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str); + } + } +} + +static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab, + uint32_t *tmr_tab) +{ + int i, empty = true; + + qemu_printf("%s\t ", name); + for (i = 0; i < 256; i++) { + if (apic_get_bit(ireg_tab, i)) { + qemu_printf("%u%s ", i, + apic_get_bit(tmr_tab, i) ? "(level)" : ""); + empty = false; + } + } + qemu_printf("%s\n", empty ? "(none)" : ""); +} + +void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) +{ + X86CPU *cpu = X86_CPU(cs); + APICCommonState *s = APIC_COMMON(cpu->apic_state); + if (!s) { + qemu_printf("local apic state not available\n"); + return; + } + uint32_t *lvt = s->lvt; + + qemu_printf("dumping local APIC state for CPU %-2u\n\n", + CPU(cpu)->cpu_index); + dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false); + dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false); + dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false); + dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false); + dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false); + dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true); + + qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u" + " current_count = %u\n", + s->divide_conf & APIC_DCR_MASK, + divider_conf(s->divide_conf), + s->initial_count, apic_get_current_count(s)); + + qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n", + s->spurious_vec, + s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled", + s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", + s->spurious_vec & APIC_VECTOR_MASK); + + dump_apic_icr(s, &cpu->env); + + qemu_printf("ESR\t 0x%08x\n", s->esr); + + dump_apic_interrupt("ISR", s->isr, s->tmr); + dump_apic_interrupt("IRR", s->irr, s->tmr); + + qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x", + s->arb_id, s->tpr, s->dest_mode, s->log_dest); + if (s->dest_mode == 0) { + qemu_printf("(cluster %u: id %u)", + s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT, + s->log_dest & APIC_LOGDEST_XAPIC_ID); + } + qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s)); +} +#else +void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) +{ +} +#endif /* !CONFIG_USER_ONLY */ + +#define DUMP_CODE_BYTES_TOTAL 50 +#define DUMP_CODE_BYTES_BACKWARD 20 + +void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + int eflags, i, nb; + char cc_op_name[32]; + static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" }; + + eflags = cpu_compute_eflags(env); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n" + "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n" + "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n" + "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n" + "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n", + env->regs[R_EAX], + env->regs[R_EBX], + env->regs[R_ECX], + env->regs[R_EDX], + env->regs[R_ESI], + env->regs[R_EDI], + env->regs[R_EBP], + env->regs[R_ESP], + env->regs[8], + env->regs[9], + env->regs[10], + env->regs[11], + env->regs[12], + env->regs[13], + env->regs[14], + env->regs[15], + env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } else +#endif + { + qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n" + "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n" + "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n", + (uint32_t)env->regs[R_EAX], + (uint32_t)env->regs[R_EBX], + (uint32_t)env->regs[R_ECX], + (uint32_t)env->regs[R_EDX], + (uint32_t)env->regs[R_ESI], + (uint32_t)env->regs[R_EDI], + (uint32_t)env->regs[R_EBP], + (uint32_t)env->regs[R_ESP], + (uint32_t)env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } + + for(i = 0; i < 6; i++) { + cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]); + } + cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt); + cpu_x86_dump_seg_cache(env, f, "TR", &env->tr); + +#ifdef TARGET_X86_64 + if (env->hflags & HF_LMA_MASK) { + qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n", + env->gdt.base, env->gdt.limit); + qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n", + env->idt.base, env->idt.limit); + qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n", + (uint32_t)env->cr[0], + env->cr[2], + env->cr[3], + (uint32_t)env->cr[4]); + for(i = 0; i < 4; i++) + qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]); + qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n", + env->dr[6], env->dr[7]); + } else +#endif + { + qemu_fprintf(f, "GDT= %08x %08x\n", + (uint32_t)env->gdt.base, env->gdt.limit); + qemu_fprintf(f, "IDT= %08x %08x\n", + (uint32_t)env->idt.base, env->idt.limit); + qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n", + (uint32_t)env->cr[0], + (uint32_t)env->cr[2], + (uint32_t)env->cr[3], + (uint32_t)env->cr[4]); + for(i = 0; i < 4; i++) { + qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]); + } + qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n", + env->dr[6], env->dr[7]); + } + if (flags & CPU_DUMP_CCOP) { + if ((unsigned)env->cc_op < CC_OP_NB) + snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]); + else + snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n", + env->cc_src, env->cc_dst, + cc_op_name); + } else +#endif + { + qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n", + (uint32_t)env->cc_src, (uint32_t)env->cc_dst, + cc_op_name); + } + } + qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer); + if (flags & CPU_DUMP_FPU) { + int fptag; + fptag = 0; + for(i = 0; i < 8; i++) { + fptag |= ((!env->fptags[i]) << i); + } + update_mxcsr_from_sse_status(env); + qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n", + env->fpuc, + (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, + env->fpstt, + fptag, + env->mxcsr); + for(i=0;i<8;i++) { + CPU_LDoubleU u; + u.d = env->fpregs[i].d; + qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x", + i, u.l.lower, u.l.upper); + if ((i & 1) == 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } + if (env->hflags & HF_CS64_MASK) + nb = 16; + else + nb = 8; + for(i=0;i<nb;i++) { + qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", + i, + env->xmm_regs[i].ZMM_L(3), + env->xmm_regs[i].ZMM_L(2), + env->xmm_regs[i].ZMM_L(1), + env->xmm_regs[i].ZMM_L(0)); + if ((i & 1) == 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } + } + if (flags & CPU_DUMP_CODE) { + target_ulong base = env->segs[R_CS].base + env->eip; + target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); + uint8_t code; + char codestr[3]; + + qemu_fprintf(f, "Code="); + for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) { + if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) { + snprintf(codestr, sizeof(codestr), "%02x", code); + } else { + snprintf(codestr, sizeof(codestr), "??"); + } + qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", + i == offs ? "<" : "", codestr, i == offs ? ">" : ""); + } + qemu_fprintf(f, "\n"); + } +} diff --git a/target/i386/helper.c b/target/i386/helper.c index a1b3367ab2..6e7e0f507c 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,8 +21,6 @@ #include "qapi/qapi-events-run-state.h" #include "cpu.h" #include "exec/exec-all.h" -#include "qemu/qemu-print.h" -#include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY @@ -88,518 +86,6 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) return 0; } -/***********************************************************/ -/* x86 debug */ - -static const char *cc_op_str[CC_OP_NB] = { - "DYNAMIC", - "EFLAGS", - - "MULB", - "MULW", - "MULL", - "MULQ", - - "ADDB", - "ADDW", - "ADDL", - "ADDQ", - - "ADCB", - "ADCW", - "ADCL", - "ADCQ", - - "SUBB", - "SUBW", - "SUBL", - "SUBQ", - - "SBBB", - "SBBW", - "SBBL", - "SBBQ", - - "LOGICB", - "LOGICW", - "LOGICL", - "LOGICQ", - - "INCB", - "INCW", - "INCL", - "INCQ", - - "DECB", - "DECW", - "DECL", - "DECQ", - - "SHLB", - "SHLW", - "SHLL", - "SHLQ", - - "SARB", - "SARW", - "SARL", - "SARQ", - - "BMILGB", - "BMILGW", - "BMILGL", - "BMILGQ", - - "ADCX", - "ADOX", - "ADCOX", - - "CLR", -}; - -static void -cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, - const char *name, struct SegmentCache *sc) -{ -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name, - sc->selector, sc->base, sc->limit, - sc->flags & 0x00ffff00); - } else -#endif - { - qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector, - (uint32_t)sc->base, sc->limit, - sc->flags & 0x00ffff00); - } - - if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) - goto done; - - qemu_fprintf(f, " DPL=%d ", - (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); - if (sc->flags & DESC_S_MASK) { - if (sc->flags & DESC_CS_MASK) { - qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : - ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); - qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-', - (sc->flags & DESC_R_MASK) ? 'R' : '-'); - } else { - qemu_fprintf(f, (sc->flags & DESC_B_MASK - || env->hflags & HF_LMA_MASK) - ? "DS " : "DS16"); - qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-', - (sc->flags & DESC_W_MASK) ? 'W' : '-'); - } - qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); - } else { - static const char *sys_type_name[2][16] = { - { /* 32 bit mode */ - "Reserved", "TSS16-avl", "LDT", "TSS16-busy", - "CallGate16", "TaskGate", "IntGate16", "TrapGate16", - "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", - "CallGate32", "Reserved", "IntGate32", "TrapGate32" - }, - { /* 64 bit mode */ - "<hiword>", "Reserved", "LDT", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved", - "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", - "Reserved", "IntGate64", "TrapGate64" - } - }; - qemu_fprintf(f, "%s", - sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] - [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]); - } -done: - qemu_fprintf(f, "\n"); -} - -#ifndef CONFIG_USER_ONLY - -/* ARRAY_SIZE check is not required because - * DeliveryMode(dm) has a size of 3 bit. - */ -static inline const char *dm2str(uint32_t dm) -{ - static const char *str[] = { - "Fixed", - "...", - "SMI", - "...", - "NMI", - "INIT", - "...", - "ExtINT" - }; - return str[dm]; -} - -static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer) -{ - uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT; - qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s", - name, lvt, - lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi", - lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge", - lvt & APIC_LVT_MASKED ? "masked" : "", - lvt & APIC_LVT_DELIV_STS ? "pending" : "", - !is_timer ? - "" : lvt & APIC_LVT_TIMER_PERIODIC ? - "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ? - "tsc-deadline" : "one-shot", - dm2str(dm)); - if (dm != APIC_DM_NMI) { - qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK); - } else { - qemu_printf("\n"); - } -} - -/* ARRAY_SIZE check is not required because - * destination shorthand has a size of 2 bit. - */ -static inline const char *shorthand2str(uint32_t shorthand) -{ - const char *str[] = { - "no-shorthand", "self", "all-self", "all" - }; - return str[shorthand]; -} - -static inline uint8_t divider_conf(uint32_t divide_conf) -{ - uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3); - - return divide_val == 7 ? 1 : 2 << divide_val; -} - -static inline void mask2str(char *str, uint32_t val, uint8_t size) -{ - while (size--) { - *str++ = (val >> size) & 1 ? '1' : '0'; - } - *str = 0; -} - -#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16 - -static void dump_apic_icr(APICCommonState *s, CPUX86State *env) -{ - uint32_t icr = s->icr[0], icr2 = s->icr[1]; - uint8_t dest_shorthand = \ - (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT; - bool logical_mod = icr & APIC_ICR_DEST_MOD; - char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1]; - uint32_t dest_field; - bool x2apic; - - qemu_printf("ICR\t 0x%08x %s %s %s %s\n", - icr, - logical_mod ? "logical" : "physical", - icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge", - icr & APIC_ICR_LEVEL ? "assert" : "de-assert", - shorthand2str(dest_shorthand)); - - qemu_printf("ICR2\t 0x%08x", icr2); - if (dest_shorthand != 0) { - qemu_printf("\n"); - return; - } - x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; - dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT; - - if (!logical_mod) { - if (x2apic) { - qemu_printf(" cpu %u (X2APIC ID)\n", dest_field); - } else { - qemu_printf(" cpu %u (APIC ID)\n", - dest_field & APIC_LOGDEST_XAPIC_ID); - } - return; - } - - if (s->dest_mode == 0xf) { /* flat mode */ - mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8); - qemu_printf(" mask %s (APIC ID)\n", apic_id_str); - } else if (s->dest_mode == 0) { /* cluster mode */ - if (x2apic) { - mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16); - qemu_printf(" cluster %u mask %s (X2APIC ID)\n", - dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str); - } else { - mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4); - qemu_printf(" cluster %u mask %s (APIC ID)\n", - dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str); - } - } -} - -static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab, - uint32_t *tmr_tab) -{ - int i, empty = true; - - qemu_printf("%s\t ", name); - for (i = 0; i < 256; i++) { - if (apic_get_bit(ireg_tab, i)) { - qemu_printf("%u%s ", i, - apic_get_bit(tmr_tab, i) ? "(level)" : ""); - empty = false; - } - } - qemu_printf("%s\n", empty ? "(none)" : ""); -} - -void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) -{ - X86CPU *cpu = X86_CPU(cs); - APICCommonState *s = APIC_COMMON(cpu->apic_state); - if (!s) { - qemu_printf("local apic state not available\n"); - return; - } - uint32_t *lvt = s->lvt; - - qemu_printf("dumping local APIC state for CPU %-2u\n\n", - CPU(cpu)->cpu_index); - dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false); - dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false); - dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false); - dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false); - dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false); - dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true); - - qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u" - " current_count = %u\n", - s->divide_conf & APIC_DCR_MASK, - divider_conf(s->divide_conf), - s->initial_count, apic_get_current_count(s)); - - qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n", - s->spurious_vec, - s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled", - s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", - s->spurious_vec & APIC_VECTOR_MASK); - - dump_apic_icr(s, &cpu->env); - - qemu_printf("ESR\t 0x%08x\n", s->esr); - - dump_apic_interrupt("ISR", s->isr, s->tmr); - dump_apic_interrupt("IRR", s->irr, s->tmr); - - qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x", - s->arb_id, s->tpr, s->dest_mode, s->log_dest); - if (s->dest_mode == 0) { - qemu_printf("(cluster %u: id %u)", - s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT, - s->log_dest & APIC_LOGDEST_XAPIC_ID); - } - qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s)); -} -#else -void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) -{ -} -#endif /* !CONFIG_USER_ONLY */ - -#define DUMP_CODE_BYTES_TOTAL 50 -#define DUMP_CODE_BYTES_BACKWARD 20 - -void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - int eflags, i, nb; - char cc_op_name[32]; - static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" }; - - eflags = cpu_compute_eflags(env); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n" - "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n" - "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n" - "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n" - "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n", - env->regs[R_EAX], - env->regs[R_EBX], - env->regs[R_ECX], - env->regs[R_EDX], - env->regs[R_ESI], - env->regs[R_EDI], - env->regs[R_EBP], - env->regs[R_ESP], - env->regs[8], - env->regs[9], - env->regs[10], - env->regs[11], - env->regs[12], - env->regs[13], - env->regs[14], - env->regs[15], - env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } else -#endif - { - qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n" - "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n" - "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n", - (uint32_t)env->regs[R_EAX], - (uint32_t)env->regs[R_EBX], - (uint32_t)env->regs[R_ECX], - (uint32_t)env->regs[R_EDX], - (uint32_t)env->regs[R_ESI], - (uint32_t)env->regs[R_EDI], - (uint32_t)env->regs[R_EBP], - (uint32_t)env->regs[R_ESP], - (uint32_t)env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } - - for(i = 0; i < 6; i++) { - cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]); - } - cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt); - cpu_x86_dump_seg_cache(env, f, "TR", &env->tr); - -#ifdef TARGET_X86_64 - if (env->hflags & HF_LMA_MASK) { - qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n", - env->gdt.base, env->gdt.limit); - qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n", - env->idt.base, env->idt.limit); - qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n", - (uint32_t)env->cr[0], - env->cr[2], - env->cr[3], - (uint32_t)env->cr[4]); - for(i = 0; i < 4; i++) - qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]); - qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n", - env->dr[6], env->dr[7]); - } else -#endif - { - qemu_fprintf(f, "GDT= %08x %08x\n", - (uint32_t)env->gdt.base, env->gdt.limit); - qemu_fprintf(f, "IDT= %08x %08x\n", - (uint32_t)env->idt.base, env->idt.limit); - qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n", - (uint32_t)env->cr[0], - (uint32_t)env->cr[2], - (uint32_t)env->cr[3], - (uint32_t)env->cr[4]); - for(i = 0; i < 4; i++) { - qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]); - } - qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n", - env->dr[6], env->dr[7]); - } - if (flags & CPU_DUMP_CCOP) { - if ((unsigned)env->cc_op < CC_OP_NB) - snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]); - else - snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n", - env->cc_src, env->cc_dst, - cc_op_name); - } else -#endif - { - qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n", - (uint32_t)env->cc_src, (uint32_t)env->cc_dst, - cc_op_name); - } - } - qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer); - if (flags & CPU_DUMP_FPU) { - int fptag; - fptag = 0; - for(i = 0; i < 8; i++) { - fptag |= ((!env->fptags[i]) << i); - } - update_mxcsr_from_sse_status(env); - qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n", - env->fpuc, - (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, - env->fpstt, - fptag, - env->mxcsr); - for(i=0;i<8;i++) { - CPU_LDoubleU u; - u.d = env->fpregs[i].d; - qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x", - i, u.l.lower, u.l.upper); - if ((i & 1) == 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); - } - if (env->hflags & HF_CS64_MASK) - nb = 16; - else - nb = 8; - for(i=0;i<nb;i++) { - qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", - i, - env->xmm_regs[i].ZMM_L(3), - env->xmm_regs[i].ZMM_L(2), - env->xmm_regs[i].ZMM_L(1), - env->xmm_regs[i].ZMM_L(0)); - if ((i & 1) == 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); - } - } - if (flags & CPU_DUMP_CODE) { - target_ulong base = env->segs[R_CS].base + env->eip; - target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); - uint8_t code; - char codestr[3]; - - qemu_fprintf(f, "Code="); - for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) { - if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) { - snprintf(codestr, sizeof(codestr), "%02x", code); - } else { - snprintf(codestr, sizeof(codestr), "??"); - } - qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", - i == offs ? "<" : "", codestr, i == offs ? ">" : ""); - } - qemu_fprintf(f, "\n"); - } -} - /***********************************************************/ /* x86 mmu */ /* XXX: add PGE support */ diff --git a/target/i386/meson.build b/target/i386/meson.build index 750471c9f3..c4bf20b319 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -4,6 +4,7 @@ i386_ss.add(files( 'gdbstub.c', 'helper.c', 'xsave_helper.c', + 'cpu-dump.c', )) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c')) -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (5 preceding siblings ...) 2020-12-17 18:46 ` [PULL 06/17] i386: move cpu dump out of helper.c into cpu-dump.c Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 22:33 ` Claudio Fontana 2020-12-17 18:46 ` [PULL 08/17] i386: move hyperv_interface_id " Eduardo Habkost ` (10 subsequent siblings) 17 siblings, 1 reply; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Paolo Bonzini, Vitaly Kuznetsov, Eduardo Habkost, Richard Henderson From: Vitaly Kuznetsov <vkuznets@redhat.com> As a preparation to expanding Hyper-V CPU features early, move hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() itself. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-2-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.h | 3 ++- target/i386/cpu.c | 23 ++++++++++++++++++++++- target/i386/kvm/kvm.c | 25 ++++++++++--------------- 3 files changed, 34 insertions(+), 17 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 343e51baab..ad9ef559fc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1659,11 +1659,12 @@ struct X86CPU { uint64_t ucode_rev; uint32_t hyperv_spinlock_attempts; - char *hyperv_vendor_id; + char *hyperv_vendor; bool hyperv_synic_kvm_only; uint64_t hyperv_features; bool hyperv_passthrough; OnOffAuto hyperv_no_nonarch_cs; + uint32_t hyperv_vendor_id[3]; bool check_cpuid; bool enforce_cpuid; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 77f0e44df8..599526406a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6544,6 +6544,25 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) } } +static void x86_cpu_hyperv_realize(X86CPU *cpu) +{ + size_t len; + + /* Hyper-V vendor id */ + if (!cpu->hyperv_vendor) { + memcpy(cpu->hyperv_vendor_id, "Microsoft Hv", 12); + } else { + len = strlen(cpu->hyperv_vendor); + + if (len > 12) { + warn_report("hv-vendor-id truncated to 12 characters"); + len = 12; + } + memset(cpu->hyperv_vendor_id, 0, 12); + memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); + } +} + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -6715,6 +6734,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) env->cache_info_amd.l3_cache = &legacy_l3_cache; } + /* Process Hyper-V enlightenments */ + x86_cpu_hyperv_realize(cpu); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { @@ -7218,7 +7239,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), - DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), + DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index bcfa4b03e0..6a5d91e39f 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1208,6 +1208,13 @@ static int hyperv_handle_properties(CPUState *cs, memcpy(cpuid_ent, &cpuid->entries[0], cpuid->nent * sizeof(cpuid->entries[0])); + c = cpuid_find_entry(cpuid, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 0); + if (c) { + cpu->hyperv_vendor_id[0] = c->ebx; + cpu->hyperv_vendor_id[1] = c->ecx; + cpu->hyperv_vendor_id[2] = c->edx; + } + c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0); if (c) { env->features[FEAT_HYPERV_EAX] = c->eax; @@ -1282,23 +1289,11 @@ static int hyperv_handle_properties(CPUState *cs, c = &cpuid_ent[cpuid_i++]; c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS; - if (!cpu->hyperv_vendor_id) { - memcpy(signature, "Microsoft Hv", 12); - } else { - size_t len = strlen(cpu->hyperv_vendor_id); - - if (len > 12) { - error_report("hv-vendor-id truncated to 12 characters"); - len = 12; - } - memset(signature, 0, 12); - memcpy(signature, cpu->hyperv_vendor_id, len); - } c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ? HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS; - c->ebx = signature[0]; - c->ecx = signature[1]; - c->edx = signature[2]; + c->ebx = cpu->hyperv_vendor_id[0]; + c->ecx = cpu->hyperv_vendor_id[1]; + c->edx = cpu->hyperv_vendor_id[2]; c = &cpuid_ent[cpuid_i++]; c->function = HV_CPUID_INTERFACE; -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() 2020-12-17 18:46 ` [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() Eduardo Habkost @ 2020-12-17 22:33 ` Claudio Fontana 2020-12-17 22:53 ` Eduardo Habkost 0 siblings, 1 reply; 26+ messages in thread From: Claudio Fontana @ 2020-12-17 22:33 UTC (permalink / raw) To: Eduardo Habkost, Paolo Bonzini Cc: Peter Maydell, Vitaly Kuznetsov, Philippe Mathieu-Daudé, qemu-devel, Richard Henderson Hello all, On 12/17/20 7:46 PM, Eduardo Habkost wrote: > From: Vitaly Kuznetsov <vkuznets@redhat.com> > > As a preparation to expanding Hyper-V CPU features early, move > hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce > x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() > itself. this seems to fit very well the ongoing work on separating accelerator specific realize functions; related to the previous discussions about the class hierarchies, do you think that we should have a separate class in target/i386/kvm/ for a hyperv variant of the kvm-cpu.c? Should it be a separate class or a subclass of "kvm-accel-x86_64-cpu" ? Thanks, Claudio > Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> > Message-Id: <20201119103221.1665171-2-vkuznets@redhat.com> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > --- > target/i386/cpu.h | 3 ++- > target/i386/cpu.c | 23 ++++++++++++++++++++++- > target/i386/kvm/kvm.c | 25 ++++++++++--------------- > 3 files changed, 34 insertions(+), 17 deletions(-) > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 343e51baab..ad9ef559fc 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -1659,11 +1659,12 @@ struct X86CPU { > uint64_t ucode_rev; > > uint32_t hyperv_spinlock_attempts; > - char *hyperv_vendor_id; > + char *hyperv_vendor; > bool hyperv_synic_kvm_only; > uint64_t hyperv_features; > bool hyperv_passthrough; > OnOffAuto hyperv_no_nonarch_cs; > + uint32_t hyperv_vendor_id[3]; > > bool check_cpuid; > bool enforce_cpuid; > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 77f0e44df8..599526406a 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -6544,6 +6544,25 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) > } > } > > +static void x86_cpu_hyperv_realize(X86CPU *cpu) > +{ > + size_t len; > + > + /* Hyper-V vendor id */ > + if (!cpu->hyperv_vendor) { > + memcpy(cpu->hyperv_vendor_id, "Microsoft Hv", 12); > + } else { > + len = strlen(cpu->hyperv_vendor); > + > + if (len > 12) { > + warn_report("hv-vendor-id truncated to 12 characters"); > + len = 12; > + } > + memset(cpu->hyperv_vendor_id, 0, 12); > + memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); > + } > +} > + > static void x86_cpu_realizefn(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > @@ -6715,6 +6734,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) > env->cache_info_amd.l3_cache = &legacy_l3_cache; > } > > + /* Process Hyper-V enlightenments */ > + x86_cpu_hyperv_realize(cpu); > > cpu_exec_realizefn(cs, &local_err); > if (local_err != NULL) { > @@ -7218,7 +7239,7 @@ static Property x86_cpu_properties[] = { > DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), > DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), > DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), > - DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), > + DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), > DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), > DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), > DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), > diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c > index bcfa4b03e0..6a5d91e39f 100644 > --- a/target/i386/kvm/kvm.c > +++ b/target/i386/kvm/kvm.c > @@ -1208,6 +1208,13 @@ static int hyperv_handle_properties(CPUState *cs, > memcpy(cpuid_ent, &cpuid->entries[0], > cpuid->nent * sizeof(cpuid->entries[0])); > > + c = cpuid_find_entry(cpuid, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 0); > + if (c) { > + cpu->hyperv_vendor_id[0] = c->ebx; > + cpu->hyperv_vendor_id[1] = c->ecx; > + cpu->hyperv_vendor_id[2] = c->edx; > + } > + > c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0); > if (c) { > env->features[FEAT_HYPERV_EAX] = c->eax; > @@ -1282,23 +1289,11 @@ static int hyperv_handle_properties(CPUState *cs, > > c = &cpuid_ent[cpuid_i++]; > c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS; > - if (!cpu->hyperv_vendor_id) { > - memcpy(signature, "Microsoft Hv", 12); > - } else { > - size_t len = strlen(cpu->hyperv_vendor_id); > - > - if (len > 12) { > - error_report("hv-vendor-id truncated to 12 characters"); > - len = 12; > - } > - memset(signature, 0, 12); > - memcpy(signature, cpu->hyperv_vendor_id, len); > - } > c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ? > HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS; > - c->ebx = signature[0]; > - c->ecx = signature[1]; > - c->edx = signature[2]; > + c->ebx = cpu->hyperv_vendor_id[0]; > + c->ecx = cpu->hyperv_vendor_id[1]; > + c->edx = cpu->hyperv_vendor_id[2]; > > c = &cpuid_ent[cpuid_i++]; > c->function = HV_CPUID_INTERFACE; > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() 2020-12-17 22:33 ` Claudio Fontana @ 2020-12-17 22:53 ` Eduardo Habkost 2020-12-17 23:34 ` Claudio Fontana 0 siblings, 1 reply; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 22:53 UTC (permalink / raw) To: Claudio Fontana Cc: Peter Maydell, qemu-devel, Paolo Bonzini, Vitaly Kuznetsov, Philippe Mathieu-Daudé, Richard Henderson On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrote: > Hello all, > > On 12/17/20 7:46 PM, Eduardo Habkost wrote: > > From: Vitaly Kuznetsov <vkuznets@redhat.com> > > > > As a preparation to expanding Hyper-V CPU features early, move > > hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce > > x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() > > itself. > > this seems to fit very well the ongoing work on separating accelerator specific realize functions; > > related to the previous discussions about the class hierarchies, > do you think that we should have a separate class in target/i386/kvm/ for a hyperv variant of the kvm-cpu.c? > > Should it be a separate class or a subclass of "kvm-accel-x86_64-cpu" ? I don't see how a separate QOM class for Hyper-V would be helpful here. What would be the problem you are trying to solve in this case? Note that the Hyper-V features here are just a set of configurable VCPU features that appear on CPUID. This is not a different kind of hypervisor and/or a different kind of accelerator. -- Eduardo ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() 2020-12-17 22:53 ` Eduardo Habkost @ 2020-12-17 23:34 ` Claudio Fontana 2020-12-17 23:47 ` Eduardo Habkost 0 siblings, 1 reply; 26+ messages in thread From: Claudio Fontana @ 2020-12-17 23:34 UTC (permalink / raw) To: Eduardo Habkost Cc: Peter Maydell, qemu-devel, Paolo Bonzini, Vitaly Kuznetsov, Philippe Mathieu-Daudé, Richard Henderson On 12/17/20 11:53 PM, Eduardo Habkost wrote: > On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrote: >> Hello all, >> >> On 12/17/20 7:46 PM, Eduardo Habkost wrote: >>> From: Vitaly Kuznetsov <vkuznets@redhat.com> >>> >>> As a preparation to expanding Hyper-V CPU features early, move >>> hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce >>> x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() >>> itself. >> >> this seems to fit very well the ongoing work on separating accelerator specific realize functions; >> >> related to the previous discussions about the class hierarchies, >> do you think that we should have a separate class in target/i386/kvm/ for a hyperv variant of the kvm-cpu.c? >> >> Should it be a separate class or a subclass of "kvm-accel-x86_64-cpu" ? > > I don't see how a separate QOM class for Hyper-V would be helpful > here. What would be the problem you are trying to solve in this > case? there is now a call to accelerator specific code x86_hyperv_cpu_realize just before cpu_exec_realize, tying the generic target/i386/cpu.c code to kvm/hyperv-specific accel initialization. if this is just a feature of the kvm accel, maybe I should just move all to kvm-cpu.c and that's it. Thanks, Claudio > > Note that the Hyper-V features here are just a set of > configurable VCPU features that appear on CPUID. This is not a > different kind of hypervisor and/or a different kind of > accelerator. > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() 2020-12-17 23:34 ` Claudio Fontana @ 2020-12-17 23:47 ` Eduardo Habkost 2020-12-18 0:07 ` Claudio Fontana 0 siblings, 1 reply; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 23:47 UTC (permalink / raw) To: Claudio Fontana Cc: Peter Maydell, qemu-devel, Paolo Bonzini, Vitaly Kuznetsov, Philippe Mathieu-Daudé, Richard Henderson On Fri, Dec 18, 2020 at 12:34:46AM +0100, Claudio Fontana wrote: > On 12/17/20 11:53 PM, Eduardo Habkost wrote: > > On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrote: > >> Hello all, > >> > >> On 12/17/20 7:46 PM, Eduardo Habkost wrote: > >>> From: Vitaly Kuznetsov <vkuznets@redhat.com> > >>> > >>> As a preparation to expanding Hyper-V CPU features early, move > >>> hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce > >>> x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() > >>> itself. > >> > >> this seems to fit very well the ongoing work on separating accelerator specific realize functions; > >> > >> related to the previous discussions about the class hierarchies, > >> do you think that we should have a separate class in target/i386/kvm/ for a hyperv variant of the kvm-cpu.c? > >> > >> Should it be a separate class or a subclass of "kvm-accel-x86_64-cpu" ? > > > > I don't see how a separate QOM class for Hyper-V would be helpful > > here. What would be the problem you are trying to solve in this > > case? > > there is now a call to accelerator specific code x86_hyperv_cpu_realize just before cpu_exec_realize, > tying the generic target/i386/cpu.c code to kvm/hyperv-specific accel initialization. > > if this is just a feature of the kvm accel, maybe I should just move all to kvm-cpu.c and that's it. That would make sense. If we decide this is a KVM-specific feature, this code can be moved to kvm_cpu_realizefn(), provided by the kvm-accel-x86_64-cpu class added by your series. However, I'm not sure we can say this is a KVM-specific feature. The feature is currently only supported by the KVM accelerator, but I'd say it is a generic feature. -- Eduardo ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() 2020-12-17 23:47 ` Eduardo Habkost @ 2020-12-18 0:07 ` Claudio Fontana 2020-12-18 1:05 ` Eduardo Habkost 0 siblings, 1 reply; 26+ messages in thread From: Claudio Fontana @ 2020-12-18 0:07 UTC (permalink / raw) To: Eduardo Habkost Cc: Peter Maydell, qemu-devel, Paolo Bonzini, Vitaly Kuznetsov, Philippe Mathieu-Daudé, Richard Henderson On 12/18/20 12:47 AM, Eduardo Habkost wrote: > On Fri, Dec 18, 2020 at 12:34:46AM +0100, Claudio Fontana wrote: >> On 12/17/20 11:53 PM, Eduardo Habkost wrote: >>> On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrote: >>>> Hello all, >>>> >>>> On 12/17/20 7:46 PM, Eduardo Habkost wrote: >>>>> From: Vitaly Kuznetsov <vkuznets@redhat.com> >>>>> >>>>> As a preparation to expanding Hyper-V CPU features early, move >>>>> hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce >>>>> x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() >>>>> itself. >>>> >>>> this seems to fit very well the ongoing work on separating accelerator specific realize functions; >>>> >>>> related to the previous discussions about the class hierarchies, >>>> do you think that we should have a separate class in target/i386/kvm/ for a hyperv variant of the kvm-cpu.c? >>>> >>>> Should it be a separate class or a subclass of "kvm-accel-x86_64-cpu" ? >>> >>> I don't see how a separate QOM class for Hyper-V would be helpful >>> here. What would be the problem you are trying to solve in this >>> case? >> >> there is now a call to accelerator specific code x86_hyperv_cpu_realize just before cpu_exec_realize, >> tying the generic target/i386/cpu.c code to kvm/hyperv-specific accel initialization. >> >> if this is just a feature of the kvm accel, maybe I should just move all to kvm-cpu.c and that's it. > > That would make sense. If we decide this is a KVM-specific > feature, this code can be moved to kvm_cpu_realizefn(), provided > by the kvm-accel-x86_64-cpu class added by your series. > > However, I'm not sure we can say this is a KVM-specific feature. > The feature is currently only supported by the KVM accelerator, > but I'd say it is a generic feature. > Maybe in the future it will be a generic feature, and we can export it the right way? It will be super-easy if the feature is well contained. Until it really is generic though, should it really appear in the middle of x86_cpu_realizefn? currently the generic code in target/i386/cpu.c contains an unconditional call to: x86_cpu_hyperv_realize(cpu); before the call to cpu_exec_realizefn(). the function is defined in this very same file before as: static void x86_cpu_hyperv_realize(X86CPU *cpu) { ... } with a bunch of initializations of hyperv specific data, for example cpu->hyperv_interface_id, cpu->hyperv_vendor_id, cpu->hyperv_version_id. That data is ever only used in kvm/kvm.c, which is built conditionally under CONFIG_KVM. So the existing situation is fairly inconsistent in my view, at least for how things are now, and in principle the extra code of the initializations for hyperv should never be executed if !CONFIG_KVM. Thanks, Ciao, Claudio ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() 2020-12-18 0:07 ` Claudio Fontana @ 2020-12-18 1:05 ` Eduardo Habkost 2020-12-18 8:50 ` Claudio Fontana 0 siblings, 1 reply; 26+ messages in thread From: Eduardo Habkost @ 2020-12-18 1:05 UTC (permalink / raw) To: Claudio Fontana Cc: Peter Maydell, qemu-devel, Paolo Bonzini, Vitaly Kuznetsov, Philippe Mathieu-Daudé, Richard Henderson On Fri, Dec 18, 2020 at 01:07:33AM +0100, Claudio Fontana wrote: > On 12/18/20 12:47 AM, Eduardo Habkost wrote: > > On Fri, Dec 18, 2020 at 12:34:46AM +0100, Claudio Fontana wrote: > >> On 12/17/20 11:53 PM, Eduardo Habkost wrote: > >>> On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrote: > >>>> Hello all, > >>>> > >>>> On 12/17/20 7:46 PM, Eduardo Habkost wrote: > >>>>> From: Vitaly Kuznetsov <vkuznets@redhat.com> > >>>>> > >>>>> As a preparation to expanding Hyper-V CPU features early, move > >>>>> hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce > >>>>> x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() > >>>>> itself. > >>>> > >>>> this seems to fit very well the ongoing work on separating accelerator specific realize functions; > >>>> > >>>> related to the previous discussions about the class hierarchies, > >>>> do you think that we should have a separate class in target/i386/kvm/ for a hyperv variant of the kvm-cpu.c? > >>>> > >>>> Should it be a separate class or a subclass of "kvm-accel-x86_64-cpu" ? > >>> > >>> I don't see how a separate QOM class for Hyper-V would be helpful > >>> here. What would be the problem you are trying to solve in this > >>> case? > >> > >> there is now a call to accelerator specific code x86_hyperv_cpu_realize just before cpu_exec_realize, > >> tying the generic target/i386/cpu.c code to kvm/hyperv-specific accel initialization. > >> > >> if this is just a feature of the kvm accel, maybe I should just move all to kvm-cpu.c and that's it. > > > > That would make sense. If we decide this is a KVM-specific > > feature, this code can be moved to kvm_cpu_realizefn(), provided > > by the kvm-accel-x86_64-cpu class added by your series. > > > > However, I'm not sure we can say this is a KVM-specific feature. > > The feature is currently only supported by the KVM accelerator, > > but I'd say it is a generic feature. > > > > Maybe in the future it will be a generic feature, and we can export it the right way? > It will be super-easy if the feature is well contained. > > Until it really is generic though, should it really appear in the middle of x86_cpu_realizefn? > currently the generic code in target/i386/cpu.c contains an unconditional call to: > > x86_cpu_hyperv_realize(cpu); > > before the call to cpu_exec_realizefn(). > > the function is defined in this very same file before as: > > static void x86_cpu_hyperv_realize(X86CPU *cpu) > { > ... > } > > with a bunch of initializations of hyperv specific data, for example cpu->hyperv_interface_id, cpu->hyperv_vendor_id, cpu->hyperv_version_id. > > That data is ever only used in kvm/kvm.c, which is built conditionally under CONFIG_KVM. > > So the existing situation is fairly inconsistent in my view, at least for how things are now, and in principle the extra code of the initializations for hyperv should never be executed if !CONFIG_KVM. What's the problem you are trying to solve? Speed? Binary size? Something else? Moving the code in x86_cpu_hyperv_realize() to kvm-cpu.c sounds like a drop in the bucket. It wouldn't get rid of hyperv-specific code in cpu.c, which includes: - the "hv-*" properties in x86_cpu_properties[]; - FEAT_HYPERV_* CPUID leaf definitions; - hyperv code in x86_cpu_get_crash_info(). I wouldn't object if somebody really wants to move it, but I don't see it as a problem. -- Eduardo ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() 2020-12-18 1:05 ` Eduardo Habkost @ 2020-12-18 8:50 ` Claudio Fontana 0 siblings, 0 replies; 26+ messages in thread From: Claudio Fontana @ 2020-12-18 8:50 UTC (permalink / raw) To: Eduardo Habkost Cc: Peter Maydell, qemu-devel, Paolo Bonzini, Vitaly Kuznetsov, Philippe Mathieu-Daudé, Richard Henderson On 12/18/20 2:05 AM, Eduardo Habkost wrote: > On Fri, Dec 18, 2020 at 01:07:33AM +0100, Claudio Fontana wrote: >> On 12/18/20 12:47 AM, Eduardo Habkost wrote: >>> On Fri, Dec 18, 2020 at 12:34:46AM +0100, Claudio Fontana wrote: >>>> On 12/17/20 11:53 PM, Eduardo Habkost wrote: >>>>> On Thu, Dec 17, 2020 at 11:33:57PM +0100, Claudio Fontana wrote: >>>>>> Hello all, >>>>>> >>>>>> On 12/17/20 7:46 PM, Eduardo Habkost wrote: >>>>>>> From: Vitaly Kuznetsov <vkuznets@redhat.com> >>>>>>> >>>>>>> As a preparation to expanding Hyper-V CPU features early, move >>>>>>> hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce >>>>>>> x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() >>>>>>> itself. >>>>>> >>>>>> this seems to fit very well the ongoing work on separating accelerator specific realize functions; >>>>>> >>>>>> related to the previous discussions about the class hierarchies, >>>>>> do you think that we should have a separate class in target/i386/kvm/ for a hyperv variant of the kvm-cpu.c? >>>>>> >>>>>> Should it be a separate class or a subclass of "kvm-accel-x86_64-cpu" ? >>>>> >>>>> I don't see how a separate QOM class for Hyper-V would be helpful >>>>> here. What would be the problem you are trying to solve in this >>>>> case? >>>> >>>> there is now a call to accelerator specific code x86_hyperv_cpu_realize just before cpu_exec_realize, >>>> tying the generic target/i386/cpu.c code to kvm/hyperv-specific accel initialization. >>>> >>>> if this is just a feature of the kvm accel, maybe I should just move all to kvm-cpu.c and that's it. >>> >>> That would make sense. If we decide this is a KVM-specific >>> feature, this code can be moved to kvm_cpu_realizefn(), provided >>> by the kvm-accel-x86_64-cpu class added by your series. >>> >>> However, I'm not sure we can say this is a KVM-specific feature. >>> The feature is currently only supported by the KVM accelerator, >>> but I'd say it is a generic feature. >>> >> >> Maybe in the future it will be a generic feature, and we can export it the right way? >> It will be super-easy if the feature is well contained. >> >> Until it really is generic though, should it really appear in the middle of x86_cpu_realizefn? >> currently the generic code in target/i386/cpu.c contains an unconditional call to: >> >> x86_cpu_hyperv_realize(cpu); >> >> before the call to cpu_exec_realizefn(). >> >> the function is defined in this very same file before as: >> >> static void x86_cpu_hyperv_realize(X86CPU *cpu) >> { >> ... >> } >> >> with a bunch of initializations of hyperv specific data, for example cpu->hyperv_interface_id, cpu->hyperv_vendor_id, cpu->hyperv_version_id. >> >> That data is ever only used in kvm/kvm.c, which is built conditionally under CONFIG_KVM. >> >> So the existing situation is fairly inconsistent in my view, at least for how things are now, and in principle the extra code of the initializations for hyperv should never be executed if !CONFIG_KVM. > > What's the problem you are trying to solve? Speed? Binary size? > Something else? > > Moving the code in x86_cpu_hyperv_realize() to kvm-cpu.c sounds > like a drop in the bucket. It wouldn't get rid of > hyperv-specific code in cpu.c, which includes: > - the "hv-*" properties in x86_cpu_properties[]; > - FEAT_HYPERV_* CPUID leaf definitions; > - hyperv code in x86_cpu_get_crash_info(). > > I wouldn't object if somebody really wants to move it, but I > don't see it as a problem. > Nm I'll take a look later on. Thanks! Claudio ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PULL 08/17] i386: move hyperv_interface_id initialization to x86_cpu_realizefn() 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (6 preceding siblings ...) 2020-12-17 18:46 ` [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 09/17] i386: move hyperv_version_id " Eduardo Habkost ` (9 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Paolo Bonzini, Vitaly Kuznetsov, Eduardo Habkost, Richard Henderson From: Vitaly Kuznetsov <vkuznets@redhat.com> As a preparation to expanding Hyper-V CPU features early, move hyperv_interface_id initialization to x86_cpu_realizefn(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-3-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.h | 1 + target/i386/cpu.c | 6 ++++++ target/i386/kvm/kvm.c | 18 ++++++++++++------ 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ad9ef559fc..fd29afebc9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1665,6 +1665,7 @@ struct X86CPU { bool hyperv_passthrough; OnOffAuto hyperv_no_nonarch_cs; uint32_t hyperv_vendor_id[3]; + uint32_t hyperv_interface_id[4]; bool check_cpuid; bool enforce_cpuid; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 599526406a..ab10c0225d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6561,6 +6561,12 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) memset(cpu->hyperv_vendor_id, 0, 12); memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); } + + /* 'Hv#1' interface identification*/ + cpu->hyperv_interface_id[0] = 0x31237648; + cpu->hyperv_interface_id[1] = 0; + cpu->hyperv_interface_id[2] = 0; + cpu->hyperv_interface_id[3] = 0; } static void x86_cpu_realizefn(DeviceState *dev, Error **errp) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 6a5d91e39f..d3aa7ca281 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1171,7 +1171,6 @@ static int hyperv_handle_properties(CPUState *cs, CPUX86State *env = &cpu->env; struct kvm_cpuid2 *cpuid; struct kvm_cpuid_entry2 *c; - uint32_t signature[3]; uint32_t cpuid_i = 0; int r; @@ -1215,6 +1214,14 @@ static int hyperv_handle_properties(CPUState *cs, cpu->hyperv_vendor_id[2] = c->edx; } + c = cpuid_find_entry(cpuid, HV_CPUID_INTERFACE, 0); + if (c) { + cpu->hyperv_interface_id[0] = c->eax; + cpu->hyperv_interface_id[1] = c->ebx; + cpu->hyperv_interface_id[2] = c->ecx; + cpu->hyperv_interface_id[3] = c->edx; + } + c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0); if (c) { env->features[FEAT_HYPERV_EAX] = c->eax; @@ -1297,11 +1304,10 @@ static int hyperv_handle_properties(CPUState *cs, c = &cpuid_ent[cpuid_i++]; c->function = HV_CPUID_INTERFACE; - memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); - c->eax = signature[0]; - c->ebx = 0; - c->ecx = 0; - c->edx = 0; + c->eax = cpu->hyperv_interface_id[0]; + c->ebx = cpu->hyperv_interface_id[1]; + c->ecx = cpu->hyperv_interface_id[2]; + c->edx = cpu->hyperv_interface_id[3]; c = &cpuid_ent[cpuid_i++]; c->function = HV_CPUID_VERSION; -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 09/17] i386: move hyperv_version_id initialization to x86_cpu_realizefn() 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (7 preceding siblings ...) 2020-12-17 18:46 ` [PULL 08/17] i386: move hyperv_interface_id " Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 10/17] i386: move hyperv_limits " Eduardo Habkost ` (8 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Paolo Bonzini, Vitaly Kuznetsov, Eduardo Habkost, Richard Henderson From: Vitaly Kuznetsov <vkuznets@redhat.com> As a preparation to expanding Hyper-V CPU features early, move hyperv_version_id initialization to x86_cpu_realizefn(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-4-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.h | 1 + target/i386/cpu.c | 4 ++++ target/i386/kvm/kvm.c | 14 ++++++++++++-- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index fd29afebc9..adce57dc78 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1666,6 +1666,7 @@ struct X86CPU { OnOffAuto hyperv_no_nonarch_cs; uint32_t hyperv_vendor_id[3]; uint32_t hyperv_interface_id[4]; + uint32_t hyperv_version_id[4]; bool check_cpuid; bool enforce_cpuid; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ab10c0225d..6c5b0fef79 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6567,6 +6567,10 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) cpu->hyperv_interface_id[1] = 0; cpu->hyperv_interface_id[2] = 0; cpu->hyperv_interface_id[3] = 0; + + /* Hypervisor system identity */ + cpu->hyperv_version_id[0] = 0x00001bbc; + cpu->hyperv_version_id[1] = 0x00060001; } static void x86_cpu_realizefn(DeviceState *dev, Error **errp) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index d3aa7ca281..db2069406d 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1222,6 +1222,14 @@ static int hyperv_handle_properties(CPUState *cs, cpu->hyperv_interface_id[3] = c->edx; } + c = cpuid_find_entry(cpuid, HV_CPUID_VERSION, 0); + if (c) { + cpu->hyperv_version_id[0] = c->eax; + cpu->hyperv_version_id[1] = c->ebx; + cpu->hyperv_version_id[2] = c->ecx; + cpu->hyperv_version_id[3] = c->edx; + } + c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0); if (c) { env->features[FEAT_HYPERV_EAX] = c->eax; @@ -1311,8 +1319,10 @@ static int hyperv_handle_properties(CPUState *cs, c = &cpuid_ent[cpuid_i++]; c->function = HV_CPUID_VERSION; - c->eax = 0x00001bbc; - c->ebx = 0x00060001; + c->eax = cpu->hyperv_version_id[0]; + c->ebx = cpu->hyperv_version_id[1]; + c->ecx = cpu->hyperv_version_id[2]; + c->edx = cpu->hyperv_version_id[3]; c = &cpuid_ent[cpuid_i++]; c->function = HV_CPUID_FEATURES; -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 10/17] i386: move hyperv_limits initialization to x86_cpu_realizefn() 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (8 preceding siblings ...) 2020-12-17 18:46 ` [PULL 09/17] i386: move hyperv_version_id " Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 11/17] x86/cpu: Add AVX512_FP16 cpu feature Eduardo Habkost ` (7 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Paolo Bonzini, Vitaly Kuznetsov, Eduardo Habkost, Richard Henderson From: Vitaly Kuznetsov <vkuznets@redhat.com> As a preparation to expanding Hyper-V CPU features early, move hyperv_limits initialization to x86_cpu_realizefn(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-5-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.h | 1 + target/i386/cpu.c | 5 +++++ target/i386/kvm/kvm.c | 13 ++++++++++++- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index adce57dc78..ee03263800 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1667,6 +1667,7 @@ struct X86CPU { uint32_t hyperv_vendor_id[3]; uint32_t hyperv_interface_id[4]; uint32_t hyperv_version_id[4]; + uint32_t hyperv_limits[3]; bool check_cpuid; bool enforce_cpuid; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6c5b0fef79..45b0588af3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6571,6 +6571,11 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) /* Hypervisor system identity */ cpu->hyperv_version_id[0] = 0x00001bbc; cpu->hyperv_version_id[1] = 0x00060001; + + /* Hypervisor implementation limits */ + cpu->hyperv_limits[0] = 64; + cpu->hyperv_limits[1] = 0; + cpu->hyperv_limits[2] = 0; } static void x86_cpu_realizefn(DeviceState *dev, Error **errp) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index db2069406d..6dc1ee052d 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1236,6 +1236,15 @@ static int hyperv_handle_properties(CPUState *cs, env->features[FEAT_HYPERV_EBX] = c->ebx; env->features[FEAT_HYPERV_EDX] = c->edx; } + + c = cpuid_find_entry(cpuid, HV_CPUID_IMPLEMENT_LIMITS, 0); + if (c) { + cpu->hv_max_vps = c->eax; + cpu->hyperv_limits[0] = c->ebx; + cpu->hyperv_limits[1] = c->ecx; + cpu->hyperv_limits[2] = c->edx; + } + c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0); if (c) { env->features[FEAT_HV_RECOMM_EAX] = c->eax; @@ -1338,7 +1347,9 @@ static int hyperv_handle_properties(CPUState *cs, c = &cpuid_ent[cpuid_i++]; c->function = HV_CPUID_IMPLEMENT_LIMITS; c->eax = cpu->hv_max_vps; - c->ebx = 0x40; + c->ebx = cpu->hyperv_limits[0]; + c->ecx = cpu->hyperv_limits[1]; + c->edx = cpu->hyperv_limits[2]; if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { __u32 function; -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 11/17] x86/cpu: Add AVX512_FP16 cpu feature 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (9 preceding siblings ...) 2020-12-17 18:46 ` [PULL 10/17] i386: move hyperv_limits " Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 12/17] i386: move TCG cpu class initialization to tcg/ Eduardo Habkost ` (6 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Cathy Zhang, Paolo Bonzini, Eduardo Habkost, Richard Henderson From: Cathy Zhang <cathy.zhang@intel.com> AVX512 Half-precision floating point (FP16) has better performance compared to FP32 if the presicion or magnitude requirements are met. It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23]. Refer to https://software.intel.com/content/www/us/en/develop/download/\ intel-architecture-instruction-set-extensions-programming-reference.html Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Message-Id: <20201216224002.32677-1-cathy.zhang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.h | 2 ++ target/i386/cpu.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ee03263800..9b2ced97ea 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -784,6 +784,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_SERIALIZE (1U << 14) /* TSX Suspend Load Address Tracking instruction */ #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) +/* AVX512_FP16 instruction */ +#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 45b0588af3..608e9cacf9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -979,7 +979,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, "serialize", NULL, "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "avx512-fp16", NULL, NULL, "spec-ctrl", "stibp", NULL, "arch-capabilities", "core-capability", "ssbd", }, -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 12/17] i386: move TCG cpu class initialization to tcg/ 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (10 preceding siblings ...) 2020-12-17 18:46 ` [PULL 11/17] x86/cpu: Add AVX512_FP16 cpu feature Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 13/17] i386: tcg: remove inline from cpu_load_eflags Eduardo Habkost ` (5 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Paolo Bonzini, Claudio Fontana, Richard Henderson, Eduardo Habkost, Richard Henderson From: Claudio Fontana <cfontana@suse.de> to do this, we need to take code out of cpu.c and helper.c, and also move some prototypes from cpu.h, for code that is needed in tcg/xxx_helper.c, and which in turn is part of the callbacks registered by the class initialization. Therefore, do some shuffling of the parts of cpu.h that are only relevant for tcg/, and put them in tcg/helper-tcg.h For FT0 and similar macros, put them in tcg/fpu-helper.c since they are used only there. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-8-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.h | 86 --------------------------- target/i386/tcg/helper-tcg.h | 106 ++++++++++++++++++++++++++++++++++ target/i386/tcg/tcg-cpu.h | 15 +++++ target/i386/cpu.c | 33 ++++------- target/i386/helper.c | 23 -------- target/i386/tcg/bpt_helper.c | 1 + target/i386/tcg/cc_helper.c | 1 + target/i386/tcg/excp_helper.c | 1 + target/i386/tcg/fpu_helper.c | 39 +++++++------ target/i386/tcg/int_helper.c | 1 + target/i386/tcg/mem_helper.c | 1 + target/i386/tcg/meson.build | 1 + target/i386/tcg/misc_helper.c | 1 + target/i386/tcg/mpx_helper.c | 1 + target/i386/tcg/seg_helper.c | 1 + target/i386/tcg/smm_helper.c | 2 + target/i386/tcg/svm_helper.c | 1 + target/i386/tcg/tcg-cpu.c | 71 +++++++++++++++++++++++ target/i386/tcg/translate.c | 1 + 19 files changed, 238 insertions(+), 148 deletions(-) create mode 100644 target/i386/tcg/helper-tcg.h create mode 100644 target/i386/tcg/tcg-cpu.h create mode 100644 target/i386/tcg/tcg-cpu.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9b2ced97ea..af130512e2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -31,9 +31,6 @@ #define KVM_HAVE_MCE_INJECTION 1 -/* Maximum instruction code size */ -#define TARGET_MAX_INSN_SIZE 16 - /* support for self modifying code even if the modified instruction is close to the modifying instruction */ #define TARGET_HAS_PRECISE_SMC @@ -1775,12 +1772,6 @@ struct X86CPU { extern VMStateDescription vmstate_x86_cpu; #endif -/** - * x86_cpu_do_interrupt: - * @cpu: vCPU the interrupt is to be handled by. - */ -void x86_cpu_do_interrupt(CPUState *cpu); -bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -1803,9 +1794,6 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void x86_cpu_exec_enter(CPUState *cpu); -void x86_cpu_exec_exit(CPUState *cpu); - void x86_cpu_list(void); int cpu_x86_support_mca_broadcast(CPUX86State *env); @@ -1930,9 +1918,6 @@ void host_cpuid(uint32_t function, uint32_t count, void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); /* helper.c */ -bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void x86_cpu_set_a20(X86CPU *cpu, int a20_state); #ifndef CONFIG_USER_ONLY @@ -1957,8 +1942,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); #endif -void breakpoint_handler(CPUState *cs); - /* will be suppressed */ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); @@ -1968,16 +1951,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); -/* XXX: This value should match the one returned by CPUID - * and in exec.c */ -# if defined(TARGET_X86_64) -# define TCG_PHYS_ADDR_BITS 40 -# else -# define TCG_PHYS_ADDR_BITS 36 -# endif - -#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) - #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_X86_CPU @@ -2014,25 +1987,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env) #define CC_SRC2 (env->cc_src2) #define CC_OP (env->cc_op) -/* n must be a constant to be efficient */ -static inline target_long lshift(target_long x, int n) -{ - if (n >= 0) { - return x << n; - } else { - return x >> (-n); - } -} - -/* float macros */ -#define FT0 (env->ft0) -#define ST0 (env->fpregs[env->fpstt].d) -#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) -#define ST1 ST(1) - -/* translate.c */ -void tcg_x86_init(void); - typedef CPUX86State CPUArchState; typedef X86CPU ArchCPU; @@ -2062,19 +2016,6 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, uint64_t status, uint64_t mcg_status, uint64_t addr, uint64_t misc, int flags); -/* excp_helper.c */ -void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); -void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, - uintptr_t retaddr); -void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, - int error_code); -void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, - int error_code, uintptr_t retaddr); -void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, - int error_code, int next_eip_addend); - -/* cc_helper.c */ -extern const uint8_t parity_table[256]; uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); static inline uint32_t cpu_compute_eflags(CPUX86State *env) @@ -2086,18 +2027,6 @@ static inline uint32_t cpu_compute_eflags(CPUX86State *env) return eflags; } -/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS - * after generating a call to a helper that uses this. - */ -static inline void cpu_load_eflags(CPUX86State *env, int eflags, - int update_mask) -{ - CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - CC_OP = CC_OP_EFLAGS; - env->df = 1 - (2 * ((eflags >> 10) & 1)); - env->eflags = (env->eflags & ~update_mask) | - (eflags & update_mask) | 0x2; -} /* load efer and update the corresponding hflags. XXX: do consistency checks with cpuid bits? */ @@ -2186,16 +2115,6 @@ void helper_lock_init(void); /* svm_helper.c */ void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param, uintptr_t retaddr); -void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, - uint64_t exit_info_1, uintptr_t retaddr); -void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); - -/* seg_helper.c */ -void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); - -/* smm_helper.c */ -void do_smm_enter(X86CPU *cpu); - /* apic.c */ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, @@ -2234,11 +2153,6 @@ typedef int X86CPUVersion; */ void x86_cpu_set_default_version(X86CPUVersion version); -/* Return name of 32-bit register, from a R_* constant */ -const char *get_register_name_32(unsigned int reg); - -void enable_compat_apic_id_mode(void); - #define APIC_DEFAULT_ADDRESS 0xfee00000 #define APIC_SPACE_SIZE 0x100000 diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h new file mode 100644 index 0000000000..148edf49a3 --- /dev/null +++ b/target/i386/tcg/helper-tcg.h @@ -0,0 +1,106 @@ +/* + * TCG specific prototypes for helpers + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef I386_HELPER_TCG_H +#define I386_HELPER_TCG_H + +#include "exec/exec-all.h" + +/* Maximum instruction code size */ +#define TARGET_MAX_INSN_SIZE 16 + +/* + * XXX: This value should match the one returned by CPUID + * and in exec.c + */ +# if defined(TARGET_X86_64) +# define TCG_PHYS_ADDR_BITS 40 +# else +# define TCG_PHYS_ADDR_BITS 36 +# endif + +#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) + +/** + * x86_cpu_do_interrupt: + * @cpu: vCPU the interrupt is to be handled by. + */ +void x86_cpu_do_interrupt(CPUState *cpu); +bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); + +/* helper.c */ +bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +void breakpoint_handler(CPUState *cs); + +/* n must be a constant to be efficient */ +static inline target_long lshift(target_long x, int n) +{ + if (n >= 0) { + return x << n; + } else { + return x >> (-n); + } +} + +/* translate.c */ +void tcg_x86_init(void); + +/* excp_helper.c */ +void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); +void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, + uintptr_t retaddr); +void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, + int error_code); +void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, + int error_code, uintptr_t retaddr); +void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, + int error_code, int next_eip_addend); + +/* cc_helper.c */ +extern const uint8_t parity_table[256]; + +/* + * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS + * after generating a call to a helper that uses this. + */ +static inline void cpu_load_eflags(CPUX86State *env, int eflags, + int update_mask) +{ + CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + CC_OP = CC_OP_EFLAGS; + env->df = 1 - (2 * ((eflags >> 10) & 1)); + env->eflags = (env->eflags & ~update_mask) | + (eflags & update_mask) | 0x2; +} + +/* svm_helper.c */ +void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, + uint64_t exit_info_1, uintptr_t retaddr); +void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); + +/* seg_helper.c */ +void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); + +/* smm_helper.c */ +void do_smm_enter(X86CPU *cpu); + +#endif /* I386_HELPER_TCG_H */ diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h new file mode 100644 index 0000000000..81f02e562e --- /dev/null +++ b/target/i386/tcg/tcg-cpu.h @@ -0,0 +1,15 @@ +/* + * i386 TCG CPU class initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPU_H +#define TCG_CPU_H + +void tcg_cpu_common_class_init(CPUClass *cc); + +#endif /* TCG_CPU_H */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 608e9cacf9..0d20e156f2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -24,6 +24,8 @@ #include "qemu/qemu-print.h" #include "cpu.h" +#include "tcg/tcg-cpu.h" +#include "tcg/helper-tcg.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" @@ -1521,7 +1523,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) cpu->env.features[FEAT_XSAVE_COMP_LO]; } -const char *get_register_name_32(unsigned int reg) +/* Return name of 32-bit register, from a R_* constant */ +static const char *get_register_name_32(unsigned int reg) { if (reg >= CPU_NB_REGS32) { return NULL; @@ -7068,13 +7071,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip = value; } -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) -{ - X86CPU *cpu = X86_CPU(cs); - - cpu->env.eip = tb->pc - tb->cs_base; -} - int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu = X86_CPU(cs); @@ -7309,17 +7305,18 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->class_by_name = x86_cpu_class_by_name; cc->parse_features = x86_cpu_parse_featurestr; cc->has_work = x86_cpu_has_work; + #ifdef CONFIG_TCG - cc->do_interrupt = x86_cpu_do_interrupt; - cc->cpu_exec_interrupt = x86_cpu_exec_interrupt; -#endif + tcg_cpu_common_class_init(cc); +#endif /* CONFIG_TCG */ + cc->dump_state = x86_cpu_dump_state; cc->set_pc = x86_cpu_set_pc; - cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; cc->gdb_read_register = x86_cpu_gdb_read_register; cc->gdb_write_register = x86_cpu_gdb_write_register; cc->get_arch_id = x86_cpu_get_arch_id; cc->get_paging_enabled = x86_cpu_get_paging_enabled; + #ifndef CONFIG_USER_ONLY cc->asidx_from_attrs = x86_asidx_from_attrs; cc->get_memory_mapping = x86_cpu_get_memory_mapping; @@ -7330,7 +7327,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->write_elf32_note = x86_cpu_write_elf32_note; cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote; cc->vmsd = &vmstate_x86_cpu; -#endif +#endif /* !CONFIG_USER_ONLY */ + cc->gdb_arch_name = x86_gdb_arch_name; #ifdef TARGET_X86_64 cc->gdb_core_xml_file = "i386-64bit.xml"; @@ -7338,15 +7336,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) #else cc->gdb_core_xml_file = "i386-32bit.xml"; cc->gdb_num_core_regs = 50; -#endif -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - cc->debug_excp_handler = breakpoint_handler; -#endif - cc->cpu_exec_enter = x86_cpu_exec_enter; - cc->cpu_exec_exit = x86_cpu_exec_exit; -#ifdef CONFIG_TCG - cc->tcg_initialize = tcg_x86_init; - cc->tlb_fill = x86_cpu_tlb_fill; #endif cc->disas_set_info = x86_disas_set_info; diff --git a/target/i386/helper.c b/target/i386/helper.c index 6e7e0f507c..6bb0c53182 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -24,10 +24,8 @@ #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY -#include "sysemu/tcg.h" #include "sysemu/hw_accel.h" #include "monitor/monitor.h" -#include "hw/i386/apic_internal.h" #endif void cpu_sync_bndcs_hflags(CPUX86State *env) @@ -572,27 +570,6 @@ void do_cpu_sipi(X86CPU *cpu) } #endif -/* Frob eflags into and out of the CPU temporary format. */ - -void x86_cpu_exec_enter(CPUState *cs) -{ - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - - CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - env->df = 1 - (2 * ((env->eflags >> 10) & 1)); - CC_OP = CC_OP_EFLAGS; - env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); -} - -void x86_cpu_exec_exit(CPUState *cs) -{ - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - - env->eflags = cpu_compute_eflags(env); -} - #ifndef CONFIG_USER_ONLY uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr) { diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c index e6cc2921e2..979230ac12 100644 --- a/target/i386/tcg/bpt_helper.c +++ b/target/i386/tcg/bpt_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c index 924dd3cd57..cc7ea9e8b9 100644 --- a/target/i386/tcg/cc_helper.c +++ b/target/i386/tcg/cc_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" const uint8_t parity_table[256] = { CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index 191471749f..a0f44431fe 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -23,6 +23,7 @@ #include "qemu/log.h" #include "sysemu/runstate.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_addend) { diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 03b35443a6..60ed93520a 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -26,11 +26,18 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" #include "fpu/softfloat-macros.h" +#include "helper-tcg.h" #ifdef CONFIG_SOFTMMU #include "hw/irq.h" #endif +/* float macros */ +#define FT0 (env->ft0) +#define ST0 (env->fpregs[env->fpstt].d) +#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) +#define ST1 ST(1) + #define FPU_RC_MASK 0xc00 #define FPU_RC_NEAR 0x000 #define FPU_RC_DOWN 0x400 @@ -2986,23 +2993,21 @@ void update_mxcsr_status(CPUX86State *env) void update_mxcsr_from_sse_status(CPUX86State *env) { - if (tcg_enabled()) { - uint8_t flags = get_float_exception_flags(&env->sse_status); - /* - * The MXCSR denormal flag has opposite semantics to - * float_flag_input_denormal (the softfloat code sets that flag - * only when flushing input denormals to zero, but SSE sets it - * only when not flushing them to zero), so is not converted - * here. - */ - env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) | - (flags & float_flag_divbyzero ? FPUS_ZE : 0) | - (flags & float_flag_overflow ? FPUS_OE : 0) | - (flags & float_flag_underflow ? FPUS_UE : 0) | - (flags & float_flag_inexact ? FPUS_PE : 0) | - (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE : - 0)); - } + uint8_t flags = get_float_exception_flags(&env->sse_status); + /* + * The MXCSR denormal flag has opposite semantics to + * float_flag_input_denormal (the softfloat code sets that flag + * only when flushing input denormals to zero, but SSE sets it + * only when not flushing them to zero), so is not converted + * here. + */ + env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) | + (flags & float_flag_divbyzero ? FPUS_ZE : 0) | + (flags & float_flag_overflow ? FPUS_OE : 0) | + (flags & float_flag_underflow ? FPUS_UE : 0) | + (flags & float_flag_inexact ? FPUS_PE : 0) | + (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE : + 0)); } void helper_update_mxcsr(CPUX86State *env) diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c index 4f89436b53..87fa7280ee 100644 --- a/target/i386/tcg/int_helper.c +++ b/target/i386/tcg/int_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "qapi/error.h" #include "qemu/guest-random.h" +#include "helper-tcg.h" //#define DEBUG_MULDIV diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 21ca3e3e88..e5cd2de1bf 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "qemu/int128.h" #include "qemu/atomic128.h" #include "tcg/tcg.h" +#include "helper-tcg.h" void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build index 02794226c2..6a1a73cdbf 100644 --- a/target/i386/tcg/meson.build +++ b/target/i386/tcg/meson.build @@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files( 'seg_helper.c', 'smm_helper.c', 'svm_helper.c', + 'tcg-cpu.c', 'translate.c'), if_false: files('tcg-stub.c')) diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index ae259d9145..c99370e5e3 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" +#include "helper-tcg.h" void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) { diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index fd966174b4..22423eedcd 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "helper-tcg.h" void helper_bndck(CPUX86State *env, uint32_t fail) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index e6ffa1f018..1255efe7e0 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/log.h" +#include "helper-tcg.h" //#define DEBUG_PCALL diff --git a/target/i386/tcg/smm_helper.c b/target/i386/tcg/smm_helper.c index d20e8edfdf..62d027abd3 100644 --- a/target/i386/tcg/smm_helper.c +++ b/target/i386/tcg/smm_helper.c @@ -22,6 +22,8 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/log.h" +#include "helper-tcg.h" + /* SMM support */ diff --git a/target/i386/tcg/svm_helper.c b/target/i386/tcg/svm_helper.c index 38931586e5..097bb9b83d 100644 --- a/target/i386/tcg/svm_helper.c +++ b/target/i386/tcg/svm_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "helper-tcg.h" /* Secure Virtual Machine helpers */ diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c new file mode 100644 index 0000000000..628dd29fe7 --- /dev/null +++ b/target/i386/tcg/tcg-cpu.c @@ -0,0 +1,71 @@ +/* + * i386 TCG cpu class initialization + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg-cpu.h" +#include "exec/exec-all.h" +#include "sysemu/runstate.h" +#include "helper-tcg.h" + +#if !defined(CONFIG_USER_ONLY) +#include "hw/i386/apic.h" +#endif + +/* Frob eflags into and out of the CPU temporary format. */ + +static void x86_cpu_exec_enter(CPUState *cs) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + + CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + env->df = 1 - (2 * ((env->eflags >> 10) & 1)); + CC_OP = CC_OP_EFLAGS; + env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); +} + +static void x86_cpu_exec_exit(CPUState *cs) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + + env->eflags = cpu_compute_eflags(env); +} + +static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + X86CPU *cpu = X86_CPU(cs); + + cpu->env.eip = tb->pc - tb->cs_base; +} + +void tcg_cpu_common_class_init(CPUClass *cc) +{ + cc->do_interrupt = x86_cpu_do_interrupt; + cc->cpu_exec_interrupt = x86_cpu_exec_interrupt; + cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; + cc->cpu_exec_enter = x86_cpu_exec_enter; + cc->cpu_exec_exit = x86_cpu_exec_exit; + cc->tcg_initialize = tcg_x86_init; + cc->tlb_fill = x86_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY + cc->debug_excp_handler = breakpoint_handler; +#endif +} diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e8f5f5803a..750f75c257 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -28,6 +28,7 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" +#include "helper-tcg.h" #include "trace-tcg.h" #include "exec/log.h" -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 13/17] i386: tcg: remove inline from cpu_load_eflags 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (11 preceding siblings ...) 2020-12-17 18:46 ` [PULL 12/17] i386: move TCG cpu class initialization to tcg/ Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 14/17] tcg: cpu_exec_{enter,exit} helpers Eduardo Habkost ` (4 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Paolo Bonzini, Claudio Fontana, Richard Henderson, Eduardo Habkost, Richard Henderson From: Claudio Fontana <cfontana@suse.de> make it a regular function. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-9-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/tcg/helper-tcg.h | 15 ++------------- target/i386/tcg/misc_helper.c | 13 +++++++++++++ 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 148edf49a3..c133c63555 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -78,19 +78,8 @@ void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, /* cc_helper.c */ extern const uint8_t parity_table[256]; -/* - * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS - * after generating a call to a helper that uses this. - */ -static inline void cpu_load_eflags(CPUX86State *env, int eflags, - int update_mask) -{ - CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - CC_OP = CC_OP_EFLAGS; - env->df = 1 - (2 * ((eflags >> 10) & 1)); - env->eflags = (env->eflags & ~update_mask) | - (eflags & update_mask) | 0x2; -} +/* misc_helper.c */ +void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask); /* svm_helper.c */ void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index c99370e5e3..0bd6c95749 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -26,6 +26,19 @@ #include "exec/address-spaces.h" #include "helper-tcg.h" +/* + * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS + * after generating a call to a helper that uses this. + */ +void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask) +{ + CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + CC_OP = CC_OP_EFLAGS; + env->df = 1 - (2 * ((eflags >> 10) & 1)); + env->eflags = (env->eflags & ~update_mask) | + (eflags & update_mask) | 0x2; +} + void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) { #ifdef CONFIG_USER_ONLY -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 14/17] tcg: cpu_exec_{enter,exit} helpers 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (12 preceding siblings ...) 2020-12-17 18:46 ` [PULL 13/17] i386: tcg: remove inline from cpu_load_eflags Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 15/17] tcg: make CPUClass.cpu_exec_* optional Eduardo Habkost ` (3 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Paolo Bonzini, Richard Henderson, Alex Bennée, Eduardo Habkost, Richard Henderson Move invocation of CPUClass.cpu_exec_*() to separate helpers, to make it easier to refactor that code later. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-10-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- accel/tcg/cpu-exec.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c2c26489c7..58117f175a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -236,9 +236,22 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles, } #endif -void cpu_exec_step_atomic(CPUState *cpu) +static void cpu_exec_enter(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + cc->cpu_exec_enter(cpu); +} + +static void cpu_exec_exit(CPUState *cpu) { CPUClass *cc = CPU_GET_CLASS(cpu); + + cc->cpu_exec_exit(cpu); +} + +void cpu_exec_step_atomic(CPUState *cpu) +{ TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; @@ -257,11 +270,11 @@ void cpu_exec_step_atomic(CPUState *cpu) /* Since we got here, we know that parallel_cpus must be true. */ parallel_cpus = false; - cc->cpu_exec_enter(cpu); + cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); - cc->cpu_exec_exit(cpu); + cpu_exec_exit(cpu); } else { /* * The mmap_lock is dropped by tb_gen_code if it runs out of @@ -713,7 +726,7 @@ int cpu_exec(CPUState *cpu) rcu_read_lock(); - cc->cpu_exec_enter(cpu); + cpu_exec_enter(cpu); /* Calculate difference between guest clock and host clock. * This delay includes the delay of the last cycle, so @@ -775,7 +788,7 @@ int cpu_exec(CPUState *cpu) } } - cc->cpu_exec_exit(cpu); + cpu_exec_exit(cpu); rcu_read_unlock(); return ret; -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 15/17] tcg: make CPUClass.cpu_exec_* optional 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (13 preceding siblings ...) 2020-12-17 18:46 ` [PULL 14/17] tcg: cpu_exec_{enter,exit} helpers Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 16/17] tcg: Make CPUClass.debug_excp_handler optional Eduardo Habkost ` (2 subsequent siblings) 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Paolo Bonzini, Alex Bennée, Eduardo Habkost, Richard Henderson This will let us simplify the code that initializes CPU class methods, when we move cpu_exec_*() to a separate struct. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201212155530.23098-11-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- accel/tcg/cpu-exec.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 58117f175a..36dde32ff9 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -240,14 +240,18 @@ static void cpu_exec_enter(CPUState *cpu) { CPUClass *cc = CPU_GET_CLASS(cpu); - cc->cpu_exec_enter(cpu); + if (cc->cpu_exec_enter) { + cc->cpu_exec_enter(cpu); + } } static void cpu_exec_exit(CPUState *cpu) { CPUClass *cc = CPU_GET_CLASS(cpu); - cc->cpu_exec_exit(cpu); + if (cc->cpu_exec_exit) { + cc->cpu_exec_exit(cpu); + } } void cpu_exec_step_atomic(CPUState *cpu) @@ -619,7 +623,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { - if (cc->cpu_exec_interrupt(cpu, interrupt_request)) { + if (cc->cpu_exec_interrupt && + cc->cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { replay_interrupt(); } -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 16/17] tcg: Make CPUClass.debug_excp_handler optional 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (14 preceding siblings ...) 2020-12-17 18:46 ` [PULL 15/17] tcg: make CPUClass.cpu_exec_* optional Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 18:46 ` [PULL 17/17] cpu: Remove unnecessary noop methods Eduardo Habkost 2020-12-17 20:48 ` [PULL 00/17] x86 queue, 2020-12-17 Peter Maydell 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Paolo Bonzini, Alex Bennée, Eduardo Habkost, Richard Henderson Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201212155530.23098-12-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- accel/tcg/cpu-exec.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 36dde32ff9..8689c54499 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -482,7 +482,9 @@ static inline void cpu_handle_debug_exception(CPUState *cpu) } } - cc->debug_excp_handler(cpu); + if (cc->debug_excp_handler) { + cc->debug_excp_handler(cpu); + } } static inline bool cpu_handle_exception(CPUState *cpu, int *ret) -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PULL 17/17] cpu: Remove unnecessary noop methods 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (15 preceding siblings ...) 2020-12-17 18:46 ` [PULL 16/17] tcg: Make CPUClass.debug_excp_handler optional Eduardo Habkost @ 2020-12-17 18:46 ` Eduardo Habkost 2020-12-17 20:48 ` [PULL 00/17] x86 queue, 2020-12-17 Peter Maydell 17 siblings, 0 replies; 26+ messages in thread From: Eduardo Habkost @ 2020-12-17 18:46 UTC (permalink / raw) To: Peter Maydell, qemu-devel Cc: Paolo Bonzini, Philippe Mathieu-Daudé, Alex Bennée, Eduardo Habkost, Richard Henderson In the previous commits we made cpu_exec_* and debug_excp_handler optional, so we can now remove these no-op handlers. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201212155530.23098-13-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- hw/core/cpu.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 5c89c858aa..7553411653 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -199,15 +199,6 @@ static bool cpu_common_virtio_is_big_endian(CPUState *cpu) return target_words_bigendian(); } -static void cpu_common_noop(CPUState *cpu) -{ -} - -static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) -{ - return false; -} - #if !defined(CONFIG_USER_ONLY) GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) { @@ -425,11 +416,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->gdb_read_register = cpu_common_gdb_read_register; k->gdb_write_register = cpu_common_gdb_write_register; k->virtio_is_big_endian = cpu_common_virtio_is_big_endian; - k->debug_excp_handler = cpu_common_noop; k->debug_check_watchpoint = cpu_common_debug_check_watchpoint; - k->cpu_exec_enter = cpu_common_noop; - k->cpu_exec_exit = cpu_common_noop; - k->cpu_exec_interrupt = cpu_common_exec_interrupt; k->adjust_watchpoint_address = cpu_adjust_watchpoint_address; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize = cpu_common_realizefn; -- 2.28.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PULL 00/17] x86 queue, 2020-12-17 2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost ` (16 preceding siblings ...) 2020-12-17 18:46 ` [PULL 17/17] cpu: Remove unnecessary noop methods Eduardo Habkost @ 2020-12-17 20:48 ` Peter Maydell 17 siblings, 0 replies; 26+ messages in thread From: Peter Maydell @ 2020-12-17 20:48 UTC (permalink / raw) To: Eduardo Habkost; +Cc: Paolo Bonzini, QEMU Developers, Richard Henderson On Thu, 17 Dec 2020 at 18:46, Eduardo Habkost <ehabkost@redhat.com> wrote: > > Note that this is using my new gitlab.com repository URL, which > was updated on commit f953c100693d ("MAINTAINERS: Update my git > repository URLs"). > > The following changes since commit af3f37319cb1e1ca0c42842ecdbd1bcfc64a4b6f: > > Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-12-15 21:24:31 +0000) > > are available in the Git repository at: > > https://gitlab.com/ehabkost/qemu.git tags/x86-next-pull-request > > for you to fetch changes up to 9fb75013d864489a91ba05e6009ed79c250d4064: > > cpu: Remove unnecessary noop methods (2020-12-16 15:50:33 -0500) > > ---------------------------------------------------------------- > x86 queue, 2020-12-17 > > Features: > * AVX512_FP16 feature (Cathy Zhang) > > Cleanups: > * accel code cleanup (Claudio Fontana) > * hyperv initialization cleanup (Vitaly Kuznetsov) > > ---------------------------------------------------------------- Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0 for any user-visible changes. -- PMM ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2020-12-18 8:51 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-17 18:46 [PULL 00/17] x86 queue, 2020-12-17 Eduardo Habkost
2020-12-17 18:46 ` [PULL 01/17] i386: move kvm accel files into kvm/ Eduardo Habkost
2020-12-17 18:46 ` [PULL 02/17] i386: move whpx accel files into whpx/ Eduardo Habkost
2020-12-17 18:46 ` [PULL 03/17] i386: move hax accel files into hax/ Eduardo Habkost
2020-12-17 18:46 ` [PULL 04/17] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Eduardo Habkost
2020-12-17 18:46 ` [PULL 05/17] i386: move TCG accel files into tcg/ Eduardo Habkost
2020-12-17 18:46 ` [PULL 06/17] i386: move cpu dump out of helper.c into cpu-dump.c Eduardo Habkost
2020-12-17 18:46 ` [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() Eduardo Habkost
2020-12-17 22:33 ` Claudio Fontana
2020-12-17 22:53 ` Eduardo Habkost
2020-12-17 23:34 ` Claudio Fontana
2020-12-17 23:47 ` Eduardo Habkost
2020-12-18 0:07 ` Claudio Fontana
2020-12-18 1:05 ` Eduardo Habkost
2020-12-18 8:50 ` Claudio Fontana
2020-12-17 18:46 ` [PULL 08/17] i386: move hyperv_interface_id " Eduardo Habkost
2020-12-17 18:46 ` [PULL 09/17] i386: move hyperv_version_id " Eduardo Habkost
2020-12-17 18:46 ` [PULL 10/17] i386: move hyperv_limits " Eduardo Habkost
2020-12-17 18:46 ` [PULL 11/17] x86/cpu: Add AVX512_FP16 cpu feature Eduardo Habkost
2020-12-17 18:46 ` [PULL 12/17] i386: move TCG cpu class initialization to tcg/ Eduardo Habkost
2020-12-17 18:46 ` [PULL 13/17] i386: tcg: remove inline from cpu_load_eflags Eduardo Habkost
2020-12-17 18:46 ` [PULL 14/17] tcg: cpu_exec_{enter,exit} helpers Eduardo Habkost
2020-12-17 18:46 ` [PULL 15/17] tcg: make CPUClass.cpu_exec_* optional Eduardo Habkost
2020-12-17 18:46 ` [PULL 16/17] tcg: Make CPUClass.debug_excp_handler optional Eduardo Habkost
2020-12-17 18:46 ` [PULL 17/17] cpu: Remove unnecessary noop methods Eduardo Habkost
2020-12-17 20:48 ` [PULL 00/17] x86 queue, 2020-12-17 Peter Maydell
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).