* [PATCH] gdb: riscv: Add target description @ 2020-12-23 16:28 Sylvain Pelissier 2020-12-29 4:10 ` Bin Meng 0 siblings, 1 reply; 6+ messages in thread From: Sylvain Pelissier @ 2020-12-23 16:28 UTC (permalink / raw) To: qemu-devel Cc: Palmer Dabbelt, Alistair Francis, qemu-riscv, Sagar Karandikar, Bastian Koppelmann [-- Attachment #1: Type: text/plain, Size: 1177 bytes --] Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> --- target/riscv/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 254cd83f8b..489d66038c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,6 +556,15 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static gchar *riscv_gdb_arch_name(CPUState *cs) +{ + #ifdef TARGET_RISCV64 + return g_strdup("riscv:rv64"); + #else + return g_strdup("riscv:rv32"); + #endif +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -591,6 +600,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; #endif + cc->gdb_arch_name = riscv_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_initialize = riscv_translate_init; cc->tlb_fill = riscv_cpu_tlb_fill; -- 2.25.1 [-- Attachment #2: Type: text/html, Size: 1493 bytes --] ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] gdb: riscv: Add target description 2020-12-23 16:28 [PATCH] gdb: riscv: Add target description Sylvain Pelissier @ 2020-12-29 4:10 ` Bin Meng 2020-12-29 16:36 ` Sylvain Pelissier 0 siblings, 1 reply; 6+ messages in thread From: Bin Meng @ 2020-12-29 4:10 UTC (permalink / raw) To: Sylvain Pelissier Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt On Thu, Dec 24, 2020 at 1:09 AM Sylvain Pelissier <sylvain.pelissier@gmail.com> wrote: > > Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. > > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> > --- > target/riscv/cpu.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 254cd83f8b..489d66038c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -556,6 +556,15 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > +static gchar *riscv_gdb_arch_name(CPUState *cs) > +{ > + #ifdef TARGET_RISCV64 Use riscv_cpu_is_32bit() instead of #ifdefs > + return g_strdup("riscv:rv64"); > + #else > + return g_strdup("riscv:rv32"); > + #endif > +} > + > static void riscv_cpu_class_init(ObjectClass *c, void *data) > { > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > @@ -591,6 +600,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) > /* For now, mark unmigratable: */ > cc->vmsd = &vmstate_riscv_cpu; > #endif > + cc->gdb_arch_name = riscv_gdb_arch_name; > #ifdef CONFIG_TCG > cc->tcg_initialize = riscv_translate_init; > cc->tlb_fill = riscv_cpu_tlb_fill; > -- Regards, Bin ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] gdb: riscv: Add target description 2020-12-29 4:10 ` Bin Meng @ 2020-12-29 16:36 ` Sylvain Pelissier 2020-12-30 0:26 ` Bin Meng 0 siblings, 1 reply; 6+ messages in thread From: Sylvain Pelissier @ 2020-12-29 16:36 UTC (permalink / raw) To: Bin Meng Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt [-- Attachment #1: Type: text/plain, Size: 2708 bytes --] Thank you for your remark here is the new patch: Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> --- target/riscv/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 254cd83f8b..ed4971978b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static gchar *riscv_gdb_arch_name(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (riscv_cpu_is_32bit(env)) { + return g_strdup("riscv:rv32"); + } else { + return g_strdup("riscv:rv64"); + } +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; #endif + cc->gdb_arch_name = riscv_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_initialize = riscv_translate_init; cc->tlb_fill = riscv_cpu_tlb_fill; -- 2.25.1 Regards Sylvain On Tue, 29 Dec 2020 at 05:11, Bin Meng <bmeng.cn@gmail.com> wrote: > On Thu, Dec 24, 2020 at 1:09 AM Sylvain Pelissier > <sylvain.pelissier@gmail.com> wrote: > > > > Target description is not currently implemented in RISC-V architecture. > Thus GDB won't set it properly when attached. The patch implements the > target description response. > > > > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> > > --- > > target/riscv/cpu.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 254cd83f8b..489d66038c 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -556,6 +556,15 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > +static gchar *riscv_gdb_arch_name(CPUState *cs) > > +{ > > + #ifdef TARGET_RISCV64 > > Use riscv_cpu_is_32bit() instead of #ifdefs > > > + return g_strdup("riscv:rv64"); > > + #else > > + return g_strdup("riscv:rv32"); > > + #endif > > +} > > + > > static void riscv_cpu_class_init(ObjectClass *c, void *data) > > { > > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > > @@ -591,6 +600,7 @@ static void riscv_cpu_class_init(ObjectClass *c, > void *data) > > /* For now, mark unmigratable: */ > > cc->vmsd = &vmstate_riscv_cpu; > > #endif > > + cc->gdb_arch_name = riscv_gdb_arch_name; > > #ifdef CONFIG_TCG > > cc->tcg_initialize = riscv_translate_init; > > cc->tlb_fill = riscv_cpu_tlb_fill; > > -- > > Regards, > Bin > [-- Attachment #2: Type: text/html, Size: 3793 bytes --] ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] gdb: riscv: Add target description 2020-12-29 16:36 ` Sylvain Pelissier @ 2020-12-30 0:26 ` Bin Meng 2020-12-30 7:42 ` Sylvain Pelissier 0 siblings, 1 reply; 6+ messages in thread From: Bin Meng @ 2020-12-30 0:26 UTC (permalink / raw) To: Sylvain Pelissier Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt Hi Sylvain, On Wed, Dec 30, 2020 at 12:37 AM Sylvain Pelissier <sylvain.pelissier@gmail.com> wrote: > > Thank you for your remark here is the new patch: This should not be put into the commit message. Previous commit message is missing. > > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> > --- > target/riscv/cpu.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > Regards, Bin ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] gdb: riscv: Add target description 2020-12-30 0:26 ` Bin Meng @ 2020-12-30 7:42 ` Sylvain Pelissier 2020-12-30 7:57 ` Bin Meng 0 siblings, 1 reply; 6+ messages in thread From: Sylvain Pelissier @ 2020-12-30 7:42 UTC (permalink / raw) To: Bin Meng Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt [-- Attachment #1: Type: text/plain, Size: 1775 bytes --] Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> --- target/riscv/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 254cd83f8b..ed4971978b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static gchar *riscv_gdb_arch_name(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (riscv_cpu_is_32bit(env)) { + return g_strdup("riscv:rv32"); + } else { + return g_strdup("riscv:rv64"); + } +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; #endif + cc->gdb_arch_name = riscv_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_initialize = riscv_translate_init; cc->tlb_fill = riscv_cpu_tlb_fill; -- 2.25.1 On Wed, 30 Dec 2020 at 01:26, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi Sylvain, > > On Wed, Dec 30, 2020 at 12:37 AM Sylvain Pelissier > <sylvain.pelissier@gmail.com> wrote: > > > > Thank you for your remark here is the new patch: > > This should not be put into the commit message. > > Previous commit message is missing. > > > > > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> > > --- > > target/riscv/cpu.c | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > Regards, > Bin > [-- Attachment #2: Type: text/html, Size: 2561 bytes --] ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] gdb: riscv: Add target description 2020-12-30 7:42 ` Sylvain Pelissier @ 2020-12-30 7:57 ` Bin Meng 0 siblings, 0 replies; 6+ messages in thread From: Bin Meng @ 2020-12-30 7:57 UTC (permalink / raw) To: Sylvain Pelissier Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt On Wed, Dec 30, 2020 at 3:42 PM Sylvain Pelissier <sylvain.pelissier@gmail.com> wrote: > > Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. > > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> > --- > target/riscv/cpu.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > Please specify the version in the email title, like v2. Otherwise, Reviewed-by: Bin Meng <bin.meng@windriver.com> Regards, Bin ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-12-30 7:59 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-12-23 16:28 [PATCH] gdb: riscv: Add target description Sylvain Pelissier 2020-12-29 4:10 ` Bin Meng 2020-12-29 16:36 ` Sylvain Pelissier 2020-12-30 0:26 ` Bin Meng 2020-12-30 7:42 ` Sylvain Pelissier 2020-12-30 7:57 ` Bin Meng
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