* [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Bin Meng
@ 2021-10-20 1:41 ` Bin Meng
2021-10-20 23:06 ` Alistair Francis
2021-10-21 8:48 ` Igor Mammedov
2021-10-20 1:41 ` [PATCH v2 2/6] hw/riscv: opentitan: " Bin Meng
` (5 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-20 1:41 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Igor Mammedov, Philippe Mathieu-Daudé
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v2:
- split RAM into low and high regions using aliases to machine->ram
- rename mc->default_ram_id to "microchip.icicle.kit.ram"
hw/riscv/microchip_pfsoc.c | 36 ++++++++++++++++++++----------------
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index e475b6d511..3fc8545562 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -463,7 +463,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
MemoryRegion *mem_high = g_new(MemoryRegion, 1);
MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
- uint64_t mem_high_size;
+ uint64_t mem_low_size, mem_high_size;
hwaddr firmware_load_addr;
const char *firmware_name;
bool kernel_as_payload = false;
@@ -485,31 +485,34 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
TYPE_MICROCHIP_PFSOC);
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
+ /* Split RAM into low and high regions using aliases to machine->ram */
+ mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
+ mem_high_size = machine->ram_size - mem_low_size;
+ memory_region_init_alias(mem_low, NULL,
+ "microchip.icicle.kit.ram_low", machine->ram,
+ 0, mem_low_size);
+ memory_region_init_alias(mem_high, NULL,
+ "microchip.icicle.kit.ram_high", machine->ram,
+ mem_low_size, mem_high_size);
+
/* Register RAM */
- memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
- memmap[MICROCHIP_PFSOC_DRAM_LO].size,
- &error_fatal);
- memory_region_init_alias(mem_low_alias, NULL,
- "microchip.icicle.kit.ram_low.alias",
- mem_low, 0,
- memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
memory_region_add_subregion(system_memory,
memmap[MICROCHIP_PFSOC_DRAM_LO].base,
mem_low);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_DRAM_HI].base,
+ mem_high);
+
+ /* Create aliases for the low and high RAM regions */
+ memory_region_init_alias(mem_low_alias, NULL,
+ "microchip.icicle.kit.ram_low.alias",
+ mem_low, 0, mem_low_size);
memory_region_add_subregion(system_memory,
memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
mem_low_alias);
-
- mem_high_size = machine->ram_size - 1 * GiB;
-
- memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
- mem_high_size, &error_fatal);
memory_region_init_alias(mem_high_alias, NULL,
"microchip.icicle.kit.ram_high.alias",
mem_high, 0, mem_high_size);
- memory_region_add_subregion(system_memory,
- memmap[MICROCHIP_PFSOC_DRAM_HI].base,
- mem_high);
memory_region_add_subregion(system_memory,
memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
mem_high_alias);
@@ -606,6 +609,7 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
mc->default_cpus = mc->min_cpus;
+ mc->default_ram_id = "microchip.icicle.kit.ram";
/*
* Map 513 MiB high memory, the mimimum required high memory size, because
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Bin Meng
@ 2021-10-20 23:06 ` Alistair Francis
2021-10-21 8:48 ` Igor Mammedov
1 sibling, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2021-10-20 23:06 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Philippe Mathieu-Daudé,
Alistair Francis, qemu-devel@nongnu.org Developers,
Igor Mammedov
On Wed, Oct 20, 2021 at 11:41 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v2:
> - split RAM into low and high regions using aliases to machine->ram
> - rename mc->default_ram_id to "microchip.icicle.kit.ram"
>
> hw/riscv/microchip_pfsoc.c | 36 ++++++++++++++++++++----------------
> 1 file changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index e475b6d511..3fc8545562 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -463,7 +463,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
> MemoryRegion *mem_high = g_new(MemoryRegion, 1);
> MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
> - uint64_t mem_high_size;
> + uint64_t mem_low_size, mem_high_size;
> hwaddr firmware_load_addr;
> const char *firmware_name;
> bool kernel_as_payload = false;
> @@ -485,31 +485,34 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> TYPE_MICROCHIP_PFSOC);
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> + /* Split RAM into low and high regions using aliases to machine->ram */
> + mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
> + mem_high_size = machine->ram_size - mem_low_size;
> + memory_region_init_alias(mem_low, NULL,
> + "microchip.icicle.kit.ram_low", machine->ram,
> + 0, mem_low_size);
> + memory_region_init_alias(mem_high, NULL,
> + "microchip.icicle.kit.ram_high", machine->ram,
> + mem_low_size, mem_high_size);
> +
> /* Register RAM */
> - memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
> - memmap[MICROCHIP_PFSOC_DRAM_LO].size,
> - &error_fatal);
> - memory_region_init_alias(mem_low_alias, NULL,
> - "microchip.icicle.kit.ram_low.alias",
> - mem_low, 0,
> - memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
> memory_region_add_subregion(system_memory,
> memmap[MICROCHIP_PFSOC_DRAM_LO].base,
> mem_low);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_DRAM_HI].base,
> + mem_high);
> +
> + /* Create aliases for the low and high RAM regions */
> + memory_region_init_alias(mem_low_alias, NULL,
> + "microchip.icicle.kit.ram_low.alias",
> + mem_low, 0, mem_low_size);
> memory_region_add_subregion(system_memory,
> memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
> mem_low_alias);
> -
> - mem_high_size = machine->ram_size - 1 * GiB;
> -
> - memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
> - mem_high_size, &error_fatal);
> memory_region_init_alias(mem_high_alias, NULL,
> "microchip.icicle.kit.ram_high.alias",
> mem_high, 0, mem_high_size);
> - memory_region_add_subregion(system_memory,
> - memmap[MICROCHIP_PFSOC_DRAM_HI].base,
> - mem_high);
> memory_region_add_subregion(system_memory,
> memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
> mem_high_alias);
> @@ -606,6 +609,7 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
> MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
> mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
> mc->default_cpus = mc->min_cpus;
> + mc->default_ram_id = "microchip.icicle.kit.ram";
>
> /*
> * Map 513 MiB high memory, the mimimum required high memory size, because
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Bin Meng
2021-10-20 23:06 ` Alistair Francis
@ 2021-10-21 8:48 ` Igor Mammedov
1 sibling, 0 replies; 19+ messages in thread
From: Igor Mammedov @ 2021-10-21 8:48 UTC (permalink / raw)
To: Bin Meng
Cc: qemu-riscv, Alistair Francis, qemu-devel, Philippe Mathieu-Daudé
On Wed, 20 Oct 2021 09:41:07 +0800
Bin Meng <bmeng.cn@gmail.com> wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
>
> ---
>
> Changes in v2:
> - split RAM into low and high regions using aliases to machine->ram
> - rename mc->default_ram_id to "microchip.icicle.kit.ram"
>
> hw/riscv/microchip_pfsoc.c | 36 ++++++++++++++++++++----------------
> 1 file changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index e475b6d511..3fc8545562 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -463,7 +463,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
> MemoryRegion *mem_high = g_new(MemoryRegion, 1);
> MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
> - uint64_t mem_high_size;
> + uint64_t mem_low_size, mem_high_size;
> hwaddr firmware_load_addr;
> const char *firmware_name;
> bool kernel_as_payload = false;
> @@ -485,31 +485,34 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> TYPE_MICROCHIP_PFSOC);
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> + /* Split RAM into low and high regions using aliases to machine->ram */
> + mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
> + mem_high_size = machine->ram_size - mem_low_size;
> + memory_region_init_alias(mem_low, NULL,
> + "microchip.icicle.kit.ram_low", machine->ram,
> + 0, mem_low_size);
> + memory_region_init_alias(mem_high, NULL,
> + "microchip.icicle.kit.ram_high", machine->ram,
> + mem_low_size, mem_high_size);
> +
> /* Register RAM */
> - memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
> - memmap[MICROCHIP_PFSOC_DRAM_LO].size,
> - &error_fatal);
> - memory_region_init_alias(mem_low_alias, NULL,
> - "microchip.icicle.kit.ram_low.alias",
> - mem_low, 0,
> - memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
> memory_region_add_subregion(system_memory,
> memmap[MICROCHIP_PFSOC_DRAM_LO].base,
> mem_low);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_DRAM_HI].base,
> + mem_high);
> +
> + /* Create aliases for the low and high RAM regions */
> + memory_region_init_alias(mem_low_alias, NULL,
> + "microchip.icicle.kit.ram_low.alias",
> + mem_low, 0, mem_low_size);
> memory_region_add_subregion(system_memory,
> memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
> mem_low_alias);
> -
> - mem_high_size = machine->ram_size - 1 * GiB;
> -
> - memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
> - mem_high_size, &error_fatal);
> memory_region_init_alias(mem_high_alias, NULL,
> "microchip.icicle.kit.ram_high.alias",
> mem_high, 0, mem_high_size);
> - memory_region_add_subregion(system_memory,
> - memmap[MICROCHIP_PFSOC_DRAM_HI].base,
> - mem_high);
> memory_region_add_subregion(system_memory,
> memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
> mem_high_alias);
> @@ -606,6 +609,7 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
> MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
> mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
> mc->default_cpus = mc->min_cpus;
> + mc->default_ram_id = "microchip.icicle.kit.ram";
>
> /*
> * Map 513 MiB high memory, the mimimum required high memory size, because
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Bin Meng
2021-10-20 1:41 ` [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Bin Meng
@ 2021-10-20 1:41 ` Bin Meng
2021-10-20 13:01 ` Philippe Mathieu-Daudé
` (2 more replies)
2021-10-20 1:41 ` [PATCH v2 3/6] hw/riscv: shakti_c: " Bin Meng
` (4 subsequent siblings)
6 siblings, 3 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-20 1:41 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Igor Mammedov, Philippe Mathieu-Daudé
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
While at it add check for user supplied RAM size and error out if it
mismatches board expected value.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v2:
- add RAM size check
- assign mc->default_ram_size
hw/riscv/opentitan.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 9803ae6d70..5d568ea58a 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -19,6 +19,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/cutils.h"
#include "hw/riscv/opentitan.h"
#include "qapi/error.h"
#include "hw/boards.h"
@@ -64,20 +65,25 @@ static const MemMapEntry ibex_memmap[] = {
static void opentitan_board_init(MachineState *machine)
{
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
const MemMapEntry *memmap = ibex_memmap;
OpenTitanState *s = g_new0(OpenTitanState, 1);
MemoryRegion *sys_mem = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc,
TYPE_RISCV_IBEX_SOC);
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
- memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
- memmap[IBEX_DEV_RAM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
- memmap[IBEX_DEV_RAM].base, main_mem);
+ memmap[IBEX_DEV_RAM].base, machine->ram);
if (machine->firmware) {
riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
@@ -95,6 +101,8 @@ static void opentitan_machine_init(MachineClass *mc)
mc->init = opentitan_board_init;
mc->max_cpus = 1;
mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
+ mc->default_ram_id = "riscv.lowrisc.ibex.ram";
+ mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
}
DEFINE_MACHINE("opentitan", opentitan_machine_init)
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 2/6] hw/riscv: opentitan: " Bin Meng
@ 2021-10-20 13:01 ` Philippe Mathieu-Daudé
2021-10-20 23:10 ` Alistair Francis
2021-10-21 8:44 ` Igor Mammedov
2 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-20 13:01 UTC (permalink / raw)
To: Bin Meng, Alistair Francis, qemu-devel, qemu-riscv; +Cc: Igor Mammedov
On 10/20/21 03:41, Bin Meng wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> While at it add check for user supplied RAM size and error out if it
> mismatches board expected value.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v2:
> - add RAM size check
> - assign mc->default_ram_size
>
> hw/riscv/opentitan.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 2/6] hw/riscv: opentitan: " Bin Meng
2021-10-20 13:01 ` Philippe Mathieu-Daudé
@ 2021-10-20 23:10 ` Alistair Francis
2021-10-21 8:44 ` Igor Mammedov
2 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2021-10-20 23:10 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Philippe Mathieu-Daudé,
Alistair Francis, qemu-devel@nongnu.org Developers,
Igor Mammedov
On Wed, Oct 20, 2021 at 11:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> While at it add check for user supplied RAM size and error out if it
> mismatches board expected value.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v2:
> - add RAM size check
> - assign mc->default_ram_size
>
> hw/riscv/opentitan.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 9803ae6d70..5d568ea58a 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -19,6 +19,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/cutils.h"
> #include "hw/riscv/opentitan.h"
> #include "qapi/error.h"
> #include "hw/boards.h"
> @@ -64,20 +65,25 @@ static const MemMapEntry ibex_memmap[] = {
>
> static void opentitan_board_init(MachineState *machine)
> {
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> const MemMapEntry *memmap = ibex_memmap;
> OpenTitanState *s = g_new0(OpenTitanState, 1);
> MemoryRegion *sys_mem = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> +
> + if (machine->ram_size != mc->default_ram_size) {
> + char *sz = size_to_str(mc->default_ram_size);
> + error_report("Invalid RAM size, should be %s", sz);
> + g_free(sz);
> + exit(EXIT_FAILURE);
> + }
>
> /* Initialize SoC */
> object_initialize_child(OBJECT(machine), "soc", &s->soc,
> TYPE_RISCV_IBEX_SOC);
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> - memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
> - memmap[IBEX_DEV_RAM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[IBEX_DEV_RAM].base, main_mem);
> + memmap[IBEX_DEV_RAM].base, machine->ram);
>
> if (machine->firmware) {
> riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
> @@ -95,6 +101,8 @@ static void opentitan_machine_init(MachineClass *mc)
> mc->init = opentitan_board_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
> + mc->default_ram_id = "riscv.lowrisc.ibex.ram";
> + mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
> }
>
> DEFINE_MACHINE("opentitan", opentitan_machine_init)
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 2/6] hw/riscv: opentitan: " Bin Meng
2021-10-20 13:01 ` Philippe Mathieu-Daudé
2021-10-20 23:10 ` Alistair Francis
@ 2021-10-21 8:44 ` Igor Mammedov
2 siblings, 0 replies; 19+ messages in thread
From: Igor Mammedov @ 2021-10-21 8:44 UTC (permalink / raw)
To: Bin Meng
Cc: qemu-riscv, Alistair Francis, qemu-devel, Philippe Mathieu-Daudé
On Wed, 20 Oct 2021 09:41:08 +0800
Bin Meng <bmeng.cn@gmail.com> wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> While at it add check for user supplied RAM size and error out if it
> mismatches board expected value.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
>
> ---
>
> Changes in v2:
> - add RAM size check
> - assign mc->default_ram_size
>
> hw/riscv/opentitan.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 9803ae6d70..5d568ea58a 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -19,6 +19,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/cutils.h"
> #include "hw/riscv/opentitan.h"
> #include "qapi/error.h"
> #include "hw/boards.h"
> @@ -64,20 +65,25 @@ static const MemMapEntry ibex_memmap[] = {
>
> static void opentitan_board_init(MachineState *machine)
> {
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> const MemMapEntry *memmap = ibex_memmap;
> OpenTitanState *s = g_new0(OpenTitanState, 1);
> MemoryRegion *sys_mem = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> +
> + if (machine->ram_size != mc->default_ram_size) {
> + char *sz = size_to_str(mc->default_ram_size);
> + error_report("Invalid RAM size, should be %s", sz);
> + g_free(sz);
> + exit(EXIT_FAILURE);
> + }
>
> /* Initialize SoC */
> object_initialize_child(OBJECT(machine), "soc", &s->soc,
> TYPE_RISCV_IBEX_SOC);
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> - memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
> - memmap[IBEX_DEV_RAM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[IBEX_DEV_RAM].base, main_mem);
> + memmap[IBEX_DEV_RAM].base, machine->ram);
>
> if (machine->firmware) {
> riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
> @@ -95,6 +101,8 @@ static void opentitan_machine_init(MachineClass *mc)
> mc->init = opentitan_board_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
> + mc->default_ram_id = "riscv.lowrisc.ibex.ram";
> + mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
> }
>
> DEFINE_MACHINE("opentitan", opentitan_machine_init)
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Bin Meng
2021-10-20 1:41 ` [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Bin Meng
2021-10-20 1:41 ` [PATCH v2 2/6] hw/riscv: opentitan: " Bin Meng
@ 2021-10-20 1:41 ` Bin Meng
2021-10-20 23:11 ` Alistair Francis
2021-10-20 1:41 ` [PATCH v2 4/6] hw/riscv: sifive_e: " Bin Meng
` (3 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Bin Meng @ 2021-10-20 1:41 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Igor Mammedov, Philippe Mathieu-Daudé
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
(no changes since v1)
hw/riscv/shakti_c.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index d7d1f91fa5..90e2cf609f 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -45,7 +45,6 @@ static void shakti_c_machine_state_init(MachineState *mstate)
{
ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
/* Allow only Shakti C CPU for this platform */
if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
@@ -59,11 +58,9 @@ static void shakti_c_machine_state_init(MachineState *mstate)
qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
/* register RAM */
- memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
- mstate->ram_size, &error_fatal);
memory_region_add_subregion(system_memory,
shakti_c_memmap[SHAKTI_C_RAM].base,
- main_mem);
+ mstate->ram);
/* ROM reset vector */
riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
@@ -88,6 +85,7 @@ static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
mc->desc = "RISC-V Board compatible with Shakti SDK";
mc->init = shakti_c_machine_state_init;
mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
+ mc->default_ram_id = "riscv.shakti.c.ram";
}
static const TypeInfo shakti_c_machine_type_info = {
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 3/6] hw/riscv: shakti_c: " Bin Meng
@ 2021-10-20 23:11 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2021-10-20 23:11 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Philippe Mathieu-Daudé,
Alistair Francis, qemu-devel@nongnu.org Developers,
Igor Mammedov
On Wed, Oct 20, 2021 at 11:46 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> (no changes since v1)
>
> hw/riscv/shakti_c.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> index d7d1f91fa5..90e2cf609f 100644
> --- a/hw/riscv/shakti_c.c
> +++ b/hw/riscv/shakti_c.c
> @@ -45,7 +45,6 @@ static void shakti_c_machine_state_init(MachineState *mstate)
> {
> ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
>
> /* Allow only Shakti C CPU for this platform */
> if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
> @@ -59,11 +58,9 @@ static void shakti_c_machine_state_init(MachineState *mstate)
> qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
>
> /* register RAM */
> - memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
> - mstate->ram_size, &error_fatal);
> memory_region_add_subregion(system_memory,
> shakti_c_memmap[SHAKTI_C_RAM].base,
> - main_mem);
> + mstate->ram);
>
> /* ROM reset vector */
> riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
> @@ -88,6 +85,7 @@ static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
> mc->desc = "RISC-V Board compatible with Shakti SDK";
> mc->init = shakti_c_machine_state_init;
> mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
> + mc->default_ram_id = "riscv.shakti.c.ram";
> }
>
> static const TypeInfo shakti_c_machine_type_info = {
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Bin Meng
` (2 preceding siblings ...)
2021-10-20 1:41 ` [PATCH v2 3/6] hw/riscv: shakti_c: " Bin Meng
@ 2021-10-20 1:41 ` Bin Meng
2021-10-20 13:02 ` Philippe Mathieu-Daudé
` (2 more replies)
2021-10-20 1:41 ` [PATCH v2 5/6] hw/riscv: sifive_u: " Bin Meng
` (2 subsequent siblings)
6 siblings, 3 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-20 1:41 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Igor Mammedov, Philippe Mathieu-Daudé
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
While at it add check for user supplied RAM size and error out if it
mismatches board expected value.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v2:
- add RAM size check
- assign mc->default_ram_size
hw/riscv/sifive_e.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 6e95ea5896..9b206407a6 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -29,6 +29,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/cutils.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/boards.h"
@@ -71,22 +72,27 @@ static const MemMapEntry sifive_e_memmap[] = {
static void sifive_e_machine_init(MachineState *machine)
{
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
const MemMapEntry *memmap = sifive_e_memmap;
SiFiveEState *s = RISCV_E_MACHINE(machine);
MemoryRegion *sys_mem = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
int i;
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
+
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* Data Tightly Integrated Memory */
- memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
- memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
- memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
+ memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
/* Mask ROM reset vector */
uint32_t reset_vec[4];
@@ -142,6 +148,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
mc->init = sifive_e_machine_init;
mc->max_cpus = 1;
mc->default_cpu_type = SIFIVE_E_CPU;
+ mc->default_ram_id = "riscv.sifive.e.ram";
+ mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
sifive_e_machine_set_revb);
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 4/6] hw/riscv: sifive_e: " Bin Meng
@ 2021-10-20 13:02 ` Philippe Mathieu-Daudé
2021-10-20 23:12 ` Alistair Francis
2021-10-21 8:43 ` Igor Mammedov
2 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-20 13:02 UTC (permalink / raw)
To: Bin Meng, Alistair Francis, qemu-devel, qemu-riscv; +Cc: Igor Mammedov
On 10/20/21 03:41, Bin Meng wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> While at it add check for user supplied RAM size and error out if it
> mismatches board expected value.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v2:
> - add RAM size check
> - assign mc->default_ram_size
>
> hw/riscv/sifive_e.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 4/6] hw/riscv: sifive_e: " Bin Meng
2021-10-20 13:02 ` Philippe Mathieu-Daudé
@ 2021-10-20 23:12 ` Alistair Francis
2021-10-21 8:43 ` Igor Mammedov
2 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2021-10-20 23:12 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Philippe Mathieu-Daudé,
Alistair Francis, qemu-devel@nongnu.org Developers,
Igor Mammedov
On Wed, Oct 20, 2021 at 11:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> While at it add check for user supplied RAM size and error out if it
> mismatches board expected value.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v2:
> - add RAM size check
> - assign mc->default_ram_size
>
> hw/riscv/sifive_e.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 6e95ea5896..9b206407a6 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -29,6 +29,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/cutils.h"
> #include "qemu/error-report.h"
> #include "qapi/error.h"
> #include "hw/boards.h"
> @@ -71,22 +72,27 @@ static const MemMapEntry sifive_e_memmap[] = {
>
> static void sifive_e_machine_init(MachineState *machine)
> {
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> const MemMapEntry *memmap = sifive_e_memmap;
>
> SiFiveEState *s = RISCV_E_MACHINE(machine);
> MemoryRegion *sys_mem = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> int i;
>
> + if (machine->ram_size != mc->default_ram_size) {
> + char *sz = size_to_str(mc->default_ram_size);
> + error_report("Invalid RAM size, should be %s", sz);
> + g_free(sz);
> + exit(EXIT_FAILURE);
> + }
> +
> /* Initialize SoC */
> object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> /* Data Tightly Integrated Memory */
> - memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
> - memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
> + memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
>
> /* Mask ROM reset vector */
> uint32_t reset_vec[4];
> @@ -142,6 +148,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> mc->init = sifive_e_machine_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = SIFIVE_E_CPU;
> + mc->default_ram_id = "riscv.sifive.e.ram";
> + mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
>
> object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
> sifive_e_machine_set_revb);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 4/6] hw/riscv: sifive_e: " Bin Meng
2021-10-20 13:02 ` Philippe Mathieu-Daudé
2021-10-20 23:12 ` Alistair Francis
@ 2021-10-21 8:43 ` Igor Mammedov
2 siblings, 0 replies; 19+ messages in thread
From: Igor Mammedov @ 2021-10-21 8:43 UTC (permalink / raw)
To: Bin Meng
Cc: qemu-riscv, Alistair Francis, qemu-devel, Philippe Mathieu-Daudé
On Wed, 20 Oct 2021 09:41:10 +0800
Bin Meng <bmeng.cn@gmail.com> wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> While at it add check for user supplied RAM size and error out if it
> mismatches board expected value.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
>
> ---
>
> Changes in v2:
> - add RAM size check
> - assign mc->default_ram_size
>
> hw/riscv/sifive_e.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 6e95ea5896..9b206407a6 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -29,6 +29,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/cutils.h"
> #include "qemu/error-report.h"
> #include "qapi/error.h"
> #include "hw/boards.h"
> @@ -71,22 +72,27 @@ static const MemMapEntry sifive_e_memmap[] = {
>
> static void sifive_e_machine_init(MachineState *machine)
> {
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> const MemMapEntry *memmap = sifive_e_memmap;
>
> SiFiveEState *s = RISCV_E_MACHINE(machine);
> MemoryRegion *sys_mem = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> int i;
>
> + if (machine->ram_size != mc->default_ram_size) {
> + char *sz = size_to_str(mc->default_ram_size);
> + error_report("Invalid RAM size, should be %s", sz);
> + g_free(sz);
> + exit(EXIT_FAILURE);
> + }
> +
> /* Initialize SoC */
> object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> /* Data Tightly Integrated Memory */
> - memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
> - memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
> + memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
>
> /* Mask ROM reset vector */
> uint32_t reset_vec[4];
> @@ -142,6 +148,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> mc->init = sifive_e_machine_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = SIFIVE_E_CPU;
> + mc->default_ram_id = "riscv.sifive.e.ram";
> + mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
>
> object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
> sifive_e_machine_set_revb);
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Bin Meng
` (3 preceding siblings ...)
2021-10-20 1:41 ` [PATCH v2 4/6] hw/riscv: sifive_e: " Bin Meng
@ 2021-10-20 1:41 ` Bin Meng
2021-10-20 23:12 ` Alistair Francis
2021-10-20 1:41 ` [PATCH v2 6/6] hw/riscv: spike: " Bin Meng
2021-10-21 21:58 ` [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Alistair Francis
6 siblings, 1 reply; 19+ messages in thread
From: Bin Meng @ 2021-10-20 1:41 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Igor Mammedov, Philippe Mathieu-Daudé
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
(no changes since v1)
hw/riscv/sifive_u.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index fc5790b8ce..0217006c27 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -528,7 +528,6 @@ static void sifive_u_machine_init(MachineState *machine)
const MemMapEntry *memmap = sifive_u_memmap;
SiFiveUState *s = RISCV_U_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
@@ -549,10 +548,8 @@ static void sifive_u_machine_init(MachineState *machine)
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* register RAM */
- memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
- machine->ram_size, &error_fatal);
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
- main_mem);
+ machine->ram);
/* register QSPI0 Flash */
memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
@@ -748,6 +745,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
mc->default_cpu_type = SIFIVE_U_CPU;
mc->default_cpus = mc->min_cpus;
+ mc->default_ram_id = "riscv.sifive.u.ram";
object_class_property_add_bool(oc, "start-in-flash",
sifive_u_machine_get_start_in_flash,
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 5/6] hw/riscv: sifive_u: " Bin Meng
@ 2021-10-20 23:12 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2021-10-20 23:12 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Philippe Mathieu-Daudé,
Alistair Francis, qemu-devel@nongnu.org Developers,
Igor Mammedov
On Wed, Oct 20, 2021 at 11:48 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> (no changes since v1)
>
> hw/riscv/sifive_u.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index fc5790b8ce..0217006c27 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -528,7 +528,6 @@ static void sifive_u_machine_init(MachineState *machine)
> const MemMapEntry *memmap = sifive_u_memmap;
> SiFiveUState *s = RISCV_U_MACHINE(machine);
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> MemoryRegion *flash0 = g_new(MemoryRegion, 1);
> target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
> target_ulong firmware_end_addr, kernel_start_addr;
> @@ -549,10 +548,8 @@ static void sifive_u_machine_init(MachineState *machine)
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> /* register RAM */
> - memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
> - machine->ram_size, &error_fatal);
> memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
> - main_mem);
> + machine->ram);
>
> /* register QSPI0 Flash */
> memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
> @@ -748,6 +745,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
> mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
> mc->default_cpu_type = SIFIVE_U_CPU;
> mc->default_cpus = mc->min_cpus;
> + mc->default_ram_id = "riscv.sifive.u.ram";
>
> object_class_property_add_bool(oc, "start-in-flash",
> sifive_u_machine_get_start_in_flash,
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Bin Meng
` (4 preceding siblings ...)
2021-10-20 1:41 ` [PATCH v2 5/6] hw/riscv: sifive_u: " Bin Meng
@ 2021-10-20 1:41 ` Bin Meng
2021-10-20 23:13 ` Alistair Francis
2021-10-21 21:58 ` [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Alistair Francis
6 siblings, 1 reply; 19+ messages in thread
From: Bin Meng @ 2021-10-20 1:41 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Igor Mammedov, Philippe Mathieu-Daudé
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
(no changes since v1)
hw/riscv/spike.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 79ae355ae2..288d69cd9f 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -180,7 +180,6 @@ static void spike_board_init(MachineState *machine)
const MemMapEntry *memmap = spike_memmap;
SpikeState *s = SPIKE_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
target_ulong firmware_end_addr, kernel_start_addr;
uint32_t fdt_load_addr;
@@ -239,10 +238,8 @@ static void spike_board_init(MachineState *machine)
}
/* register system main memory (actual RAM) */
- memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
- machine->ram_size, &error_fatal);
memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
- main_mem);
+ machine->ram);
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
@@ -326,6 +323,7 @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
mc->numa_mem_supported = true;
+ mc->default_ram_id = "riscv.spike.ram";
}
static const TypeInfo spike_machine_typeinfo = {
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
2021-10-20 1:41 ` [PATCH v2 6/6] hw/riscv: spike: " Bin Meng
@ 2021-10-20 23:13 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2021-10-20 23:13 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Philippe Mathieu-Daudé,
Alistair Francis, qemu-devel@nongnu.org Developers,
Igor Mammedov
On Wed, Oct 20, 2021 at 11:43 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> (no changes since v1)
>
> hw/riscv/spike.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 79ae355ae2..288d69cd9f 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -180,7 +180,6 @@ static void spike_board_init(MachineState *machine)
> const MemMapEntry *memmap = spike_memmap;
> SpikeState *s = SPIKE_MACHINE(machine);
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> target_ulong firmware_end_addr, kernel_start_addr;
> uint32_t fdt_load_addr;
> @@ -239,10 +238,8 @@ static void spike_board_init(MachineState *machine)
> }
>
> /* register system main memory (actual RAM) */
> - memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
> - machine->ram_size, &error_fatal);
> memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
> - main_mem);
> + machine->ram);
>
> /* create device tree */
> create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
> @@ -326,6 +323,7 @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
> mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
> mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
> mc->numa_mem_supported = true;
> + mc->default_ram_id = "riscv.spike.ram";
> }
>
> static const TypeInfo spike_machine_typeinfo = {
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines
2021-10-20 1:41 [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Bin Meng
` (5 preceding siblings ...)
2021-10-20 1:41 ` [PATCH v2 6/6] hw/riscv: spike: " Bin Meng
@ 2021-10-21 21:58 ` Alistair Francis
6 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2021-10-21 21:58 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Philippe Mathieu-Daudé,
Alistair Francis, qemu-devel@nongnu.org Developers,
Igor Mammedov
On Wed, Oct 20, 2021 at 11:41 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> As of today, all RISC-V machines (except virt) are still using memory_region_init_ram()
> to initilize the sysytem RAM, which can't possibly handle vhost-user, and can't
> work as expected with '-numa node,memdev' options.
>
> Change to use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to opt in to
> memdev scheme.
>
> Changes in v2:
> - split RAM into low and high regions using aliases to machine->ram
> - rename mc->default_ram_id to "microchip.icicle.kit.ram"
> - opentitan: add RAM size check
> - opentitan: assign mc->default_ram_size
> - sifive_e: add RAM size check
> - sifive_e: assign mc->default_ram_size
>
> Bin Meng (6):
> hw/riscv: microchip_pfsoc: Use MachineState::ram and
> MachineClass::default_ram_id
> hw/riscv: opentitan: Use MachineState::ram and
> MachineClass::default_ram_id
> hw/riscv: shakti_c: Use MachineState::ram and
> MachineClass::default_ram_id
> hw/riscv: sifive_e: Use MachineState::ram and
> MachineClass::default_ram_id
> hw/riscv: sifive_u: Use MachineState::ram and
> MachineClass::default_ram_id
> hw/riscv: spike: Use MachineState::ram and
> MachineClass::default_ram_id
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> hw/riscv/microchip_pfsoc.c | 36 ++++++++++++++++++++----------------
> hw/riscv/opentitan.c | 16 ++++++++++++----
> hw/riscv/shakti_c.c | 6 ++----
> hw/riscv/sifive_e.c | 16 ++++++++++++----
> hw/riscv/sifive_u.c | 6 ++----
> hw/riscv/spike.c | 6 ++----
> 6 files changed, 50 insertions(+), 36 deletions(-)
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread