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From: Yakir Yang <ykk@rock-chips.com>
To: Heiko Stuebner <heiko@sntech.de>,
	Thierry Reding <treding@nvidia.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Fabio Estevam <fabio.estevam@freescale.com>,
	Inki Dae <inki.dae@samsung.com>,
	joe@perches.com, Russell King <rmk+kernel@arm.linux.org.uk>
Cc: djkurtz@google.com, dianders@google.com, seanpaul@google.com,
	Takashi Iwai <tiwai@suse.de>,
	ajaynumb@gmail.com, Andrzej Hajda <a.hajda@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	David Airlie <airlied@linux.ie>,
	Gustavo Padovan <gustavo.padovan@collabora.co.uk>,
	Vincent Palatin <vpalatin@chromium.org>,
	Mark Yao <mark.yao@rock-chips.com>,
	Andy Yan <andy.yan@rock-chips.com>,
	Kumar Gala <galak@codeaurora.org>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	Yakir Yang <ykk@rock-chips.com>
Subject: [PATCH v3 10/14] drm: bridge: analogix_dp: add some rk3288 special registers setting
Date: Wed, 19 Aug 2015 09:51:44 -0500	[thread overview]
Message-ID: <1439995904-18608-1-git-send-email-ykk@rock-chips.com> (raw)
In-Reply-To: <1439995728-18046-1-git-send-email-ykk@rock-chips.com>

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error

 drivers/gpu/drm/bridge/analogix_dp_reg.c | 76 ++++++++++++++++++++------------
 drivers/gpu/drm/bridge/analogix_dp_reg.h | 12 +++++
 2 files changed, 60 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix_dp_reg.c
index cc5cdbf..a0fc1fb 100644
--- a/drivers/gpu/drm/bridge/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix_dp_reg.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
+#include <drm/bridge/analogix_dp.h>
+
 #include "analogix_dp_core.h"
 #include "analogix_dp_reg.h"
 
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+	}
+
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable)
 {
 	u32 reg;
+	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		phy_pd_addr = ANALOGIX_DP_PD;
 
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(0x00, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+		      AUX_HW_RETRY_COUNT_SEL(3) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	else
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+		      AUX_HW_RETRY_COUNT_SEL(0) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix_dp_reg.h
index bed226f..e38af21 100644
--- a/drivers/gpu/drm/bridge/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix_dp_reg.h
@@ -22,6 +22,14 @@
 #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
 #define ANALOGIX_DP_VIDEO_CTL_10			0x44
 
+#define ANALOGIX_DP_PLL_REG_1			0xfc
+#define ANALOGIX_DP_PLL_REG_2			0x9e4
+#define ANALOGIX_DP_PLL_REG_3			0x9e8
+#define ANALOGIX_DP_PLL_REG_4			0x9ec
+#define ANALOGIX_DP_PLL_REG_5			0xa00
+
+#define ANALOGIX_DP_PD                          0x12c
+
 #define ANALOGIX_DP_LANE_MAP			0x35C
 
 #define ANALOGIX_DP_ANALOG_CTL_1			0x370
@@ -154,6 +162,10 @@
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-- 
1.9.1



WARNING: multiple messages have this Message-ID (diff)
From: ykk@rock-chips.com (Yakir Yang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 10/14] drm: bridge: analogix_dp: add some rk3288 special registers setting
Date: Wed, 19 Aug 2015 09:51:44 -0500	[thread overview]
Message-ID: <1439995904-18608-1-git-send-email-ykk@rock-chips.com> (raw)
In-Reply-To: <1439995728-18046-1-git-send-email-ykk@rock-chips.com>

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error

 drivers/gpu/drm/bridge/analogix_dp_reg.c | 76 ++++++++++++++++++++------------
 drivers/gpu/drm/bridge/analogix_dp_reg.h | 12 +++++
 2 files changed, 60 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix_dp_reg.c
index cc5cdbf..a0fc1fb 100644
--- a/drivers/gpu/drm/bridge/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix_dp_reg.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
+#include <drm/bridge/analogix_dp.h>
+
 #include "analogix_dp_core.h"
 #include "analogix_dp_reg.h"
 
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+	}
+
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable)
 {
 	u32 reg;
+	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		phy_pd_addr = ANALOGIX_DP_PD;
 
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(0x00, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+		      AUX_HW_RETRY_COUNT_SEL(3) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	else
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+		      AUX_HW_RETRY_COUNT_SEL(0) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix_dp_reg.h
index bed226f..e38af21 100644
--- a/drivers/gpu/drm/bridge/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix_dp_reg.h
@@ -22,6 +22,14 @@
 #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
 #define ANALOGIX_DP_VIDEO_CTL_10			0x44
 
+#define ANALOGIX_DP_PLL_REG_1			0xfc
+#define ANALOGIX_DP_PLL_REG_2			0x9e4
+#define ANALOGIX_DP_PLL_REG_3			0x9e8
+#define ANALOGIX_DP_PLL_REG_4			0x9ec
+#define ANALOGIX_DP_PLL_REG_5			0xa00
+
+#define ANALOGIX_DP_PD                          0x12c
+
 #define ANALOGIX_DP_LANE_MAP			0x35C
 
 #define ANALOGIX_DP_ANALOG_CTL_1			0x370
@@ -154,6 +162,10 @@
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-- 
1.9.1

  parent reply	other threads:[~2015-08-19 14:52 UTC|newest]

Thread overview: 187+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-19 14:48 [PATCH v3 0/14] Add Analogix Core Display Port Driver Yakir Yang
2015-08-19 14:48 ` Yakir Yang
2015-08-19 14:49 ` [PATCH v3 01/14] drm: exynos/dp: fix code style Yakir Yang
2015-08-19 14:49   ` Yakir Yang
2015-08-19 14:49 ` [PATCH v3 02/14] drm: exynos/dp: convert to drm bridge mode Yakir Yang
2015-08-19 14:49   ` Yakir Yang
2015-08-19 14:50 ` [PATCH v3 03/14] drm: bridge: analogix_dp: split exynos dp driver to bridge dir Yakir Yang
2015-08-19 14:50   ` Yakir Yang
2015-08-19 14:50 ` [PATCH v3 04/14] drm: bridge/analogix_dp: dynamic parse sync_pol & interlace & colorimetry Yakir Yang
2015-08-19 14:50   ` Yakir Yang
2015-08-19 14:50 ` [PATCH v3 05/14] drm: bridge/analogix_dp: fix link_rate & lane_count bug Yakir Yang
2015-08-19 14:50   ` Yakir Yang
2015-08-20  7:22   ` Jingoo Han
2015-08-20  7:22     ` Jingoo Han
2015-08-20  7:22     ` Jingoo Han
2015-08-20  8:04     ` Yakir Yang
2015-08-20  8:04       ` Yakir Yang
2015-08-20  8:04       ` Yakir Yang
2015-08-19 14:50 ` [PATCH v3 06/14] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-08-19 14:50   ` Yakir Yang
2015-08-23 23:23   ` Rob Herring
2015-08-23 23:23     ` Rob Herring
2015-08-23 23:23     ` Rob Herring
2015-08-24  0:43     ` Krzysztof Kozlowski
2015-08-24  0:43       ` Krzysztof Kozlowski
2015-08-24  0:43       ` Krzysztof Kozlowski
2015-08-24  2:42       ` Yakir Yang
2015-08-24  2:42         ` Yakir Yang
2015-08-24  4:20         ` Krzysztof Kozlowski
2015-08-24  4:20           ` Krzysztof Kozlowski
2015-08-24  4:20           ` Krzysztof Kozlowski
2015-08-24 12:48           ` Yakir Yang
2015-08-24 12:48             ` Yakir Yang
2015-08-24 12:48             ` Yakir Yang
2015-08-24 13:03             ` Heiko Stuebner
2015-08-24 13:03               ` Heiko Stuebner
2015-08-24 13:03               ` Heiko Stuebner
2015-08-25  1:37               ` Yakir Yang
2015-08-25  1:37                 ` Yakir Yang
2015-08-25  1:37                 ` Yakir Yang
2015-08-24 23:49             ` Krzysztof Kozlowski
2015-08-24 23:49               ` Krzysztof Kozlowski
2015-08-24 23:49               ` Krzysztof Kozlowski
     [not found]               ` <55DBAD90.3040901-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-08-25  1:32                 ` Yakir Yang
2015-08-25  1:33               ` Yakir Yang
2015-08-25  1:33                 ` Yakir Yang
2015-08-25  1:33                 ` Yakir Yang
2015-08-25  1:35                 ` Krzysztof Kozlowski
2015-08-25  1:35                   ` Krzysztof Kozlowski
2015-08-25  1:35                   ` Krzysztof Kozlowski
2015-08-24  7:40       ` Jingoo Han
2015-08-24  7:40         ` Jingoo Han
2015-08-24  7:40         ` Jingoo Han
2015-08-24 12:55         ` Yakir Yang
2015-08-24 12:55           ` Yakir Yang
2015-08-24 12:55           ` Yakir Yang
2015-08-24  2:19     ` Yakir Yang
2015-08-24  2:19       ` Yakir Yang
2015-08-24 12:57     ` Russell King - ARM Linux
2015-08-24 12:57       ` Russell King - ARM Linux
2015-08-24 12:57       ` Russell King - ARM Linux
2015-08-24 14:48       ` Rob Herring
2015-08-24 14:48         ` Rob Herring
2015-08-24 14:48         ` Rob Herring
2015-08-24 16:16         ` Heiko Stuebner
2015-08-24 16:16           ` Heiko Stuebner
2015-08-24 16:16           ` Heiko Stuebner
2015-08-25  1:21         ` Yakir Yang
2015-08-25  1:21           ` Yakir Yang
2015-08-25  1:21           ` Yakir Yang
2015-08-25  9:12         ` Thierry Reding
2015-08-25  9:12           ` Thierry Reding
2015-08-25  9:12           ` Thierry Reding
2015-08-25  9:29           ` Russell King - ARM Linux
2015-08-25  9:29             ` Russell King - ARM Linux
2015-08-25  9:29             ` Russell King - ARM Linux
2015-08-25 10:40             ` Thierry Reding
2015-08-25 10:40               ` Thierry Reding
2015-08-25 10:40               ` Thierry Reding
2015-08-25 10:52               ` Russell King - ARM Linux
2015-08-25 10:52                 ` Russell King - ARM Linux
2015-08-25 10:52                 ` Russell King - ARM Linux
2015-08-25  9:41           ` Yakir Yang
2015-08-25  9:41             ` Yakir Yang
2015-08-25 10:06             ` Thierry Reding
2015-08-25 10:06               ` Thierry Reding
2015-08-25 10:06               ` Thierry Reding
2015-08-25 14:02               ` Yakir Yang
2015-08-25 14:02                 ` Yakir Yang
2015-08-25  9:15     ` Thierry Reding
2015-08-25  9:15       ` Thierry Reding
2015-08-25  9:15       ` Thierry Reding
2015-08-25  9:37       ` Yakir Yang
2015-08-25  9:37         ` Yakir Yang
2015-08-25 13:27       ` Rob Herring
2015-08-25 13:27         ` Rob Herring
2015-08-25 13:27         ` Rob Herring
2015-08-25 13:48         ` Yakir Yang
2015-08-25 14:16           ` Thierry Reding
2015-08-25 14:16             ` Thierry Reding
2015-08-25 14:16             ` Thierry Reding
2015-08-25 14:23             ` Yakir Yang
2015-08-25 14:23               ` Yakir Yang
2015-08-25  9:58   ` Thierry Reding
2015-08-25  9:58     ` Thierry Reding
2015-08-25  9:58     ` Thierry Reding
2015-08-25 14:03     ` Yakir Yang
2015-08-25 14:03       ` Yakir Yang
2015-08-25 14:21       ` Thierry Reding
2015-08-25 14:21         ` Thierry Reding
2015-08-25 14:21         ` Thierry Reding
2015-08-25 15:57         ` Russell King - ARM Linux
2015-08-25 15:57           ` Russell King - ARM Linux
2015-08-25 15:57           ` Russell King - ARM Linux
2015-08-19 14:50 ` [PATCH v3 07/14] drm: rockchip/dp: add rockchip platform dp driver Yakir Yang
2015-08-19 14:50   ` Yakir Yang
2015-08-19 14:50   ` Yakir Yang
2015-08-19 14:51 ` [PATCH v3 08/14] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-08-19 14:51   ` Yakir Yang
2015-08-20  4:40   ` Kishon Vijay Abraham I
2015-08-20  4:40     ` Kishon Vijay Abraham I
2015-08-20  4:40     ` Kishon Vijay Abraham I
2015-08-20  6:56     ` Yakir Yang
2015-08-20  7:01       ` Yakir Yang
2015-08-19 14:51 ` [PATCH v3 09/14] drm: bridge/analogix_dp: add platform device type support Yakir Yang
2015-08-19 14:51   ` Yakir Yang
2015-08-19 14:51   ` Yakir Yang
2015-08-19 14:51 ` Yakir Yang [this message]
2015-08-19 14:51   ` [PATCH v3 10/14] drm: bridge: analogix_dp: add some rk3288 special registers setting Yakir Yang
2015-08-19 14:51 ` [PATCH v3 11/14] drm: bridge: analogix_dp: try force hpd after plug in lookup failed Yakir Yang
2015-08-19 14:51   ` Yakir Yang
2015-08-19 14:52 ` [PATCH v3 12/14] drm: bridge/analogix_dp: expand the delay time for hpd detect Yakir Yang
2015-08-19 14:52   ` Yakir Yang
2015-08-19 14:52   ` Yakir Yang
2015-08-20  6:11   ` Jingoo Han
2015-08-20  6:11     ` Jingoo Han
2015-08-20  6:11     ` Jingoo Han
2015-08-20  8:02     ` Yakir Yang
2015-08-20  8:02       ` Yakir Yang
2015-08-20  8:02       ` Yakir Yang
2015-08-19 14:52 ` [PATCH v3 13/14] drm: bridge/analogix_dp: move hpd detect to connector detect function Yakir Yang
2015-08-19 14:52   ` Yakir Yang
2015-08-20  7:49   ` Jingoo Han
2015-08-20  7:49     ` Jingoo Han
2015-08-20  7:49     ` Jingoo Han
2015-08-20  8:18     ` Yakir Yang
2015-08-20  8:18       ` Yakir Yang
2015-08-20  8:18       ` Yakir Yang
2015-08-19 14:52 ` [PATCH v3 14/14] drm: bridge/analogix_dp: add edid modes parse in get_modes method Yakir Yang
2015-08-19 14:52   ` Yakir Yang
2015-08-19 23:54 ` [PATCH v3 0/14] Add Analogix Core Display Port Driver Dave Airlie
2015-08-19 23:54   ` Dave Airlie
2015-08-19 23:54   ` Dave Airlie
2015-08-20  1:02   ` Yakir Yang
2015-08-20  1:02     ` Yakir Yang
2015-08-20  1:02     ` Yakir Yang
2015-08-20  4:29 ` Archit Taneja
2015-08-20  4:29   ` Archit Taneja
2015-08-20  4:29   ` Archit Taneja
2015-08-20  5:54   ` Jingoo Han
2015-08-20  5:54     ` Jingoo Han
2015-08-20  5:54     ` Jingoo Han
2015-08-20  6:23     ` Yakir Yang
2015-08-20  6:23       ` Yakir Yang
2015-08-20  6:23       ` Yakir Yang
2015-08-20  6:55       ` Jingoo Han
2015-08-20  6:55         ` Jingoo Han
2015-08-20  6:55         ` Jingoo Han
2015-08-20  8:03         ` Yakir Yang
2015-08-20  8:03           ` Yakir Yang
2015-08-20  8:03           ` Yakir Yang
2015-08-21  8:20 ` Jingoo Han
2015-08-21  8:20   ` Jingoo Han
2015-08-21  8:20   ` Jingoo Han
2015-08-21 10:01   ` Yakir Yang
2015-08-21 11:24     ` Jingoo Han
2015-08-21 13:16       ` Thierry Reding
2015-08-21 13:16         ` Thierry Reding
2015-08-21 13:16         ` Thierry Reding
2015-08-22 10:13         ` Yakir Yang
2015-08-30 12:16         ` Romain Perier
2015-08-30 12:16           ` Romain Perier
2015-08-30 12:16           ` Romain Perier
2015-08-31  2:40           ` Yakir Yang
2015-08-31  2:40             ` Yakir Yang
2015-08-31  2:40             ` Yakir Yang
2015-08-22  9:42       ` Yakir Yang

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