All of lore.kernel.org
 help / color / mirror / Atom feed
From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com
Subject: [RFC 2/7] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
Date: Fri, 15 Nov 2019 20:55:44 +0530	[thread overview]
Message-ID: <20191115152549.23047-3-animesh.manna@intel.com> (raw)
In-Reply-To: <20191115152549.23047-1-animesh.manna@intel.com>

vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.

No functional change.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
 .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
 3 files changed, 35 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3123958e2081..cc8e0d1a73af 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4062,6 +4062,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
 	}
 }
 
+void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+		       const u8 *link_status)
+{
+	u8 v = 0;
+	u8 p = 0;
+	int lane;
+	u8 voltage_max;
+	u8 preemph_max;
+
+	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
+		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
+
+		if (this_v > v)
+			v = this_v;
+		if (this_p > p)
+			p = this_p;
+	}
+
+	voltage_max = intel_dp_voltage_max(intel_dp);
+	if (v >= voltage_max)
+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+	if (p >= preemph_max)
+		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+	for (lane = 0; lane < 4; lane++)
+		intel_dp->train_set[lane] = v | p;
+}
+
 void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..0d0cb692f701 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -91,6 +91,9 @@ void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 				       u8 dp_train_pat);
 void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+		       const u8 *link_status);
+void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
 u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..1e38584e7d56 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 		      link_status[3], link_status[4], link_status[5]);
 }
 
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
-		       const u8 link_status[DP_LINK_STATUS_SIZE])
-{
-	u8 v = 0;
-	u8 p = 0;
-	int lane;
-	u8 voltage_max;
-	u8 preemph_max;
-
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
-		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
-		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-
-		if (this_v > v)
-			v = this_v;
-		if (this_p > p)
-			p = this_p;
-	}
-
-	voltage_max = intel_dp_voltage_max(intel_dp);
-	if (v >= voltage_max)
-		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
-	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
-	if (p >= preemph_max)
-		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
-	for (lane = 0; lane < 4; lane++)
-		intel_dp->train_set[lane] = v | p;
-}
-
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
 			u8 dp_train_pat)
-- 
2.22.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com
Subject: [Intel-gfx] [RFC 2/7] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
Date: Fri, 15 Nov 2019 20:55:44 +0530	[thread overview]
Message-ID: <20191115152549.23047-3-animesh.manna@intel.com> (raw)
Message-ID: <20191115152544.OAot54eSPOfj5gmowC6oBTLDkGXEyjyiFpoCYfyohg0@z> (raw)
In-Reply-To: <20191115152549.23047-1-animesh.manna@intel.com>

vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.

No functional change.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
 .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
 3 files changed, 35 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3123958e2081..cc8e0d1a73af 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4062,6 +4062,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
 	}
 }
 
+void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+		       const u8 *link_status)
+{
+	u8 v = 0;
+	u8 p = 0;
+	int lane;
+	u8 voltage_max;
+	u8 preemph_max;
+
+	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
+		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
+
+		if (this_v > v)
+			v = this_v;
+		if (this_p > p)
+			p = this_p;
+	}
+
+	voltage_max = intel_dp_voltage_max(intel_dp);
+	if (v >= voltage_max)
+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+	if (p >= preemph_max)
+		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+	for (lane = 0; lane < 4; lane++)
+		intel_dp->train_set[lane] = v | p;
+}
+
 void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..0d0cb692f701 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -91,6 +91,9 @@ void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 				       u8 dp_train_pat);
 void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+		       const u8 *link_status);
+void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
 u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..1e38584e7d56 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 		      link_status[3], link_status[4], link_status[5]);
 }
 
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
-		       const u8 link_status[DP_LINK_STATUS_SIZE])
-{
-	u8 v = 0;
-	u8 p = 0;
-	int lane;
-	u8 voltage_max;
-	u8 preemph_max;
-
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
-		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
-		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-
-		if (this_v > v)
-			v = this_v;
-		if (this_p > p)
-			p = this_p;
-	}
-
-	voltage_max = intel_dp_voltage_max(intel_dp);
-	if (v >= voltage_max)
-		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
-	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
-	if (p >= preemph_max)
-		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
-	for (lane = 0; lane < 4; lane++)
-		intel_dp->train_set[lane] = v | p;
-}
-
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
 			u8 dp_train_pat)
-- 
2.22.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-11-15 15:35 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-15 15:25 [RFC 0/7] DP Phy compliace auto test Animesh Manna
2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna
2019-11-15 15:25 ` [RFC 1/7] drm/dp: get/set phy compliance pattern Animesh Manna
2019-11-15 15:25   ` [Intel-gfx] " Animesh Manna
2019-11-18  4:04   ` Manasi Navare
2019-11-18  4:04     ` [Intel-gfx] " Manasi Navare
2019-11-18 18:39     ` Animesh Manna
2019-11-18 18:39       ` [Intel-gfx] " Animesh Manna
2019-11-15 15:25 ` Animesh Manna [this message]
2019-11-15 15:25   ` [Intel-gfx] [RFC 2/7] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
2019-11-15 15:25 ` [RFC 3/7] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2019-11-15 15:25   ` [Intel-gfx] " Animesh Manna
2019-11-18  4:47   ` Manasi Navare
2019-11-18  4:47     ` [Intel-gfx] " Manasi Navare
2019-11-15 15:25 ` [RFC 4/7] drm/i915/dp: Notify testapp using uevent and debugfs entry Animesh Manna
2019-11-15 15:25   ` [Intel-gfx] " Animesh Manna
2019-11-18  4:58   ` Manasi Navare
2019-11-18  4:58     ` [Intel-gfx] " Manasi Navare
2019-11-18  5:06     ` Manasi Navare
2019-11-18  5:06       ` [Intel-gfx] " Manasi Navare
2019-11-18 18:45       ` Animesh Manna
2019-11-18 18:45         ` [Intel-gfx] " Animesh Manna
2019-11-15 15:25 ` [RFC 5/7] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2019-11-15 15:25   ` [Intel-gfx] " Animesh Manna
2019-11-18  5:00   ` Manasi Navare
2019-11-18  5:00     ` [Intel-gfx] " Manasi Navare
2019-11-15 15:25 ` [RFC 6/7] drm/i915/dp: Update the pattern as per request Animesh Manna
2019-11-15 15:25   ` [Intel-gfx] " Animesh Manna
2019-11-18  6:41   ` Manasi Navare
2019-11-18  6:41     ` [Intel-gfx] " Manasi Navare
2019-11-18 18:47     ` Animesh Manna
2019-11-18 18:47       ` [Intel-gfx] " Animesh Manna
2019-12-11 23:44       ` Manasi Navare
2019-11-15 15:25 ` [RFC 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
2019-11-15 15:25   ` [Intel-gfx] " Animesh Manna
2019-11-18  7:53   ` Manasi Navare
2019-11-18  7:53     ` [Intel-gfx] " Manasi Navare
2019-12-11 23:50     ` Manasi Navare
2019-12-13 17:24       ` Animesh Manna
2020-01-14 21:38         ` Manasi Navare
2020-01-20 13:53           ` Manna, Animesh
2020-01-24  0:56             ` Manasi Navare
2019-11-15 19:27 ` ✗ Fi.CI.BUILD: failure for DP Phy compliace auto test Patchwork
2019-11-15 19:27   ` [Intel-gfx] " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191115152549.23047-3-animesh.manna@intel.com \
    --to=animesh.manna@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jani.nikula@intel.com \
    --cc=nidhi1.gupta@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.