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From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
	wxy194768@alibaba-inc.com, chihmin.chao@sifive.com,
	wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com,
	alex.bennee@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 00/11] RISC-V risu porting
Date: Sun, 12 Jul 2020 00:16:44 +0800	[thread overview]
Message-ID: <20200711161655.2856-1-zhiwei_liu@c-sky.com> (raw)

In contrast to the RFC, add more instructions description. Now it supports
RV64IMACFD. Some cross verifications have been done, such as comparison
between QEMU and TinyEMU, and comparison between QEMU and C906 FPGA.

Now it has some productive.

Features:
* support RV64IMACFD.
* support multi-precision float point.
* support accurate special values generation.

Todo:
* support RVV and RVP.


LIU Zhiwei (11):
  riscv: Add RV64I instructions description
  riscv: Add RV64M instructions description
  riscv: Add RV64A instructions description
  riscv: Add RV64F instructions description
  riscv: Add RV64D instructions description
  riscv: Add RV64C instructions description
  riscv: Generate payload scripts
  riscv: Add standard test case
  riscv: Define riscv struct reginfo
  riscv: Implement payload load interfaces
  riscv: Add configure script

 configure              |   4 +-
 risu_reginfo_riscv64.c | 132 +++++++++
 risu_reginfo_riscv64.h |  28 ++
 risu_riscv64.c         |  47 +++
 risugen_riscv.pm       | 643 +++++++++++++++++++++++++++++++++++++++++
 rv64.risu              | 466 +++++++++++++++++++++++++++++
 rv64c.risu             |  97 +++++++
 test_riscv64.s         |  85 ++++++
 upstream/configure     | 204 +++++++++++++
 9 files changed, 1705 insertions(+), 1 deletion(-)
 create mode 100644 risu_reginfo_riscv64.c
 create mode 100644 risu_reginfo_riscv64.h
 create mode 100644 risu_riscv64.c
 create mode 100644 risugen_riscv.pm
 create mode 100644 rv64.risu
 create mode 100644 rv64c.risu
 create mode 100644 test_riscv64.s
 create mode 100644 upstream/configure

-- 
2.23.0



WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, Alistair.Francis@wdc.com,
	chihmin.chao@sifive.com, alex.bennee@linaro.org,
	peter.maydell@linaro.org, wenmeng_zhang@c-sky.com,
	wxy194768@alibaba-inc.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 00/11] RISC-V risu porting
Date: Sun, 12 Jul 2020 00:16:44 +0800	[thread overview]
Message-ID: <20200711161655.2856-1-zhiwei_liu@c-sky.com> (raw)

In contrast to the RFC, add more instructions description. Now it supports
RV64IMACFD. Some cross verifications have been done, such as comparison
between QEMU and TinyEMU, and comparison between QEMU and C906 FPGA.

Now it has some productive.

Features:
* support RV64IMACFD.
* support multi-precision float point.
* support accurate special values generation.

Todo:
* support RVV and RVP.


LIU Zhiwei (11):
  riscv: Add RV64I instructions description
  riscv: Add RV64M instructions description
  riscv: Add RV64A instructions description
  riscv: Add RV64F instructions description
  riscv: Add RV64D instructions description
  riscv: Add RV64C instructions description
  riscv: Generate payload scripts
  riscv: Add standard test case
  riscv: Define riscv struct reginfo
  riscv: Implement payload load interfaces
  riscv: Add configure script

 configure              |   4 +-
 risu_reginfo_riscv64.c | 132 +++++++++
 risu_reginfo_riscv64.h |  28 ++
 risu_riscv64.c         |  47 +++
 risugen_riscv.pm       | 643 +++++++++++++++++++++++++++++++++++++++++
 rv64.risu              | 466 +++++++++++++++++++++++++++++
 rv64c.risu             |  97 +++++++
 test_riscv64.s         |  85 ++++++
 upstream/configure     | 204 +++++++++++++
 9 files changed, 1705 insertions(+), 1 deletion(-)
 create mode 100644 risu_reginfo_riscv64.c
 create mode 100644 risu_reginfo_riscv64.h
 create mode 100644 risu_riscv64.c
 create mode 100644 risugen_riscv.pm
 create mode 100644 rv64.risu
 create mode 100644 rv64c.risu
 create mode 100644 test_riscv64.s
 create mode 100644 upstream/configure

-- 
2.23.0



             reply	other threads:[~2020-07-11 16:20 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-11 16:16 LIU Zhiwei [this message]
2020-07-11 16:16 ` [PATCH 00/11] RISC-V risu porting LIU Zhiwei
2020-07-11 16:16 ` [PATCH 01/11] riscv: Add RV64I instructions description LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 02/11] riscv: Add RV64M " LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 03/11] riscv: Add RV64A " LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 04/11] riscv: Add RV64F " LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 05/11] riscv: Add RV64D " LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 06/11] riscv: Add RV64C " LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 07/11] riscv: Generate payload scripts LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 08/11] riscv: Add standard test case LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 09/11] riscv: Define riscv struct reginfo LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 10/11] riscv: Implement payload load interfaces LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 11/11] riscv: Add configure script LIU Zhiwei
2020-07-11 16:16   ` LIU Zhiwei
2020-07-22  2:50 ` [PATCH 00/11] RISC-V risu porting LIU Zhiwei
2020-07-22  2:50   ` LIU Zhiwei

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