* [PATCH v10 00/14] Add CAAM driver model support
@ 2022-01-12 13:31 Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 01/14] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
` (14 more replies)
0 siblings, 15 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
This patchset adds the support for following:
1) CAAM Driver model for all i.MX, layerscape, PPC platforms.
2) Added crypto node in device tree files.
3) fix build issue for mx6sabre: Remove SPL DTB related configs and SPL_OF_CONTROL.
i.MX platforms:
i.MX6, i.MX7, i.MX7ULP, i.MX8MM/MN/MP/MQ, i.MX8QM/QXP
Layerscape platforms:
LS1021, LS1012, LS1028, LS1043, LS1046, LS1088, LS2088, LX2160, LX2162
Powerpc platforms:
P3041, P4080, P5040, P2041, T1024, T1042, T2080, T4240
changes since v9:
- added IS_ENABLED(CONFIG_FSL_CAAM) check before probing CAAM driver.
- FSL_CAAM enablement is moved to defconfigs for layerscape, powerpc.
changes since v8:
- rebase to latest master
- removed patch "crypto/fsl: Improve hwrng performance in kernel".
- moved FSL_CAAM config to board defconfig for Layerscape platforms.
- moved MISC config select to "config FSL_CAAM" as "select MISC if DM".
changes since v7:
- rebase to latest master
- corrected the order of include files as per coding style in jr.c.
https://www.denx.de/wiki/U-Boot/CodingStyle
- added brackets around #defines for -ve number in jr.h
- added comments for struct caam_regs in jr.h
changes since v6:
- rebase to latest master
- added caam_jr_ioctl() operation which calls run_descriptor_jr().
- removed CONFIG_ARCH_IMX8 config from JR driver.
- removed FSL_BLOB config
changes since v5:
- rebase to latest master
- updated BIT() macro for JRDID in drivers/crypto/fsl/jr.h
- removed auto select FSL_BLOB from CMD_BLOB config.
- removed patch for blob key encryption key(bkek), random number generation.
- updated patch description for improving hwrng performance in kernel.
- removed sec_init() from kontron/sl28.
- for LS1028A architecture, enable CAAM only for LS1028AQDS and LS1028ARDB.
changes since v4:
- rebase to latest master
- updated caam_jr_probe() with livetree APIs.
- imx8m: moved jr0 disable code to *-uboot.dtsi files.
changes since v3:
- rebase to latest master
- fixed build error when new file arch/powerpc/include/asm/u-boot-ppc.h is
included from assembly files.
- removed arch/arm/dts/fsl-ls1028a.dtsi as it is conflicting with the series
https://lore.kernel.org/u-boot/20211013161427.612033-1-michael@walle.cc/
Gaurav Jain (13):
crypto/fsl: Add support for CAAM Job ring driver model
i.MX8M: crypto: updated device tree for supporting DM in SPL
crypto/fsl: i.MX8M: Enable Job ring driver model.
i.MX6: Enable Job ring driver model.
i.MX7: Enable Job ring driver model.
i.MX7ULP: Enable Job ring driver model.
i.MX8: Add crypto node in device tree
crypto/fsl: i.MX8: Enable Job ring driver model.
Layerscape: Add crypto node in device tree
Layerscape: Enable Job ring driver model.
PPC: Add crypto node in device tree
PPC: Enable Job ring driver model.
update CAAM MAINTAINER
Ye Li (1):
mx6sabre: Remove unnecessary SPL configs
MAINTAINERS | 6 +
arch/arm/Kconfig | 9 +-
arch/arm/cpu/armv7/ls102xa/cpu.c | 18 +
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 11 +-
arch/arm/dts/fsl-imx8dx.dtsi | 61 ++-
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 +-
arch/arm/dts/fsl-imx8qm.dtsi | 61 ++-
arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 +-
arch/arm/dts/fsl-ls1012a.dtsi | 46 ++-
arch/arm/dts/fsl-ls1043a.dtsi | 45 ++-
arch/arm/dts/fsl-ls1046a.dtsi | 44 +++
arch/arm/dts/fsl-ls1088a.dtsi | 39 ++
arch/arm/dts/fsl-ls2080a.dtsi | 39 ++
arch/arm/dts/fsl-lx2160a.dtsi | 41 +-
arch/arm/dts/imx7ulp.dtsi | 24 ++
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 +-
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 +-
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 +-
arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4 +
arch/arm/dts/ls1021a.dtsi | 40 ++
arch/arm/include/asm/arch-imx8/imx-regs.h | 5 +-
arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 +
arch/arm/mach-imx/cmd_dek.c | 1 +
arch/arm/mach-imx/imx8/Kconfig | 7 +
arch/arm/mach-imx/imx8/cpu.c | 18 +-
arch/arm/mach-imx/imx8m/Kconfig | 13 +
arch/arm/mach-imx/imx8m/soc.c | 11 +-
arch/arm/mach-imx/mx6/Kconfig | 10 +
arch/arm/mach-imx/mx6/soc.c | 13 +-
arch/arm/mach-imx/mx7/Kconfig | 1 +
arch/arm/mach-imx/mx7/soc.c | 12 +-
arch/arm/mach-imx/mx7ulp/Kconfig | 2 +
arch/arm/mach-imx/mx7ulp/soc.c | 18 +
arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 +-
arch/powerpc/dts/p2041si-post.dtsi | 1 +
arch/powerpc/dts/p3041si-post.dtsi | 1 +
arch/powerpc/dts/p4080si-post.dtsi | 1 +
arch/powerpc/dts/p5040si-post.dtsi | 1 +
arch/powerpc/dts/qoriq-sec4.0-0.dtsi | 74 ++++
arch/powerpc/dts/qoriq-sec4.2-0.dtsi | 83 ++++
arch/powerpc/dts/qoriq-sec5.2-0.dtsi | 92 +++++
arch/powerpc/dts/t1023si-post.dtsi | 1 +
arch/powerpc/dts/t1042si-post.dtsi | 1 +
arch/powerpc/dts/t2080si-post.dtsi | 1 +
arch/powerpc/dts/t4240si-post.dtsi | 1 +
arch/powerpc/include/asm/u-boot-ppc.h | 17 +
arch/powerpc/include/asm/u-boot.h | 1 +
board/freescale/imx8mm_evk/spl.c | 10 +-
board/freescale/imx8mn_evk/spl.c | 9 +-
board/freescale/imx8mp_evk/spl.c | 14 +-
board/freescale/imx8mq_evk/spl.c | 8 +-
board/freescale/imx8qm_mek/spl.c | 6 +-
board/freescale/imx8qxp_mek/spl.c | 6 +-
board/freescale/ls1012afrdm/ls1012afrdm.c | 7 +-
board/freescale/ls1012aqds/ls1012aqds.c | 6 +-
board/freescale/ls1012ardb/ls1012ardb.c | 6 +-
board/freescale/ls1021aiot/ls1021aiot.c | 6 +-
board/freescale/ls1021aqds/ls1021aqds.c | 6 +-
board/freescale/ls1021atsn/ls1021atsn.c | 7 +-
board/freescale/ls1021atwr/ls1021atwr.c | 8 +-
board/freescale/ls1028a/ls1028a.c | 6 +-
board/freescale/ls1043ardb/ls1043ardb.c | 6 +-
board/freescale/ls1046afrwy/ls1046afrwy.c | 7 +-
board/freescale/ls1046aqds/ls1046aqds.c | 7 +-
board/freescale/ls1046ardb/ls1046ardb.c | 6 +-
board/freescale/ls1088a/ls1088a.c | 6 +-
board/freescale/ls2080aqds/ls2080aqds.c | 6 +-
board/freescale/ls2080ardb/ls2080ardb.c | 9 +-
board/freescale/lx2160a/lx2160a.c | 5 -
board/kontron/sl28/sl28.c | 3 -
configs/P2041RDB_NAND_defconfig | 1 +
configs/P2041RDB_SDCARD_defconfig | 1 +
configs/P2041RDB_SPIFLASH_defconfig | 1 +
configs/P2041RDB_defconfig | 1 +
configs/P3041DS_NAND_defconfig | 1 +
configs/P3041DS_SDCARD_defconfig | 1 +
configs/P3041DS_SPIFLASH_defconfig | 1 +
configs/P3041DS_defconfig | 1 +
configs/P4080DS_SDCARD_defconfig | 1 +
configs/P4080DS_SPIFLASH_defconfig | 1 +
configs/P4080DS_defconfig | 1 +
configs/P5040DS_NAND_defconfig | 1 +
configs/P5040DS_SDCARD_defconfig | 1 +
configs/P5040DS_SPIFLASH_defconfig | 1 +
configs/P5040DS_defconfig | 1 +
configs/T1024RDB_NAND_defconfig | 1 +
configs/T1024RDB_SDCARD_defconfig | 1 +
configs/T1024RDB_SPIFLASH_defconfig | 1 +
configs/T1024RDB_defconfig | 1 +
configs/T1042D4RDB_NAND_defconfig | 1 +
configs/T1042D4RDB_SDCARD_defconfig | 1 +
configs/T1042D4RDB_SPIFLASH_defconfig | 1 +
configs/T1042D4RDB_defconfig | 1 +
configs/T2080QDS_NAND_defconfig | 1 +
configs/T2080QDS_SDCARD_defconfig | 1 +
configs/T2080QDS_SPIFLASH_defconfig | 1 +
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 +
configs/T2080QDS_defconfig | 1 +
configs/T2080RDB_NAND_defconfig | 1 +
configs/T2080RDB_SDCARD_defconfig | 1 +
configs/T2080RDB_SPIFLASH_defconfig | 1 +
configs/T2080RDB_defconfig | 1 +
configs/T2080RDB_revD_NAND_defconfig | 1 +
configs/T2080RDB_revD_SDCARD_defconfig | 1 +
configs/T2080RDB_revD_SPIFLASH_defconfig | 1 +
configs/T2080RDB_revD_defconfig | 1 +
configs/T4240RDB_SDCARD_defconfig | 1 +
configs/T4240RDB_defconfig | 1 +
configs/ls1021aiot_qspi_defconfig | 1 +
configs/ls1021aiot_sdcard_defconfig | 1 +
configs/ls1021aqds_ddr4_nor_defconfig | 1 +
configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 +
configs/ls1021aqds_nand_defconfig | 1 +
configs/ls1021aqds_nor_defconfig | 1 +
configs/ls1021aqds_nor_lpuart_defconfig | 1 +
configs/ls1021aqds_qspi_defconfig | 1 +
configs/ls1021aqds_sdcard_ifc_defconfig | 1 +
configs/ls1021aqds_sdcard_qspi_defconfig | 1 +
configs/ls1021atsn_qspi_defconfig | 1 +
configs/ls1021atsn_sdcard_defconfig | 1 +
configs/ls1021atwr_nor_defconfig | 1 +
configs/ls1021atwr_nor_lpuart_defconfig | 1 +
configs/ls1021atwr_qspi_defconfig | 1 +
...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
configs/ls1021atwr_sdcard_ifc_defconfig | 1 +
configs/ls1021atwr_sdcard_qspi_defconfig | 1 +
configs/ls1043aqds_defconfig | 1 +
configs/ls1043aqds_lpuart_defconfig | 1 +
configs/ls1043aqds_nand_defconfig | 1 +
configs/ls1043aqds_nor_ddr3_defconfig | 1 +
configs/ls1043aqds_qspi_defconfig | 1 +
configs/ls1043aqds_sdcard_ifc_defconfig | 1 +
configs/ls1043aqds_sdcard_qspi_defconfig | 1 +
configs/ls1043aqds_tfa_defconfig | 1 +
configs/ls1043ardb_defconfig | 1 +
configs/ls1043ardb_nand_defconfig | 1 +
configs/ls1043ardb_sdcard_defconfig | 1 +
configs/ls1043ardb_tfa_defconfig | 1 +
configs/ls1046afrwy_tfa_defconfig | 1 +
configs/ls1046aqds_defconfig | 1 +
configs/ls1046aqds_lpuart_defconfig | 1 +
configs/ls1046aqds_nand_defconfig | 1 +
configs/ls1046aqds_qspi_defconfig | 1 +
configs/ls1046aqds_sdcard_ifc_defconfig | 1 +
configs/ls1046aqds_sdcard_qspi_defconfig | 1 +
configs/ls1046aqds_tfa_defconfig | 1 +
configs/ls1046ardb_emmc_defconfig | 1 +
configs/ls1046ardb_qspi_defconfig | 1 +
configs/ls1046ardb_qspi_spl_defconfig | 1 +
configs/ls1046ardb_sdcard_defconfig | 1 +
configs/ls1046ardb_tfa_defconfig | 1 +
configs/mx6sabreauto_defconfig | 2 -
configs/mx6sabresd_defconfig | 4 -
drivers/crypto/fsl/Kconfig | 3 +-
drivers/crypto/fsl/jr.c | 374 ++++++++++++------
drivers/crypto/fsl/jr.h | 31 +-
include/fsl_sec.h | 12 +-
scripts/config_whitelist.txt | 1 +
158 files changed, 1432 insertions(+), 255 deletions(-)
create mode 100644 arch/powerpc/dts/qoriq-sec4.0-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec4.2-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec5.2-0.dtsi
create mode 100644 arch/powerpc/include/asm/u-boot-ppc.h
--
2.17.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v10 01/14] crypto/fsl: Add support for CAAM Job ring driver model
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 20:03 ` Simon Glass
2022-01-12 13:31 ` [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
` (13 subsequent siblings)
14 siblings, 1 reply; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
added device tree support for job ring driver.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
drivers/crypto/fsl/Kconfig | 1 +
drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++-------------
drivers/crypto/fsl/jr.h | 31 +++-
3 files changed, 241 insertions(+), 114 deletions(-)
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 94ff540111..231eb00b5f 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -2,6 +2,7 @@ config FSL_CAAM
bool "Freescale Crypto Driver Support"
select SHA_HW_ACCEL
# hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL
+ select MISC if DM
imply SPL_CRYPTO if (ARM && SPL)
imply CMD_HASH
help
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 22b649219e..8103987425 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
* Based on CAAM driver in drivers/crypto/caam in Linux
*/
@@ -11,7 +11,6 @@
#include <linux/kernel.h>
#include <log.h>
#include <malloc.h>
-#include "fsl_sec.h"
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
@@ -21,7 +20,10 @@
#include <asm/cache.h>
#include <asm/fsl_pamu.h>
#endif
+#include <dm.h>
#include <dm/lists.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
#include <linux/delay.h>
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
@@ -35,20 +37,29 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
#endif
};
+#if CONFIG_IS_ENABLED(DM)
+struct udevice *caam_dev;
+#else
#define SEC_ADDR(idx) \
(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
#define SEC_JR0_ADDR(idx) \
(ulong)(SEC_ADDR(idx) + \
(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+struct caam_regs caam_st;
+#endif
-struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+static inline u32 jr_start_reg(u8 jrid)
+{
+ return (1 << jrid);
+}
-static inline void start_jr0(uint8_t sec_idx)
+static inline void start_jr(struct caam_regs *caam)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+ ccsr_sec_t *sec = caam->sec;
u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
u32 scfgr = sec_in32(&sec->scfgr);
+ u32 jrstart = jr_start_reg(caam->jrid);
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
@@ -56,23 +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
*/
if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
(scfgr & SEC_SCFGR_VIRT_EN))
- sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+ sec_out32(&sec->jrstartr, jrstart);
} else {
/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
- sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+ sec_out32(&sec->jrstartr, jrstart);
}
}
-static inline void jr_reset_liodn(uint8_t sec_idx)
+static inline void jr_disable_irq(struct jr_regs *regs)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- sec_out32(&sec->jrliodnr[0].ls, 0);
-}
-
-static inline void jr_disable_irq(uint8_t sec_idx)
-{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
uint32_t jrcfg = sec_in32(®s->jrcfg1);
jrcfg = jrcfg | JR_INTMASK;
@@ -80,10 +84,10 @@ static inline void jr_disable_irq(uint8_t sec_idx)
sec_out32(®s->jrcfg1, jrcfg);
}
-static void jr_initregs(uint8_t sec_idx)
+static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
@@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
sec_out32(®s->irs, JR_SIZE);
if (!jr->irq)
- jr_disable_irq(sec_idx);
+ jr_disable_irq(regs);
}
-static int jr_init(uint8_t sec_idx)
+static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
{
- struct jobring *jr = &jr0[sec_idx];
+ struct jobring *jr = &caam->jr[sec_idx];
memset(jr, 0, sizeof(struct jobring));
- jr->jq_id = DEFAULT_JR_ID;
+ jr->jq_id = caam->jrid;
jr->irq = DEFAULT_IRQ;
#ifdef CONFIG_FSL_CORENET
@@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
memset(jr->output_ring, 0, jr->op_size);
- start_jr0(sec_idx);
-
- jr_initregs(sec_idx);
-
- return 0;
-}
-
-static int jr_sw_cleanup(uint8_t sec_idx)
-{
- struct jobring *jr = &jr0[sec_idx];
-
- jr->head = 0;
- jr->tail = 0;
- jr->read_idx = 0;
- jr->write_idx = 0;
- memset(jr->info, 0, sizeof(jr->info));
- memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
- memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
-
- return 0;
-}
-
-static int jr_hw_reset(uint8_t sec_idx)
-{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- uint32_t timeout = 100000;
- uint32_t jrint, jrcr;
-
- sec_out32(®s->jrcr, JRCR_RESET);
- do {
- jrint = sec_in32(®s->jrint);
- } while (((jrint & JRINT_ERR_HALT_MASK) ==
- JRINT_ERR_HALT_INPROGRESS) && --timeout);
-
- jrint = sec_in32(®s->jrint);
- if (((jrint & JRINT_ERR_HALT_MASK) !=
- JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
- return -1;
-
- timeout = 100000;
- sec_out32(®s->jrcr, JRCR_RESET);
- do {
- jrcr = sec_in32(®s->jrcr);
- } while ((jrcr & JRCR_RESET) && --timeout);
-
- if (timeout == 0)
- return -1;
+ start_jr(caam);
+ jr_initregs(sec_idx, caam);
return 0;
}
@@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
void (*callback)(uint32_t status, void *arg),
- void *arg, uint8_t sec_idx)
+ void *arg, uint8_t sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
int head = jr->head;
uint32_t desc_word;
int length = desc_len(desc_addr);
@@ -263,10 +222,10 @@ static int jr_enqueue(uint32_t *desc_addr,
return 0;
}
-static int jr_dequeue(int sec_idx)
+static int jr_dequeue(int sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
int head = jr->head;
int tail = jr->tail;
int idx, i, found;
@@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void *arg)
{
struct result *x = arg;
x->status = status;
-#ifndef CONFIG_SPL_BUILD
caam_jr_strstatus(status);
-#endif
x->done = 1;
}
static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
{
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
unsigned long long timeval = 0;
unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
struct result op;
@@ -364,7 +327,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
memset(&op, 0, sizeof(op));
- ret = jr_enqueue(desc, desc_done, &op, sec_idx);
+ ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
if (ret) {
debug("Error in SEC enq\n");
ret = JQ_ENQ_ERR;
@@ -375,7 +338,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
udelay(1);
timeval += 1;
- ret = jr_dequeue(sec_idx);
+ ret = jr_dequeue(sec_idx, caam);
if (ret) {
debug("Error in SEC deq\n");
ret = JQ_DEQ_ERR;
@@ -402,13 +365,62 @@ int run_descriptor_jr(uint32_t *desc)
return run_descriptor_jr_idx(desc, 0);
}
+static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam)
+{
+ struct jobring *jr = &caam->jr[sec_idx];
+
+ jr->head = 0;
+ jr->tail = 0;
+ jr->read_idx = 0;
+ jr->write_idx = 0;
+ memset(jr->info, 0, sizeof(jr->info));
+ memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
+ memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
+
+ return 0;
+}
+
+static int jr_hw_reset(struct jr_regs *regs)
+{
+ uint32_t timeout = 100000;
+ uint32_t jrint, jrcr;
+
+ sec_out32(®s->jrcr, JRCR_RESET);
+ do {
+ jrint = sec_in32(®s->jrint);
+ } while (((jrint & JRINT_ERR_HALT_MASK) ==
+ JRINT_ERR_HALT_INPROGRESS) && --timeout);
+
+ jrint = sec_in32(®s->jrint);
+ if (((jrint & JRINT_ERR_HALT_MASK) !=
+ JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
+ return -1;
+
+ timeout = 100000;
+ sec_out32(®s->jrcr, JRCR_RESET);
+ do {
+ jrcr = sec_in32(®s->jrcr);
+ } while ((jrcr & JRCR_RESET) && --timeout);
+
+ if (timeout == 0)
+ return -1;
+
+ return 0;
+}
+
static inline int jr_reset_sec(uint8_t sec_idx)
{
- if (jr_hw_reset(sec_idx) < 0)
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
+ if (jr_hw_reset(caam->regs) < 0)
return -1;
/* Clean up the jobring structure maintained by software */
- jr_sw_cleanup(sec_idx);
+ jr_sw_cleanup(sec_idx, caam);
return 0;
}
@@ -418,9 +430,15 @@ int jr_reset(void)
return jr_reset_sec(0);
}
-static inline int sec_reset_idx(uint8_t sec_idx)
+int sec_reset(void)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
+ ccsr_sec_t *sec = caam->sec;
uint32_t mcfgr = sec_in32(&sec->mcfgr);
uint32_t timeout = 100000;
@@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t sec_idx)
return 0;
}
-int sec_reset(void)
-{
- return sec_reset_idx(0);
-}
-#ifndef CONFIG_SPL_BUILD
+
static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
{
u32 *desc;
@@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
return ret;
}
-static int instantiate_rng(u8 sec_idx, int gen_sk)
+static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int gen_sk)
{
u32 *desc;
u32 rdsta_val;
int ret = 0, sh_idx, size;
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
@@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
return ret;
}
-static u8 get_rng_vid(uint8_t sec_idx)
+static u8 get_rng_vid(ccsr_sec_t *sec)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
u8 vid;
if (caam_get_era() < 10) {
@@ -574,9 +586,8 @@ static u8 get_rng_vid(uint8_t sec_idx)
* By default, the TRNG runs for 200 clocks per sample;
* 1200 clocks per sample generates better entropy.
*/
-static void kick_trng(int ent_delay, uint8_t sec_idx)
+static void kick_trng(int ent_delay, ccsr_sec_t *sec)
{
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 val;
@@ -603,10 +614,9 @@ static void kick_trng(int ent_delay, uint8_t sec_idx)
sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
}
-static int rng_init(uint8_t sec_idx)
+static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
{
int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 inst_handles;
@@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
* the TRNG parameters.
*/
if (!inst_handles) {
- kick_trng(ent_delay, sec_idx);
+ kick_trng(ent_delay, sec);
ent_delay += 400;
}
/*
@@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
* interval, leading to a sucessful initialization of
* the RNG.
*/
- ret = instantiate_rng(sec_idx, gen_sk);
+ ret = instantiate_rng(sec_idx, sec, gen_sk);
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
if (ret) {
printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
@@ -646,13 +656,28 @@ static int rng_init(uint8_t sec_idx)
return ret;
}
-#endif
+
int sec_init_idx(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- uint32_t mcr = sec_in32(&sec->mcfgr);
int ret = 0;
-
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ if (!caam_dev) {
+ printf("caam_jr: caam not found\n");
+ return -1;
+ }
+ caam = dev_get_priv(caam_dev);
+#else
+ caam_st.sec = (void *)SEC_ADDR(sec_idx);
+ caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+ caam_st.jrid = 0;
+ caam = &caam_st;
+#endif
+ ccsr_sec_t *sec = caam->sec;
+ uint32_t mcr = sec_in32(&sec->mcfgr);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+ uint32_t jrdid_ms = 0;
+#endif
#ifdef CONFIG_FSL_CORENET
uint32_t liodnr;
uint32_t liodn_ns;
@@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+ jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID;
+ sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms);
+#endif
+ jr_reset();
#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SPL_BUILD
@@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
- liodnr = sec_in32(&sec->jrliodnr[0].ls) &
+ liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
~(JRNSLIODN_MASK | JRSLIODN_MASK);
liodnr = liodnr |
(liodn_ns << JRNSLIODN_SHIFT) |
(liodn_s << JRSLIODN_SHIFT);
- sec_out32(&sec->jrliodnr[0].ls, liodnr);
+ sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
#else
- liodnr = sec_in32(&sec->jrliodnr[0].ls);
+ liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
#endif
-
- ret = jr_init(sec_idx);
+ ret = jr_init(sec_idx, caam);
if (ret < 0) {
printf("SEC%u: initialization failed\n", sec_idx);
return -1;
@@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
pamu_enable();
#endif
-#ifndef CONFIG_SPL_BUILD
- if (get_rng_vid(sec_idx) >= 4) {
- if (rng_init(sec_idx) < 0) {
+
+ if (get_rng_vid(caam->sec) >= 4) {
+ if (rng_init(sec_idx, caam->sec) < 0) {
printf("SEC%u: RNG instantiation failed\n", sec_idx);
return -1;
}
@@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
printf("SEC%u: RNG instantiated\n", sec_idx);
}
-#endif
return ret;
}
@@ -743,3 +771,76 @@ int sec_init(void)
{
return sec_init_idx(0);
}
+
+#if CONFIG_IS_ENABLED(DM)
+static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
+{
+ if (request != CAAM_JR_RUN_DESC)
+ return -ENOSYS;
+
+ return run_descriptor_jr(buf);
+}
+
+static int caam_jr_probe(struct udevice *dev)
+{
+ struct caam_regs *caam = dev_get_priv(dev);
+ fdt_addr_t addr;
+ ofnode node;
+ unsigned int jr_node = 0;
+
+ caam_dev = dev;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("caam_jr: crypto not found\n");
+ return -EINVAL;
+ }
+ caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
+ caam->regs = (struct jr_regs *)caam->sec;
+
+ /* Check for enabled job ring node */
+ ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+ if (!ofnode_is_available(node))
+ continue;
+
+ jr_node = ofnode_read_u32_default(node, "reg", -1);
+ if (jr_node > 0) {
+ caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
+ while (!(jr_node & 0x0F))
+ jr_node = jr_node >> 4;
+
+ caam->jrid = jr_node - 1;
+ break;
+ }
+ }
+
+ if (sec_init())
+ printf("\nsec_init failed!\n");
+
+ return 0;
+}
+
+static int caam_jr_bind(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct misc_ops caam_jr_ops = {
+ .ioctl = caam_jr_ioctl,
+};
+
+static const struct udevice_id caam_jr_match[] = {
+ { .compatible = "fsl,sec-v4.0" },
+ { }
+};
+
+U_BOOT_DRIVER(caam_jr) = {
+ .name = "caam_jr",
+ .id = UCLASS_MISC,
+ .of_match = caam_jr_match,
+ .ops = &caam_jr_ops,
+ .bind = caam_jr_bind,
+ .probe = caam_jr_probe,
+ .priv_auto = sizeof(struct caam_regs),
+};
+#endif
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 1047aa772c..3eb7be79da 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*
*/
@@ -8,7 +9,9 @@
#define __JR_H
#include <linux/compiler.h>
+#include "fsl_sec.h"
#include "type.h"
+#include <misc.h>
#define JR_SIZE 4
/* Timeout currently defined as 10 sec */
@@ -35,12 +38,21 @@
#define JRSLIODN_SHIFT 0
#define JRSLIODN_MASK 0x00000fff
-#define JQ_DEQ_ERR -1
-#define JQ_DEQ_TO_ERR -2
-#define JQ_ENQ_ERR -3
+#define JRDID_MS_PRIM_DID BIT(0)
+#define JRDID_MS_PRIM_TZ BIT(4)
+#define JRDID_MS_TZ_OWN BIT(15)
+
+#define JQ_DEQ_ERR (-1)
+#define JQ_DEQ_TO_ERR (-2)
+#define JQ_ENQ_ERR (-3)
#define RNG4_MAX_HANDLES 2
+enum {
+ /* Run caam jobring descriptor(in buf) */
+ CAAM_JR_RUN_DESC,
+};
+
struct op_ring {
caam_dma_addr_t desc;
uint32_t status;
@@ -102,6 +114,19 @@ struct result {
uint32_t status;
};
+/*
+ * struct caam_regs - CAAM initialization register interface
+ *
+ * Interface to caam memory map, jobring register, jobring storage.
+ */
+struct caam_regs {
+ ccsr_sec_t *sec; /*caam initialization registers*/
+ struct jr_regs *regs; /*jobring configuration registers*/
+ u8 jrid; /*id to identify a jobring*/
+ /*Private sub-storage for a single JobR*/
+ struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+};
+
void caam_jr_strstatus(u32 status);
int run_descriptor_jr(uint32_t *desc);
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 01/14] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-31 21:45 ` ZHIZHIKIN Andrey
2022-01-12 13:31 ` [PATCH v10 03/14] crypto/fsl: i.MX8M: Enable Job ring driver model Gaurav Jain
` (12 subsequent siblings)
14 siblings, 1 reply; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
disabled use of JR0 in SPL and uboot, as JR0 is reserved
for secure boot.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 ++++++++++++++++++-
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++++++++++++++++++-
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 ++++++++++++++++++-
arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4 ++++
4 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 6b459831e7..e5682ca165 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include "imx8mm-u-boot.dtsi"
@@ -68,6 +68,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 1d3844437d..d8df863083 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
/ {
@@ -104,6 +104,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index ab849ebaac..f3f83ba303 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include "imx8mp-u-boot.dtsi"
@@ -67,6 +67,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&i2c1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
index 6f9c81462e..8f1f942215 100644
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -10,3 +10,7 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&sec_jr0 {
+ status = "disabled";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 03/14] crypto/fsl: i.MX8M: Enable Job ring driver model.
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 01/14] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 04/14] mx6sabre: Remove unnecessary SPL configs Gaurav Jain
` (11 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
i.MX8MM/MN/MP/MQ - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 +
arch/arm/mach-imx/imx8m/Kconfig | 13 +++++++++++++
arch/arm/mach-imx/imx8m/soc.c | 11 ++++++++++-
board/freescale/imx8mm_evk/spl.c | 10 +++++++++-
board/freescale/imx8mn_evk/spl.c | 9 +++++++--
board/freescale/imx8mp_evk/spl.c | 14 ++++++++++++--
board/freescale/imx8mq_evk/spl.c | 8 ++++++--
drivers/crypto/fsl/jr.c | 14 +++++++++++---
scripts/config_whitelist.txt | 1 +
10 files changed, 71 insertions(+), 12 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7264d72bde..67f6805b13 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -820,7 +820,7 @@ config ARCH_IMX8M
select ARM64
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select SYS_I2C_MXC
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index b800da13a1..ff8de53f67 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -72,6 +72,7 @@
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
+#define CONFIG_SYS_FSL_JR1_OFFSET (0x2000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index d6a869068a..f3713529da 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -39,6 +39,9 @@ config TARGET_IMX8MQ_EVK
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
@@ -52,6 +55,9 @@ config TARGET_IMX8MM_EVK
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
@@ -91,6 +97,8 @@ config TARGET_IMX8MN_EVK
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
@@ -98,6 +106,8 @@ config TARGET_IMX8MN_DDR4_EVK
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
+ select FSL_CAAM
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
@@ -105,6 +115,9 @@ config TARGET_IMX8MP_EVK
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 863508776d..6e07b0a7c1 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2019, 2021 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
@@ -20,6 +20,7 @@
#include <asm/ptrace.h>
#include <asm/armv8/mmu.h>
#include <dm/uclass.h>
+#include <dm/device.h>
#include <efi_loader.h>
#include <env.h>
#include <env_internal.h>
@@ -1197,6 +1198,14 @@ static void acquire_buildinfo(void)
int arch_misc_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
acquire_buildinfo();
return 0;
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 4ef7f6f180..cf4882cd10 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -51,6 +51,14 @@ static void spl_dram_init(void)
void spl_board_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
puts("Normal Boot\n");
}
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index 03f2a56e80..dfa81a0d65 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -49,6 +49,11 @@ void spl_board_init(void)
struct udevice *dev;
int ret;
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
puts("Normal Boot\n");
ret = uclass_get_device_by_name(UCLASS_CLK,
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index eca42c756e..503a752ae9 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -20,6 +20,8 @@
#include <asm/arch/ddr.h>
#include <power/pmic.h>
#include <power/pca9450.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -35,6 +37,14 @@ void spl_dram_init(void)
void spl_board_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
/*
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
* not allow to change it. Should set the clock after PMIC
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index 67d069b2b0..b28056bb48 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -22,6 +21,7 @@
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc_imx.h>
+#include <fsl_sec.h>
#include <mmc.h>
#include <linux/delay.h>
#include <power/pmic.h>
@@ -199,6 +199,10 @@ int power_init_board(void)
void spl_board_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ if (sec_init())
+ printf("\nsec_init failed!\n");
+ }
puts("Normal Boot\n");
}
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 8103987425..4e7accfb89 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -43,9 +43,17 @@ struct udevice *caam_dev;
#define SEC_ADDR(idx) \
(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
-#define SEC_JR0_ADDR(idx) \
+#ifndef CONFIG_IMX8M
+#define SEC_JR_ADDR(idx) \
(ulong)(SEC_ADDR(idx) + \
(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+#define JR_ID 0
+#else
+#define SEC_JR_ADDR(idx) \
+ (ulong)(SEC_ADDR(idx) + \
+ (CONFIG_SYS_FSL_JR1_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+#define JR_ID 1
+#endif
struct caam_regs caam_st;
#endif
@@ -669,8 +677,8 @@ int sec_init_idx(uint8_t sec_idx)
caam = dev_get_priv(caam_dev);
#else
caam_st.sec = (void *)SEC_ADDR(sec_idx);
- caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- caam_st.jrid = 0;
+ caam_st.regs = (struct jr_regs *)SEC_JR_ADDR(sec_idx);
+ caam_st.jrid = JR_ID;
caam = &caam_st;
#endif
ccsr_sec_t *sec = caam->sec;
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 79f03d1636..98a4bf5aec 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1273,6 +1273,7 @@ CONFIG_SYS_FSL_IFC_LE
CONFIG_SYS_FSL_ISBC_VER
CONFIG_SYS_FSL_JR0_ADDR
CONFIG_SYS_FSL_JR0_OFFSET
+CONFIG_SYS_FSL_JR1_OFFSET
CONFIG_SYS_FSL_LS1_CLK_ADDR
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
CONFIG_SYS_FSL_MAX_NUM_OF_SEC
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 04/14] mx6sabre: Remove unnecessary SPL configs
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (2 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 03/14] crypto/fsl: i.MX8M: Enable Job ring driver model Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 05/14] i.MX6: Enable Job ring driver model Gaurav Jain
` (10 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean
From: Ye Li <ye.li@nxp.com>
Because we don't use SPL_DM on mx6sabresd and mx6sabreauto, so it is
unnecessary to have SPL DTB related configs and SPL_OF_CONTROL enabled.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
---
configs/mx6sabreauto_defconfig | 2 --
configs/mx6sabresd_defconfig | 4 ----
2 files changed, 6 deletions(-)
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index e03ac323ee..03e10f0711 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -62,10 +62,8 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6dl-sabreauto imx6q-sabreauto imx6qp-sabreauto"
CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 6cb74132d5..2e250397e0 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -65,12 +65,8 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd"
CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 05/14] i.MX6: Enable Job ring driver model.
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (3 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 04/14] mx6sabre: Remove unnecessary SPL configs Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 06/14] i.MX7: " Gaurav Jain
` (9 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
i.MX6,i.MX6SX,i.MX6UL - added support for JR driver model.
removed sec_init() call, sec is initialized based on
job ring information processed from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/mach-imx/mx6/Kconfig | 10 ++++++++++
arch/arm/mach-imx/mx6/soc.c | 13 +++++++++----
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 98df4d4e42..3d675fcd73 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -354,6 +354,8 @@ config TARGET_MX6SABREAUTO
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6SABRESD
bool "mx6sabresd"
@@ -364,6 +366,8 @@ config TARGET_MX6SABRESD
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6SLEVK
bool "mx6slevk"
@@ -386,6 +390,8 @@ config TARGET_MX6SXSABRESD
select DM
select DM_THERMAL
select SUPPORT_SPL
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6SXSABREAUTO
bool "mx6sxsabreauto"
@@ -404,6 +410,8 @@ config TARGET_MX6UL_9X9_EVK
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
@@ -413,6 +421,8 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index aacfc854a2..afaad42952 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -4,6 +4,7 @@
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -23,7 +24,6 @@
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
-#include <fsl_sec.h>
#include <imx_thermal.h>
#include <mmc.h>
@@ -734,9 +734,14 @@ static void setup_serial_number(void)
int arch_misc_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
setup_serial_number();
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 06/14] i.MX7: Enable Job ring driver model.
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (4 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 05/14] i.MX6: Enable Job ring driver model Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 07/14] i.MX7ULP: " Gaurav Jain
` (8 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
i.MX7D - added support for JR driver model.
removed sec_init() call, sec is initialized based on
job ring information processed from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-imx/mx7/Kconfig | 1 +
arch/arm/mach-imx/mx7/soc.c | 12 ++++++++----
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 67f6805b13..06efe07b1c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -888,7 +888,7 @@ config ARCH_MX7
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
imply BOARD_EARLY_INIT_F
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 0cad825287..4f9f51c9b0 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -68,6 +68,7 @@ config TARGET_MX7DSABRESD
select DM_THERMAL
select MX7D
imply CMD_DM
+ select FSL_CAAM
config TARGET_PICO_IMX7D
bool "pico-imx7d"
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 21690072e1..e482b3f687 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -19,7 +20,6 @@
#include <dm.h>
#include <env.h>
#include <imx_thermal.h>
-#include <fsl_sec.h>
#include <asm/setup.h>
#include <linux/delay.h>
@@ -353,9 +353,13 @@ int arch_misc_init(void)
env_set("serial#", serial_string);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 07/14] i.MX7ULP: Enable Job ring driver model.
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (5 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 06/14] i.MX7: " Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 08/14] i.MX8: Add crypto node in device tree Gaurav Jain
` (7 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
added crypto node in device tree.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/dts/imx7ulp.dtsi | 24 ++++++++++++++++++++++++
arch/arm/mach-imx/mx7ulp/Kconfig | 2 ++
arch/arm/mach-imx/mx7ulp/soc.c | 18 ++++++++++++++++++
4 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 06efe07b1c..5e3c2ed3eb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -875,7 +875,7 @@ config ARCH_MX7ULP
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select ROM_UNIFIED_SECTIONS
diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
index 7bcd2cc346..494b9d98b2 100644
--- a/arch/arm/dts/imx7ulp.dtsi
+++ b/arch/arm/dts/imx7ulp.dtsi
@@ -1,5 +1,6 @@
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -198,6 +199,29 @@
};
};
+ crypto: crypto@40240000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40240000 0x10000>;
+ ranges = <0 0x40240000 0x10000>;
+ clocks = <&clks IMX7ULP_CLK_CAAM>,
+ <&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
+ clock-names = "aclk", "ipg";
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index 2ffac9cf7c..0d238d2557 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -25,6 +25,8 @@ config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
select MX7ULP
select SYS_ARCH_TIMER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
endchoice
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index c90ce22404..24990f7d7f 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -15,6 +16,7 @@
#include <asm/mach-imx/hab.h>
#include <asm/setup.h>
#include <linux/bitops.h>
+#include <dm.h>
#define PMC0_BASE_ADDR 0x410a1000
#define PMC0_CTRL 0x28
@@ -80,6 +82,22 @@ int arch_cpu_init(void)
return 0;
}
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 08/14] i.MX8: Add crypto node in device tree
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (6 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 07/14] i.MX7ULP: " Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 09/14] crypto/fsl: i.MX8: Enable Job ring driver model Gaurav Jain
` (6 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.
disabled use of JR1 in SPL and uboot, as JR1 is reserved
for SECO FW.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/dts/fsl-imx8dx.dtsi | 61 +++++++++++++++++++++++-
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 ++++++++++++-
arch/arm/dts/fsl-imx8qm.dtsi | 61 +++++++++++++++++++++++-
arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 ++++++++++++-
4 files changed, 186 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 7d95cf0b7d..63a56699b5 100644
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -261,6 +261,30 @@
power-domains = <&pd_dma>;
};
};
+
+ pd_caam: PD_CAAM {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_NONE>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_caam_jr1: PD_CAAM_JR1 {
+ reg = <SC_R_CAAM_JR1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr2: PD_CAAM_JR2 {
+ reg = <SC_R_CAAM_JR2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr3: PD_CAAM_JR3 {
+ reg = <SC_R_CAAM_JR3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ };
};
i2c0: i2c@5a800000 {
@@ -609,6 +633,41 @@
};
};
};
+
+ crypto: caam@0x31400000 {
+ compatible = "fsl,sec-v4.0";
+ reg = <0 0x31400000 0 0x400000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x31400000 0x400000>;
+ fsl,first-jr-index = <2>;
+ fsl,sec-era = <9>;
+
+ sec_jr1: jr1@0x20000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x1000>;
+ interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr1>;
+ status = "disabled";
+ };
+
+ sec_jr2: jr2@30000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x1000>;
+ interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr2>;
+ status = "okay";
+ };
+
+ sec_jr3: jr3@40000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x1000>;
+ interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr3>;
+ status = "okay";
+ };
+ };
};
&A35_0 {
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
index 9e0d264b71..a95209e141 100644
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
&{/imx8qm-pm} {
@@ -80,6 +80,22 @@
u-boot,dm-spl;
};
+&pd_caam {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
@@ -126,3 +142,19 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index 88aeaf65b3..517fb13cad 100644
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -235,6 +235,30 @@
wakeup-irq = <349>;
};
};
+
+ pd_caam: PD_CAAM {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_NONE>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_caam_jr1: PD_CAAM_JR1 {
+ reg = <SC_R_CAAM_JR1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr2: PD_CAAM_JR2 {
+ reg = <SC_R_CAAM_JR2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr3: PD_CAAM_JR3 {
+ reg = <SC_R_CAAM_JR3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ };
};
i2c0: i2c@5a800000 {
@@ -556,6 +580,41 @@
power-domains = <&pd_conn_enet1>;
status = "disabled";
};
+
+ crypto: caam@0x31400000 {
+ compatible = "fsl,sec-v4.0";
+ reg = <0 0x31400000 0 0x400000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x31400000 0x400000>;
+ fsl,first-jr-index = <2>;
+ fsl,sec-era = <9>;
+
+ sec_jr1: jr1@0x20000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x1000>;
+ interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr1>;
+ status = "disabled";
+ };
+
+ sec_jr2: jr2@30000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x1000>;
+ interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr2>;
+ status = "okay";
+ };
+
+ sec_jr3: jr3@40000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x1000>;
+ interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr3>;
+ status = "okay";
+ };
+ };
};
&A53_0 {
diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 701af4434d..ae037c7550 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
&{/imx8qx-pm} {
@@ -80,6 +80,22 @@
u-boot,dm-spl;
};
+&pd_caam {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
@@ -126,3 +142,19 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 09/14] crypto/fsl: i.MX8: Enable Job ring driver model.
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (7 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 08/14] i.MX8: Add crypto node in device tree Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 10/14] Layerscape: Add crypto node in device tree Gaurav Jain
` (5 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
i.MX8(QM/QXP) - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 3 ++
arch/arm/include/asm/arch-imx8/imx-regs.h | 5 ++-
arch/arm/mach-imx/cmd_dek.c | 1 +
arch/arm/mach-imx/imx8/Kconfig | 7 ++++
arch/arm/mach-imx/imx8/cpu.c | 18 ++++++++-
board/freescale/imx8qm_mek/spl.c | 6 ++-
board/freescale/imx8qxp_mek/spl.c | 6 ++-
drivers/crypto/fsl/Kconfig | 2 +-
drivers/crypto/fsl/jr.c | 47 ++++++++++++++++++++++-
include/fsl_sec.h | 12 +++---
10 files changed, 91 insertions(+), 16 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5e3c2ed3eb..dd01856b3e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -809,6 +809,9 @@ config ARCH_LPC32XX
config ARCH_IMX8
bool "NXP i.MX8 platform"
select ARM64
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
select DM
select GPIO_EXTRA_HEADER
select MACH_IMX
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index ed6e05e556..2d64b0604b 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __ASM_ARCH_IMX8_REGS_H__
@@ -47,4 +47,7 @@
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
+#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 89da89c51d..04c4b20a84 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -9,6 +9,7 @@
#include <command.h>
#include <log.h>
#include <malloc.h>
+#include <memalign.h>
#include <asm/byteorder.h>
#include <linux/compiler.h>
#include <fsl_sec.h>
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index b43739e5c6..f969833bab 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -8,6 +8,7 @@ config AHAB_BOOT
config IMX8
bool
+ select HAS_CAAM
config MU_BASE_SPL
hex "MU base address used in SPL"
@@ -72,6 +73,9 @@ config TARGET_IMX8QM_MEK
bool "Support i.MX8QM MEK board"
select BOARD_LATE_INIT
select IMX8QM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_CONGA_QMX8
bool "Support congatec conga-QMX8 board"
@@ -89,6 +93,9 @@ config TARGET_IMX8QXP_MEK
bool "Support i.MX8QXP MEK board"
select BOARD_LATE_INIT
select IMX8QXP
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
endchoice
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index ee5cc47903..991908fbd3 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <common.h>
@@ -89,6 +89,22 @@ int arch_cpu_init_dm(void)
return 0;
}
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
+
+ return 0;
+}
+#endif
+
int print_bootinfo(void)
{
enum boot_device bt_dev = get_boot_device();
diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c
index 944ba745c0..332a662dee 100644
--- a/board/freescale/imx8qm_mek/spl.c
+++ b/board/freescale/imx8qm_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -24,6 +24,8 @@ void spl_board_init(void)
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c
index ae6b64ff6e..2fa6840056 100644
--- a/board/freescale/imx8qxp_mek/spl.c
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -39,6 +39,8 @@ void spl_board_init(void)
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 231eb00b5f..e03fcdd9c7 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -12,7 +12,7 @@ config FSL_CAAM
config CAAM_64BIT
bool
- default y if PHYS_64BIT && !ARCH_IMX8M
+ default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8
help
Select Crypto driver for 64 bits CAAM version
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 4e7accfb89..a84440ab10 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
#include <linux/kernel.h>
#include <log.h>
#include <malloc.h>
+#include <power-domain.h>
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
@@ -121,7 +122,9 @@ static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
{
struct jobring *jr = &caam->jr[sec_idx];
-
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+#endif
memset(jr, 0, sizeof(struct jobring));
jr->jq_id = caam->jrid;
@@ -146,7 +149,11 @@ static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
memset(jr->output_ring, 0, jr->op_size);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ if (!ofnode_valid(scu_node))
+#endif
start_jr(caam);
+
jr_initregs(sec_idx, caam);
return 0;
@@ -681,6 +688,13 @@ int sec_init_idx(uint8_t sec_idx)
caam_st.jrid = JR_ID;
caam = &caam_st;
#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+
+ if (ofnode_valid(scu_node))
+ goto init;
+#endif
+
ccsr_sec_t *sec = caam->sec;
uint32_t mcr = sec_in32(&sec->mcfgr);
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
@@ -742,12 +756,19 @@ int sec_init_idx(uint8_t sec_idx)
liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
+#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+init:
#endif
ret = jr_init(sec_idx, caam);
if (ret < 0) {
printf("SEC%u: initialization failed\n", sec_idx);
return -1;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ if (ofnode_valid(scu_node))
+ return ret;
+#endif
#ifdef CONFIG_FSL_CORENET
ret = sec_config_pamu_table(liodn_ns, liodn_s);
@@ -781,6 +802,23 @@ int sec_init(void)
}
#if CONFIG_IS_ENABLED(DM)
+static int jr_power_on(ofnode node)
+{
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+ struct udevice __maybe_unused jr_dev;
+ struct power_domain pd;
+
+ dev_set_ofnode(&jr_dev, node);
+
+ /* Power on Job Ring before access it */
+ if (!power_domain_get(&jr_dev, &pd)) {
+ if (power_domain_on(&pd))
+ return -EINVAL;
+ }
+#endif
+ return 0;
+}
+
static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
{
if (request != CAAM_JR_RUN_DESC)
@@ -793,7 +831,7 @@ static int caam_jr_probe(struct udevice *dev)
{
struct caam_regs *caam = dev_get_priv(dev);
fdt_addr_t addr;
- ofnode node;
+ ofnode node, scu_node;
unsigned int jr_node = 0;
caam_dev = dev;
@@ -818,6 +856,11 @@ static int caam_jr_probe(struct udevice *dev)
jr_node = jr_node >> 4;
caam->jrid = jr_node - 1;
+ scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+ if (ofnode_valid(scu_node)) {
+ if (jr_power_on(node))
+ return -EINVAL;
+ }
break;
}
}
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index c4121696f8..7b6e3e2c20 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -3,7 +3,7 @@
* Common internal memory map for some Freescale SoCs
*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __FSL_SEC_H
@@ -194,12 +194,10 @@ typedef struct ccsr_sec {
#define SEC_CHAVID_LS_RNG_SHIFT 16
#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
-#define CONFIG_JRSTARTR_JR0 0x00000001
-
struct jr_regs {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
u32 irba_l;
u32 irba_h;
#else
@@ -214,7 +212,7 @@ struct jr_regs {
u32 irja;
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
u32 orba_l;
u32 orba_h;
#else
@@ -248,7 +246,7 @@ struct jr_regs {
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
uint32_t addr_lo; /* Memory Address - lo */
uint32_t addr_hi; /* Memory Address of start of buffer - hi */
#else
@@ -268,7 +266,7 @@ struct sg_entry {
};
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
/* Job Ring Base Address */
#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
/* Secure Memory Offset varies accross versions */
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 10/14] Layerscape: Add crypto node in device tree
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (8 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 09/14] crypto/fsl: i.MX8: Enable Job ring driver model Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 11/14] Layerscape: Enable Job ring driver model Gaurav Jain
` (4 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/arm/dts/fsl-ls1012a.dtsi | 46 ++++++++++++++++++++++++++++++++++-
arch/arm/dts/fsl-ls1043a.dtsi | 45 +++++++++++++++++++++++++++++++++-
arch/arm/dts/fsl-ls1046a.dtsi | 44 +++++++++++++++++++++++++++++++++
arch/arm/dts/fsl-ls1088a.dtsi | 39 +++++++++++++++++++++++++++++
arch/arm/dts/fsl-ls2080a.dtsi | 39 +++++++++++++++++++++++++++++
arch/arm/dts/fsl-lx2160a.dtsi | 41 ++++++++++++++++++++++++++++++-
arch/arm/dts/ls1021a.dtsi | 40 ++++++++++++++++++++++++++++++
7 files changed, 291 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 0ea899c7d7..1cdcc99c1e 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor
*/
@@ -71,6 +71,50 @@
bus-width = <4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 52dc5a9638..72877d2ff5 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1043A family SoC.
*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
@@ -125,6 +125,49 @@
interrupts = <0 43 0x4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index a60cbf11fc..c655e002aa 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright (C) 2016, Freescale Semiconductor
+ * Copyright 2021 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
@@ -124,6 +125,49 @@
interrupts = <0 43 0x4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index f73fdfda8b..9b7c54b260 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -174,6 +174,45 @@
dr_mode = "host";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 72ba52594a..a1837454f4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -239,6 +239,45 @@
status = "disabled";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <0 139 0x4>; /* Level high type */
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 140 0x4>; /* Level high type */
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 141 0x4>; /* Level high type */
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 142 0x4>; /* Level high type */
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 143 0x4>; /* Level high type */
+ };
+ };
+
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc", "simple-mfd";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 52e4d7205a..57c7d3ef71 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP lx2160a SOC common device tree source
*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*
*/
@@ -27,6 +27,45 @@
clock-output-names = "sysclk";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
clockgen: clocking@1300000 {
compatible = "fsl,ls2080a-clockgen";
reg = <0 0x1300000 0 0xa0000>;
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 86192cbb7f..be330c130f 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -3,6 +3,7 @@
* Freescale ls1021a SOC common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include "skeleton.dtsi"
@@ -144,6 +145,45 @@
big-endian;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1700000 0x100000>;
+ ranges = <0x0 0x1700000 0x100000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
clockgen: clocking@1ee1000 {
#address-cells = <1>;
#size-cells = <1>;
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 11/14] Layerscape: Enable Job ring driver model.
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (9 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 10/14] Layerscape: Add crypto node in device tree Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 15:50 ` Michael Walle
2022-01-12 13:31 ` [PATCH v10 12/14] PPC: Add crypto node in device tree Gaurav Jain
` (3 subsequent siblings)
14 siblings, 1 reply; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162
platforms are enabled with JR driver model.
removed sec_init() call from board files.
removed CONFIG_FSL_CAAM from defconfig files.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 18 ++++++++++++++++++
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 11 ++++++++++-
board/freescale/ls1012afrdm/ls1012afrdm.c | 7 +------
board/freescale/ls1012aqds/ls1012aqds.c | 6 +-----
board/freescale/ls1012ardb/ls1012ardb.c | 6 +-----
board/freescale/ls1021aiot/ls1021aiot.c | 6 ++----
board/freescale/ls1021aqds/ls1021aqds.c | 6 +-----
board/freescale/ls1021atsn/ls1021atsn.c | 7 ++-----
board/freescale/ls1021atwr/ls1021atwr.c | 8 ++------
board/freescale/ls1028a/ls1028a.c | 6 +-----
board/freescale/ls1043ardb/ls1043ardb.c | 6 +-----
board/freescale/ls1046afrwy/ls1046afrwy.c | 7 +------
board/freescale/ls1046aqds/ls1046aqds.c | 7 +------
board/freescale/ls1046ardb/ls1046ardb.c | 6 +-----
board/freescale/ls1088a/ls1088a.c | 6 +-----
board/freescale/ls2080aqds/ls2080aqds.c | 6 +-----
board/freescale/ls2080ardb/ls2080ardb.c | 9 +--------
board/freescale/lx2160a/lx2160a.c | 5 -----
board/kontron/sl28/sl28.c | 3 ---
configs/ls1021aiot_qspi_defconfig | 1 +
configs/ls1021aiot_sdcard_defconfig | 1 +
configs/ls1021aqds_ddr4_nor_defconfig | 1 +
configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 +
configs/ls1021aqds_nand_defconfig | 1 +
configs/ls1021aqds_nor_defconfig | 1 +
configs/ls1021aqds_nor_lpuart_defconfig | 1 +
configs/ls1021aqds_qspi_defconfig | 1 +
configs/ls1021aqds_sdcard_ifc_defconfig | 1 +
configs/ls1021aqds_sdcard_qspi_defconfig | 1 +
configs/ls1021atsn_qspi_defconfig | 1 +
configs/ls1021atsn_sdcard_defconfig | 1 +
configs/ls1021atwr_nor_defconfig | 1 +
configs/ls1021atwr_nor_lpuart_defconfig | 1 +
configs/ls1021atwr_qspi_defconfig | 1 +
...ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
configs/ls1021atwr_sdcard_ifc_defconfig | 1 +
configs/ls1021atwr_sdcard_qspi_defconfig | 1 +
configs/ls1043aqds_defconfig | 1 +
configs/ls1043aqds_lpuart_defconfig | 1 +
configs/ls1043aqds_nand_defconfig | 1 +
configs/ls1043aqds_nor_ddr3_defconfig | 1 +
configs/ls1043aqds_qspi_defconfig | 1 +
configs/ls1043aqds_sdcard_ifc_defconfig | 1 +
configs/ls1043aqds_sdcard_qspi_defconfig | 1 +
configs/ls1043aqds_tfa_defconfig | 1 +
configs/ls1043ardb_defconfig | 1 +
configs/ls1043ardb_nand_defconfig | 1 +
configs/ls1043ardb_sdcard_defconfig | 1 +
configs/ls1043ardb_tfa_defconfig | 1 +
configs/ls1046afrwy_tfa_defconfig | 1 +
configs/ls1046aqds_defconfig | 1 +
configs/ls1046aqds_lpuart_defconfig | 1 +
configs/ls1046aqds_nand_defconfig | 1 +
configs/ls1046aqds_qspi_defconfig | 1 +
configs/ls1046aqds_sdcard_ifc_defconfig | 1 +
configs/ls1046aqds_sdcard_qspi_defconfig | 1 +
configs/ls1046aqds_tfa_defconfig | 1 +
configs/ls1046ardb_emmc_defconfig | 1 +
configs/ls1046ardb_qspi_defconfig | 1 +
configs/ls1046ardb_qspi_spl_defconfig | 1 +
configs/ls1046ardb_sdcard_defconfig | 1 +
configs/ls1046ardb_tfa_defconfig | 1 +
62 files changed, 89 insertions(+), 90 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d863c9625a..9fe1cd9048 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -20,6 +21,7 @@
#include <config.h>
#include <fsl_wdog.h>
#include <linux/delay.h>
+#include <dm.h>
#include "fsl_epu.h"
@@ -397,3 +399,19 @@ void arch_preboot_os(void)
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 2ded3e4efc..0fffddab71 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
@@ -49,6 +49,7 @@
#endif
#endif
#include <linux/mii.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -1650,6 +1651,14 @@ __weak int serdes_misc_init(void)
int arch_misc_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
serdes_misc_init();
return 0;
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index 5dd19cfcd9..bc37c553a5 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2021 NXP
*/
#include <common.h>
@@ -22,7 +22,6 @@
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -172,10 +171,6 @@ int board_init(void)
if (current_el() == 3)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 68578e81a5..361bd5c582 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -28,7 +29,6 @@
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"
@@ -150,10 +150,6 @@ int board_init(void)
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 064fb4d39f..456609d993 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -27,7 +28,6 @@
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -173,10 +173,6 @@ int board_init(void)
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index bfe6137604..5ab03b3340 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -209,10 +210,7 @@ int misc_init_r(void)
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 0647622cde..2eaad9e742 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -20,7 +20,6 @@
#include <mmc.h>
#include <fsl_csu.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include <fsl_devdis.h>
#include <fsl_validate.h>
@@ -388,9 +387,6 @@ int misc_init_r(void)
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
-#endif
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
#endif
return 0;
}
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index f31e16c419..f016088670 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP
+/* Copyright 2016-2019, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@@ -238,10 +238,7 @@ int misc_init_r(void)
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index f0b441db63..a2a87eaf35 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -26,7 +26,6 @@
#include <netdev.h>
#include <fsl_mdio.h>
#include <tsec.h>
-#include <fsl_sec.h>
#include <fsl_devdis.h>
#include <spl.h>
#include <linux/delay.h>
@@ -555,10 +554,7 @@ int misc_init_r(void)
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_board_mux();
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index 486a544d35..71a086ef67 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -73,10 +73,6 @@ u32 get_lpuart_clk(void)
int board_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index beef26b084..c7f214c236 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -20,7 +21,6 @@
#include <fm_eth.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
@@ -211,10 +211,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index f1c08a13f7..5a298cd311 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -20,7 +20,6 @@
#include <fm_eth.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
-#include <fsl_sec.h>
#include <fsl_dspi.h>
#include "../common/i2c_mux.h"
@@ -135,10 +134,6 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 8481c45a58..e5b5441e2c 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*/
#include <common.h>
@@ -28,7 +28,6 @@
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include "../common/i2c_mux.h"
@@ -421,10 +420,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
return 0;
}
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 93ef903f29..2e9a6d44eb 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -23,7 +24,6 @@
#include <fsl_esdhc.h>
#include <power/mc34vr500_pmic.h>
#include "cpld.h"
-#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -85,10 +85,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index aa548b20d7..db94ee5689 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@@ -13,7 +13,6 @@
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
@@ -820,9 +819,6 @@ int board_init(void)
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 297629d5ef..5bdafebb6b 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@@ -21,7 +22,6 @@
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
-#include <fsl_sec.h>
#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
@@ -222,10 +222,6 @@ int board_init(void)
#endif
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 1975b0f47d..f5ebb934eb 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
- * Copyright 2017 NXP
+ * Copyright 2017, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@@ -24,7 +24,6 @@
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
-#include <fsl_sec.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
@@ -288,9 +287,6 @@ int board_init(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
@@ -299,9 +295,6 @@ int board_init(void)
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index bda665624d..c8a47c6bae 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -14,7 +14,6 @@
#include <errno.h>
#include <netdev.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/bitops.h>
@@ -596,10 +595,6 @@ int board_init(void)
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
index e84b356918..7f2a8aac62 100644
--- a/board/kontron/sl28/sl28.c
+++ b/board/kontron/sl28/sl28.c
@@ -28,9 +28,6 @@ int board_early_init_f(void)
int board_init(void)
{
- if (CONFIG_IS_ENABLED(FSL_CAAM))
- sec_init();
-
return 0;
}
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index 4705e34e1d..fec664a21d 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -39,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index e387264d89..b451a1fe54 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -56,6 +56,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 79ccc41a43..d8e53965bc 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -52,6 +52,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 0a2a076332..a8d49a48bb 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -53,6 +53,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 0b12f100d4..8e3d8eaaaa 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -73,6 +73,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index f4e2274fb8..71b18a0ebb 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -52,6 +52,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 0eacaa3354..b1c2d26747 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -53,6 +53,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index f967619ef9..ac044dd808 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -51,6 +51,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index fa190a7502..65f2dfb808 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -70,6 +70,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 625dd086ab..8cc5e4b8cb 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -68,6 +68,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index 5c8cee3ea9..80c3c5fe05 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -38,6 +38,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index a3b8f248c7..4d0305e564 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 02c25cda7d..2e40e8da3c 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -46,6 +46,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 49d6dda6a5..d8a8b84cdf 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -47,6 +47,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 36a8aee0b1..19db8465b8 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -47,6 +47,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 756e072f9c..8a3233e54a 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -62,6 +62,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_SPL_OF_CONTROL=y
# CONFIG_SPL_BLK is not set
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index ede4c95dd1..a13604722b 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -64,6 +64,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 1315043094..42dc2aa5d2 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -64,6 +64,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 1a484ff483..043c3b7e3a 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -51,6 +51,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index dfd7fb881b..57d8c2c8c3 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -52,6 +52,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 9e87f0fd88..5315e8d035 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -71,6 +71,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index bffe105220..fc74b41be1 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -51,6 +51,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index e01324ccef..cf2ccb6f0a 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -52,6 +52,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index b487b370b5..80d19ae2c4 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -70,6 +70,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 084d104ea4..dc32606ab0 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -69,6 +69,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 8d02bed8e1..54f6941818 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -59,6 +59,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index ca6958fdb4..9aafa72a64 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -38,6 +38,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index e8986db42b..744fb2af24 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -59,6 +59,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index c399ed0891..e370a7df20 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -58,6 +58,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 99c125731f..d2605da1b2 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -42,6 +42,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_ADDR=0x60500000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index af07b1cd46..48f191778a 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -40,6 +40,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
# CONFIG_DDR_SPD is not set
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index f136aeafae..b4a488ff96 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -52,6 +52,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
index 6d448905ef..d366246e07 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -53,6 +53,7 @@ CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index e4cd4a2f60..30cbf4ee7e 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -71,6 +71,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index fe295c51e4..13800e1c23 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -53,6 +53,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index fe1fe6f162..6c4cdb1c24 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -72,6 +72,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index 18f560e947..bf786f0d49 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -71,6 +71,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index f706dd6179..cca009bbfe 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -60,6 +60,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 46301fb183..52b1e65049 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -61,6 +61,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 1837833a8d..bf8c842aae 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -47,6 +47,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index 777b7678a3..529b2a99ec 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -66,6 +66,7 @@ CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index ac8f2bcb1b..49efcf463e 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -60,6 +60,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 149091af4a..da20951ad0 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -45,6 +45,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 12/14] PPC: Add crypto node in device tree
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (10 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 11/14] Layerscape: Enable Job ring driver model Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 13/14] PPC: Enable Job ring driver model Gaurav Jain
` (2 subsequent siblings)
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
device tree imported from linux kernel.
c500bee1c5b2 (tag: v5.14-rc4) Linux 5.14-rc4
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/powerpc/dts/p2041si-post.dtsi | 1 +
arch/powerpc/dts/p3041si-post.dtsi | 1 +
arch/powerpc/dts/p4080si-post.dtsi | 1 +
arch/powerpc/dts/p5040si-post.dtsi | 1 +
arch/powerpc/dts/qoriq-sec4.0-0.dtsi | 74 ++++++++++++++++++++++
arch/powerpc/dts/qoriq-sec4.2-0.dtsi | 83 +++++++++++++++++++++++++
arch/powerpc/dts/qoriq-sec5.2-0.dtsi | 92 ++++++++++++++++++++++++++++
arch/powerpc/dts/t1023si-post.dtsi | 1 +
arch/powerpc/dts/t1042si-post.dtsi | 1 +
arch/powerpc/dts/t2080si-post.dtsi | 1 +
arch/powerpc/dts/t4240si-post.dtsi | 1 +
11 files changed, 257 insertions(+)
create mode 100644 arch/powerpc/dts/qoriq-sec4.0-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec4.2-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec5.2-0.dtsi
diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi
index 01ab395950..8819199646 100644
--- a/arch/powerpc/dts/p2041si-post.dtsi
+++ b/arch/powerpc/dts/p2041si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p3041si-post.dtsi b/arch/powerpc/dts/p3041si-post.dtsi
index 21f322f06f..a3e8088d25 100644
--- a/arch/powerpc/dts/p3041si-post.dtsi
+++ b/arch/powerpc/dts/p3041si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p4080si-post.dtsi b/arch/powerpc/dts/p4080si-post.dtsi
index 7c3f2fb92e..56b79b14f4 100644
--- a/arch/powerpc/dts/p4080si-post.dtsi
+++ b/arch/powerpc/dts/p4080si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p5040si-post.dtsi b/arch/powerpc/dts/p5040si-post.dtsi
index 1efad2d017..fae3ed31a5 100644
--- a/arch/powerpc/dts/p5040si-post.dtsi
+++ b/arch/powerpc/dts/p5040si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/qoriq-sec4.0-0.dtsi b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
new file mode 100644
index 0000000000..ff348d70f1
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sec4.2-0.dtsi b/arch/powerpc/dts/qoriq-sec4.2-0.dtsi
new file mode 100644
index 0000000000..57a0bc5c56
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec4.2-0.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+ fsl,sec-era = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.2-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sec5.2-0.dtsi b/arch/powerpc/dts/qoriq-sec5.2-0.dtsi
new file mode 100644
index 0000000000..e5f87effd3
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec5.2-0.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <5>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v5.2-rtic",
+ "fsl,sec-v5.0-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/t1023si-post.dtsi b/arch/powerpc/dts/t1023si-post.dtsi
index 7284eb9791..6f666a1554 100644
--- a/arch/powerpc/dts/t1023si-post.dtsi
+++ b/arch/powerpc/dts/t1023si-post.dtsi
@@ -14,6 +14,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman3l-0.dtsi"
diff --git a/arch/powerpc/dts/t1042si-post.dtsi b/arch/powerpc/dts/t1042si-post.dtsi
index 5c60944e60..eebbbaf0e1 100644
--- a/arch/powerpc/dts/t1042si-post.dtsi
+++ b/arch/powerpc/dts/t1042si-post.dtsi
@@ -12,6 +12,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-fman3l-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
diff --git a/arch/powerpc/dts/t2080si-post.dtsi b/arch/powerpc/dts/t2080si-post.dtsi
index d8ef579cb7..c06526b3db 100644
--- a/arch/powerpc/dts/t2080si-post.dtsi
+++ b/arch/powerpc/dts/t2080si-post.dtsi
@@ -13,6 +13,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
/include/ "qoriq-fman3-0.dtsi"
/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi"
diff --git a/arch/powerpc/dts/t4240si-post.dtsi b/arch/powerpc/dts/t4240si-post.dtsi
index a596f48b54..9fa99ae771 100644
--- a/arch/powerpc/dts/t4240si-post.dtsi
+++ b/arch/powerpc/dts/t4240si-post.dtsi
@@ -12,6 +12,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-fman3-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 13/14] PPC: Enable Job ring driver model.
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (11 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 12/14] PPC: Add crypto node in device tree Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 14/14] update CAAM MAINTAINER Gaurav Jain
2022-01-31 6:01 ` [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
removed sec_init() call and CONFIG_FSL_CAAM from defconfig.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 +++++++++++++++++--
arch/powerpc/include/asm/u-boot-ppc.h | 17 +++++++++++++++++
arch/powerpc/include/asm/u-boot.h | 1 +
configs/P2041RDB_NAND_defconfig | 1 +
configs/P2041RDB_SDCARD_defconfig | 1 +
configs/P2041RDB_SPIFLASH_defconfig | 1 +
configs/P2041RDB_defconfig | 1 +
configs/P3041DS_NAND_defconfig | 1 +
configs/P3041DS_SDCARD_defconfig | 1 +
configs/P3041DS_SPIFLASH_defconfig | 1 +
configs/P3041DS_defconfig | 1 +
configs/P4080DS_SDCARD_defconfig | 1 +
configs/P4080DS_SPIFLASH_defconfig | 1 +
configs/P4080DS_defconfig | 1 +
configs/P5040DS_NAND_defconfig | 1 +
configs/P5040DS_SDCARD_defconfig | 1 +
configs/P5040DS_SPIFLASH_defconfig | 1 +
configs/P5040DS_defconfig | 1 +
configs/T1024RDB_NAND_defconfig | 1 +
configs/T1024RDB_SDCARD_defconfig | 1 +
configs/T1024RDB_SPIFLASH_defconfig | 1 +
configs/T1024RDB_defconfig | 1 +
configs/T1042D4RDB_NAND_defconfig | 1 +
configs/T1042D4RDB_SDCARD_defconfig | 1 +
configs/T1042D4RDB_SPIFLASH_defconfig | 1 +
configs/T1042D4RDB_defconfig | 1 +
configs/T2080QDS_NAND_defconfig | 1 +
configs/T2080QDS_SDCARD_defconfig | 1 +
configs/T2080QDS_SPIFLASH_defconfig | 1 +
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 +
configs/T2080QDS_defconfig | 1 +
configs/T2080RDB_NAND_defconfig | 1 +
configs/T2080RDB_SDCARD_defconfig | 1 +
configs/T2080RDB_SPIFLASH_defconfig | 1 +
configs/T2080RDB_defconfig | 1 +
configs/T2080RDB_revD_NAND_defconfig | 1 +
configs/T2080RDB_revD_SDCARD_defconfig | 1 +
configs/T2080RDB_revD_SPIFLASH_defconfig | 1 +
configs/T2080RDB_revD_defconfig | 1 +
configs/T4240RDB_SDCARD_defconfig | 1 +
configs/T4240RDB_defconfig | 1 +
41 files changed, 73 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/include/asm/u-boot-ppc.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e920e01b25..c64f0ac7aa 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -56,6 +56,7 @@
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
#endif
+#include <dm.h>
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
@@ -974,8 +975,6 @@ int cpu_init_r(void)
#endif
#ifdef CONFIG_FSL_CAAM
- sec_init();
-
#if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293))
@@ -1014,6 +1013,22 @@ int cpu_init_r(void)
return 0;
}
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
+
+ return 0;
+}
+#endif
+
void arch_preboot_os(void)
{
u32 msr;
diff --git a/arch/powerpc/include/asm/u-boot-ppc.h b/arch/powerpc/include/asm/u-boot-ppc.h
new file mode 100644
index 0000000000..372ca3e037
--- /dev/null
+++ b/arch/powerpc/include/asm/u-boot-ppc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2021 NXP
+ *
+ * Gaurav Jain <gaurav.jain@nxp.com>
+ */
+
+#ifndef _U_BOOT_PPC_H_
+#define _U_BOOT_PPC_H_
+
+#ifndef __ASSEMBLY__
+
+int arch_misc_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _U_BOOT_PPC_H_ */
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index 19b3c0db5f..36af8e5403 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -21,5 +21,6 @@
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
#include <asm/ppc.h>
+#include <asm/u-boot-ppc.h>
#endif /* __U_BOOT_H__ */
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index b7acfe05ae..cef39122c6 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -41,6 +41,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFFA00C21
CONFIG_SYS_OR0_PRELIM=0xFFFC0796
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index fa21910b42..0091cdb7fe 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -42,6 +42,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index ba9b8dfb5f..1b48d1c39f 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -43,6 +43,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 53130ccf82..83c6a7814e 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -38,6 +38,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 29a968d9a3..6988595208 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -39,6 +39,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 72c3b7af29..783c96cdd3 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index abb9ce611d..e601165ad5 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -41,6 +41,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 39dd70888c..9e710029ef 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -36,6 +36,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index bd66e31fe1..be23b6a1e9 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 79f51c91d4..be184e14fd 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -41,6 +41,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 43f16d45e2..67484e64ba 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -36,6 +36,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 6f31034573..2712c1e519 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 0a881d8417..7d88deb456 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 0e4a5457ef..1ebbd303d7 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -41,6 +41,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index d614917385..68628220f3 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -36,6 +36,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 086e579090..bc55e6458b 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -63,6 +63,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 5afce38499..82b8fac8d4 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -62,6 +62,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 90d745bf34..a704634427 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -64,6 +64,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 98f1d6c794..9a87002a7b 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -47,6 +47,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index ca22e1e4f2..d0c4b96d52 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -54,6 +54,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index b9f7992d35..8aaf832852 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -53,6 +53,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index f8e2b6d2ee..9e8d22c31c 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -55,6 +55,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 4797f2907f..fcb144e846 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -38,6 +38,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index ba07ce8feb..e812ed9791 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -57,6 +57,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index bf5410b344..92578d2597 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -56,6 +56,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 367416f337..25d6e2cdc0 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -58,6 +58,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index ef4d8888b6..ba529f8a4d 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -38,6 +38,7 @@ CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index db9e970e64..2416b083b7 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -41,6 +41,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 4501cf64e4..839b7e2796 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -61,6 +61,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index f62c85c805..965a91c1b6 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -60,6 +60,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 2a7529d1cc..d350cd1104 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -62,6 +62,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 6b076405d6..1b92f92bfe 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -45,6 +45,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index cdd7524ec4..73c55a9665 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -62,6 +62,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index 1771c24003..7cf967db7f 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -61,6 +61,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index bb9d5c809e..049c53ab8d 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -63,6 +63,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index 472463fabb..7646a9fd10 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -46,6 +46,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 526c474955..b9a6e7379a 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -52,6 +52,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index bbaab35fd8..a61183512f 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -37,6 +37,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v10 14/14] update CAAM MAINTAINER
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (12 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 13/14] PPC: Enable Job ring driver model Gaurav Jain
@ 2022-01-12 13:31 ` Gaurav Jain
2022-01-31 6:01 ` [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-12 13:31 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
updated CAAM driver files maintainer.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f4bd3d79e2..1c912b2c65 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1334,3 +1334,9 @@ T: git https://source.denx.de/u-boot/u-boot.git
F: configs/tools-only_defconfig
F: *
F: */
+
+CAAM
+M: Gaurav Jain <gaurav.jain@nxp.com>
+S: Maintained
+F: drivers/crypto/fsl/
+F: include/fsl_sec.h
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v10 11/14] Layerscape: Enable Job ring driver model.
2022-01-12 13:31 ` [PATCH v10 11/14] Layerscape: Enable Job ring driver model Gaurav Jain
@ 2022-01-12 15:50 ` Michael Walle
0 siblings, 0 replies; 23+ messages in thread
From: Michael Walle @ 2022-01-12 15:50 UTC (permalink / raw)
To: Gaurav Jain
Cc: u-boot, Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean
Am 2022-01-12 14:31, schrieb Gaurav Jain:
> LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162
> platforms are enabled with JR driver model.
>
> removed sec_init() call from board files.
> removed CONFIG_FSL_CAAM from defconfig files.
> sec is initialized based on job ring information processed
> from device tree.
>
> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
..
> configs/ls1021aiot_qspi_defconfig | 1 +
> configs/ls1021aiot_sdcard_defconfig | 1 +
> configs/ls1021aqds_ddr4_nor_defconfig | 1 +
> configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 +
> configs/ls1021aqds_nand_defconfig | 1 +
> configs/ls1021aqds_nor_defconfig | 1 +
> configs/ls1021aqds_nor_lpuart_defconfig | 1 +
> configs/ls1021aqds_qspi_defconfig | 1 +
> configs/ls1021aqds_sdcard_ifc_defconfig | 1 +
> configs/ls1021aqds_sdcard_qspi_defconfig | 1 +
> configs/ls1021atsn_qspi_defconfig | 1 +
> configs/ls1021atsn_sdcard_defconfig | 1 +
> configs/ls1021atwr_nor_defconfig | 1 +
> configs/ls1021atwr_nor_lpuart_defconfig | 1 +
> configs/ls1021atwr_qspi_defconfig | 1 +
> ...ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
> configs/ls1021atwr_sdcard_ifc_defconfig | 1 +
> configs/ls1021atwr_sdcard_qspi_defconfig | 1 +
> configs/ls1043aqds_defconfig | 1 +
> configs/ls1043aqds_lpuart_defconfig | 1 +
> configs/ls1043aqds_nand_defconfig | 1 +
> configs/ls1043aqds_nor_ddr3_defconfig | 1 +
> configs/ls1043aqds_qspi_defconfig | 1 +
> configs/ls1043aqds_sdcard_ifc_defconfig | 1 +
> configs/ls1043aqds_sdcard_qspi_defconfig | 1 +
> configs/ls1043aqds_tfa_defconfig | 1 +
> configs/ls1043ardb_defconfig | 1 +
> configs/ls1043ardb_nand_defconfig | 1 +
> configs/ls1043ardb_sdcard_defconfig | 1 +
> configs/ls1043ardb_tfa_defconfig | 1 +
> configs/ls1046afrwy_tfa_defconfig | 1 +
> configs/ls1046aqds_defconfig | 1 +
> configs/ls1046aqds_lpuart_defconfig | 1 +
> configs/ls1046aqds_nand_defconfig | 1 +
> configs/ls1046aqds_qspi_defconfig | 1 +
> configs/ls1046aqds_sdcard_ifc_defconfig | 1 +
> configs/ls1046aqds_sdcard_qspi_defconfig | 1 +
> configs/ls1046aqds_tfa_defconfig | 1 +
> configs/ls1046ardb_emmc_defconfig | 1 +
> configs/ls1046ardb_qspi_defconfig | 1 +
> configs/ls1046ardb_qspi_spl_defconfig | 1 +
> configs/ls1046ardb_sdcard_defconfig | 1 +
> configs/ls1046ardb_tfa_defconfig | 1 +
These are all setting CONFIG_ARCH_MISC_INIT=y which should
probably done by the ARCH symbol, see FSL_LSCH3 for example.
I don't think this is something the user should take
care of and will save you all these settings. But I neither
care for ls1021a nor for ls104[36], thus for everything else:
Reviewed-by: Michael Walle <michael@walle.cc>
-michael
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v10 01/14] crypto/fsl: Add support for CAAM Job ring driver model
2022-01-12 13:31 ` [PATCH v10 01/14] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
@ 2022-01-12 20:03 ` Simon Glass
0 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2022-01-12 20:03 UTC (permalink / raw)
To: Gaurav Jain
Cc: U-Boot Mailing List, Stefano Babic, Fabio Estevam, Peng Fan,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean
On Wed, 12 Jan 2022 at 06:32, Gaurav Jain <gaurav.jain@nxp.com> wrote:
>
> added device tree support for job ring driver.
> sec is initialized based on job ring information processed
> from device tree.
>
> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> drivers/crypto/fsl/Kconfig | 1 +
> drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++-------------
> drivers/crypto/fsl/jr.h | 31 +++-
> 3 files changed, 241 insertions(+), 114 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v10 00/14] Add CAAM driver model support
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
` (13 preceding siblings ...)
2022-01-12 13:31 ` [PATCH v10 14/14] update CAAM MAINTAINER Gaurav Jain
@ 2022-01-31 6:01 ` Gaurav Jain
14 siblings, 0 replies; 23+ messages in thread
From: Gaurav Jain @ 2022-01-31 6:01 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil Malhotra, Pankaj Gupta,
Varun Sethi, dl-uboot-imx, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Andy Tang, Adrian Alonso, Vladimir Oltean
Hi Stefano
Can you help to review and merge this patch series.
Regards
Gaurav Jain
> -----Original Message-----
> From: Gaurav Jain
> Sent: Wednesday, January 12, 2022 7:02 PM
> To: u-boot@lists.denx.de
> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>;
> Peng Fan <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Michael
> Walle <michael@walle.cc>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean
> <olteanv@gmail.com>; Gaurav Jain <gaurav.jain@nxp.com>
> Subject: [PATCH v10 00/14] Add CAAM driver model support
>
> This patchset adds the support for following:
> 1) CAAM Driver model for all i.MX, layerscape, PPC platforms.
> 2) Added crypto node in device tree files.
> 3) fix build issue for mx6sabre: Remove SPL DTB related configs and
> SPL_OF_CONTROL.
>
> i.MX platforms:
> i.MX6, i.MX7, i.MX7ULP, i.MX8MM/MN/MP/MQ, i.MX8QM/QXP
>
> Layerscape platforms:
> LS1021, LS1012, LS1028, LS1043, LS1046, LS1088, LS2088, LX2160, LX2162
>
> Powerpc platforms:
> P3041, P4080, P5040, P2041, T1024, T1042, T2080, T4240
>
> changes since v9:
> - added IS_ENABLED(CONFIG_FSL_CAAM) check before probing CAAM driver.
> - FSL_CAAM enablement is moved to defconfigs for layerscape, powerpc.
>
> changes since v8:
> - rebase to latest master
> - removed patch "crypto/fsl: Improve hwrng performance in kernel".
> - moved FSL_CAAM config to board defconfig for Layerscape platforms.
> - moved MISC config select to "config FSL_CAAM" as "select MISC if DM".
>
> changes since v7:
> - rebase to latest master
> - corrected the order of include files as per coding style in jr.c.
> https://www.denx.de/wiki/U-Boot/CodingStyle
> - added brackets around #defines for -ve number in jr.h
> - added comments for struct caam_regs in jr.h
>
> changes since v6:
> - rebase to latest master
> - added caam_jr_ioctl() operation which calls run_descriptor_jr().
> - removed CONFIG_ARCH_IMX8 config from JR driver.
> - removed FSL_BLOB config
>
> changes since v5:
> - rebase to latest master
> - updated BIT() macro for JRDID in drivers/crypto/fsl/jr.h
> - removed auto select FSL_BLOB from CMD_BLOB config.
> - removed patch for blob key encryption key(bkek), random number generation.
> - updated patch description for improving hwrng performance in kernel.
> - removed sec_init() from kontron/sl28.
> - for LS1028A architecture, enable CAAM only for LS1028AQDS and LS1028ARDB.
>
> changes since v4:
> - rebase to latest master
> - updated caam_jr_probe() with livetree APIs.
> - imx8m: moved jr0 disable code to *-uboot.dtsi files.
>
> changes since v3:
> - rebase to latest master
> - fixed build error when new file arch/powerpc/include/asm/u-boot-ppc.h is
> included from assembly files.
> - removed arch/arm/dts/fsl-ls1028a.dtsi as it is conflicting with the series
> https://lore.kernel.org/u-boot/20211013161427.612033-1-michael@walle.cc/
>
> Gaurav Jain (13):
> crypto/fsl: Add support for CAAM Job ring driver model
> i.MX8M: crypto: updated device tree for supporting DM in SPL
> crypto/fsl: i.MX8M: Enable Job ring driver model.
> i.MX6: Enable Job ring driver model.
> i.MX7: Enable Job ring driver model.
> i.MX7ULP: Enable Job ring driver model.
> i.MX8: Add crypto node in device tree
> crypto/fsl: i.MX8: Enable Job ring driver model.
> Layerscape: Add crypto node in device tree
> Layerscape: Enable Job ring driver model.
> PPC: Add crypto node in device tree
> PPC: Enable Job ring driver model.
> update CAAM MAINTAINER
>
> Ye Li (1):
> mx6sabre: Remove unnecessary SPL configs
>
> MAINTAINERS | 6 +
> arch/arm/Kconfig | 9 +-
> arch/arm/cpu/armv7/ls102xa/cpu.c | 18 +
> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 11 +-
> arch/arm/dts/fsl-imx8dx.dtsi | 61 ++-
> arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 +-
> arch/arm/dts/fsl-imx8qm.dtsi | 61 ++-
> arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 +-
> arch/arm/dts/fsl-ls1012a.dtsi | 46 ++-
> arch/arm/dts/fsl-ls1043a.dtsi | 45 ++-
> arch/arm/dts/fsl-ls1046a.dtsi | 44 +++
> arch/arm/dts/fsl-ls1088a.dtsi | 39 ++
> arch/arm/dts/fsl-ls2080a.dtsi | 39 ++
> arch/arm/dts/fsl-lx2160a.dtsi | 41 +-
> arch/arm/dts/imx7ulp.dtsi | 24 ++
> arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 +-
> arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 +-
> arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 +-
> arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4 +
> arch/arm/dts/ls1021a.dtsi | 40 ++
> arch/arm/include/asm/arch-imx8/imx-regs.h | 5 +-
> arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 +
> arch/arm/mach-imx/cmd_dek.c | 1 +
> arch/arm/mach-imx/imx8/Kconfig | 7 +
> arch/arm/mach-imx/imx8/cpu.c | 18 +-
> arch/arm/mach-imx/imx8m/Kconfig | 13 +
> arch/arm/mach-imx/imx8m/soc.c | 11 +-
> arch/arm/mach-imx/mx6/Kconfig | 10 +
> arch/arm/mach-imx/mx6/soc.c | 13 +-
> arch/arm/mach-imx/mx7/Kconfig | 1 +
> arch/arm/mach-imx/mx7/soc.c | 12 +-
> arch/arm/mach-imx/mx7ulp/Kconfig | 2 +
> arch/arm/mach-imx/mx7ulp/soc.c | 18 +
> arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 +-
> arch/powerpc/dts/p2041si-post.dtsi | 1 +
> arch/powerpc/dts/p3041si-post.dtsi | 1 +
> arch/powerpc/dts/p4080si-post.dtsi | 1 +
> arch/powerpc/dts/p5040si-post.dtsi | 1 +
> arch/powerpc/dts/qoriq-sec4.0-0.dtsi | 74 ++++
> arch/powerpc/dts/qoriq-sec4.2-0.dtsi | 83 ++++
> arch/powerpc/dts/qoriq-sec5.2-0.dtsi | 92 +++++
> arch/powerpc/dts/t1023si-post.dtsi | 1 +
> arch/powerpc/dts/t1042si-post.dtsi | 1 +
> arch/powerpc/dts/t2080si-post.dtsi | 1 +
> arch/powerpc/dts/t4240si-post.dtsi | 1 +
> arch/powerpc/include/asm/u-boot-ppc.h | 17 +
> arch/powerpc/include/asm/u-boot.h | 1 +
> board/freescale/imx8mm_evk/spl.c | 10 +-
> board/freescale/imx8mn_evk/spl.c | 9 +-
> board/freescale/imx8mp_evk/spl.c | 14 +-
> board/freescale/imx8mq_evk/spl.c | 8 +-
> board/freescale/imx8qm_mek/spl.c | 6 +-
> board/freescale/imx8qxp_mek/spl.c | 6 +-
> board/freescale/ls1012afrdm/ls1012afrdm.c | 7 +-
> board/freescale/ls1012aqds/ls1012aqds.c | 6 +-
> board/freescale/ls1012ardb/ls1012ardb.c | 6 +-
> board/freescale/ls1021aiot/ls1021aiot.c | 6 +-
> board/freescale/ls1021aqds/ls1021aqds.c | 6 +-
> board/freescale/ls1021atsn/ls1021atsn.c | 7 +-
> board/freescale/ls1021atwr/ls1021atwr.c | 8 +-
> board/freescale/ls1028a/ls1028a.c | 6 +-
> board/freescale/ls1043ardb/ls1043ardb.c | 6 +-
> board/freescale/ls1046afrwy/ls1046afrwy.c | 7 +-
> board/freescale/ls1046aqds/ls1046aqds.c | 7 +-
> board/freescale/ls1046ardb/ls1046ardb.c | 6 +-
> board/freescale/ls1088a/ls1088a.c | 6 +-
> board/freescale/ls2080aqds/ls2080aqds.c | 6 +-
> board/freescale/ls2080ardb/ls2080ardb.c | 9 +-
> board/freescale/lx2160a/lx2160a.c | 5 -
> board/kontron/sl28/sl28.c | 3 -
> configs/P2041RDB_NAND_defconfig | 1 +
> configs/P2041RDB_SDCARD_defconfig | 1 +
> configs/P2041RDB_SPIFLASH_defconfig | 1 +
> configs/P2041RDB_defconfig | 1 +
> configs/P3041DS_NAND_defconfig | 1 +
> configs/P3041DS_SDCARD_defconfig | 1 +
> configs/P3041DS_SPIFLASH_defconfig | 1 +
> configs/P3041DS_defconfig | 1 +
> configs/P4080DS_SDCARD_defconfig | 1 +
> configs/P4080DS_SPIFLASH_defconfig | 1 +
> configs/P4080DS_defconfig | 1 +
> configs/P5040DS_NAND_defconfig | 1 +
> configs/P5040DS_SDCARD_defconfig | 1 +
> configs/P5040DS_SPIFLASH_defconfig | 1 +
> configs/P5040DS_defconfig | 1 +
> configs/T1024RDB_NAND_defconfig | 1 +
> configs/T1024RDB_SDCARD_defconfig | 1 +
> configs/T1024RDB_SPIFLASH_defconfig | 1 +
> configs/T1024RDB_defconfig | 1 +
> configs/T1042D4RDB_NAND_defconfig | 1 +
> configs/T1042D4RDB_SDCARD_defconfig | 1 +
> configs/T1042D4RDB_SPIFLASH_defconfig | 1 +
> configs/T1042D4RDB_defconfig | 1 +
> configs/T2080QDS_NAND_defconfig | 1 +
> configs/T2080QDS_SDCARD_defconfig | 1 +
> configs/T2080QDS_SPIFLASH_defconfig | 1 +
> configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 +
> configs/T2080QDS_defconfig | 1 +
> configs/T2080RDB_NAND_defconfig | 1 +
> configs/T2080RDB_SDCARD_defconfig | 1 +
> configs/T2080RDB_SPIFLASH_defconfig | 1 +
> configs/T2080RDB_defconfig | 1 +
> configs/T2080RDB_revD_NAND_defconfig | 1 +
> configs/T2080RDB_revD_SDCARD_defconfig | 1 +
> configs/T2080RDB_revD_SPIFLASH_defconfig | 1 +
> configs/T2080RDB_revD_defconfig | 1 +
> configs/T4240RDB_SDCARD_defconfig | 1 +
> configs/T4240RDB_defconfig | 1 +
> configs/ls1021aiot_qspi_defconfig | 1 +
> configs/ls1021aiot_sdcard_defconfig | 1 +
> configs/ls1021aqds_ddr4_nor_defconfig | 1 +
> configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 +
> configs/ls1021aqds_nand_defconfig | 1 +
> configs/ls1021aqds_nor_defconfig | 1 +
> configs/ls1021aqds_nor_lpuart_defconfig | 1 +
> configs/ls1021aqds_qspi_defconfig | 1 +
> configs/ls1021aqds_sdcard_ifc_defconfig | 1 +
> configs/ls1021aqds_sdcard_qspi_defconfig | 1 +
> configs/ls1021atsn_qspi_defconfig | 1 +
> configs/ls1021atsn_sdcard_defconfig | 1 +
> configs/ls1021atwr_nor_defconfig | 1 +
> configs/ls1021atwr_nor_lpuart_defconfig | 1 +
> configs/ls1021atwr_qspi_defconfig | 1 +
> ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
> configs/ls1021atwr_sdcard_ifc_defconfig | 1 +
> configs/ls1021atwr_sdcard_qspi_defconfig | 1 +
> configs/ls1043aqds_defconfig | 1 +
> configs/ls1043aqds_lpuart_defconfig | 1 +
> configs/ls1043aqds_nand_defconfig | 1 +
> configs/ls1043aqds_nor_ddr3_defconfig | 1 +
> configs/ls1043aqds_qspi_defconfig | 1 +
> configs/ls1043aqds_sdcard_ifc_defconfig | 1 +
> configs/ls1043aqds_sdcard_qspi_defconfig | 1 +
> configs/ls1043aqds_tfa_defconfig | 1 +
> configs/ls1043ardb_defconfig | 1 +
> configs/ls1043ardb_nand_defconfig | 1 +
> configs/ls1043ardb_sdcard_defconfig | 1 +
> configs/ls1043ardb_tfa_defconfig | 1 +
> configs/ls1046afrwy_tfa_defconfig | 1 +
> configs/ls1046aqds_defconfig | 1 +
> configs/ls1046aqds_lpuart_defconfig | 1 +
> configs/ls1046aqds_nand_defconfig | 1 +
> configs/ls1046aqds_qspi_defconfig | 1 +
> configs/ls1046aqds_sdcard_ifc_defconfig | 1 +
> configs/ls1046aqds_sdcard_qspi_defconfig | 1 +
> configs/ls1046aqds_tfa_defconfig | 1 +
> configs/ls1046ardb_emmc_defconfig | 1 +
> configs/ls1046ardb_qspi_defconfig | 1 +
> configs/ls1046ardb_qspi_spl_defconfig | 1 +
> configs/ls1046ardb_sdcard_defconfig | 1 +
> configs/ls1046ardb_tfa_defconfig | 1 +
> configs/mx6sabreauto_defconfig | 2 -
> configs/mx6sabresd_defconfig | 4 -
> drivers/crypto/fsl/Kconfig | 3 +-
> drivers/crypto/fsl/jr.c | 374 ++++++++++++------
> drivers/crypto/fsl/jr.h | 31 +-
> include/fsl_sec.h | 12 +-
> scripts/config_whitelist.txt | 1 +
> 158 files changed, 1432 insertions(+), 255 deletions(-) create mode 100644
> arch/powerpc/dts/qoriq-sec4.0-0.dtsi
> create mode 100644 arch/powerpc/dts/qoriq-sec4.2-0.dtsi
> create mode 100644 arch/powerpc/dts/qoriq-sec5.2-0.dtsi
> create mode 100644 arch/powerpc/include/asm/u-boot-ppc.h
>
> --
> 2.17.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL
2022-01-12 13:31 ` [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
@ 2022-01-31 21:45 ` ZHIZHIKIN Andrey
2022-01-31 22:02 ` Michael Walle
2022-02-03 5:27 ` [EXT] " Gaurav Jain
0 siblings, 2 replies; 23+ messages in thread
From: ZHIZHIKIN Andrey @ 2022-01-31 21:45 UTC (permalink / raw)
To: Gaurav Jain, u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean
Hello Gaurav,
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Gaurav Jain
> Sent: Wednesday, January 12, 2022 2:31 PM
> To: u-boot@lists.denx.de
> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan
> <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Michael Walle
> <michael@walle.cc>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>;
> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> <franck.lenormand@nxp.com>; Silvano Di Ninno <silvano.dininno@nxp.com>; Sahil
> malhotra <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> Sethi <V.Sethi@nxp.com>; NXP i . MX U-Boot Team <uboot-imx@nxp.com>; Shengzhou
> Liu <Shengzhou.Liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat
> <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim
> Khan <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Tang Yuantian <andy.tang@nxp.com>; Adrian Alonso
> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>; Gaurav Jain
> <gaurav.jain@nxp.com>
> Subject: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM
> in SPL
>
> disabled use of JR0 in SPL and uboot, as JR0 is reserved
> for secure boot.
I'd like to return the original question here, which was not completely clarified
during previous reviews: where does the reservation restriction is coming from?
BootROM does reserve the JR0 and JR1, which are later released by ATF. NXP downstream
ATF keeps the JR0 reserved, but upstream ATF does release *all* JRs to NS World.
If this reservation is taken like the patch proposes and U-Boot is built with upstream
ATF - this would eventually lead to the situation where the HW configuration is not
aligned with what DTB indicates.
Please note, that recent OP-TEE release has also re-mapped the JR it uses from JR0 to
JR2, which can also lead to usage of the JR which is already taken by OP-TEE. There is
an ongoing PR in OP-TEE to disable JR nodes via DT overlay for Linux [1], but I'm not
sure if the same applies to U-Boot as well.
>
> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 ++++++++++++++++++-
> arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++++++++++++++++++-
> arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 ++++++++++++++++++-
> arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4 ++++
> 4 files changed, 58 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-
> boot.dtsi
> index 6b459831e7..e5682ca165 100644
> --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2019 NXP
> + * Copyright 2019, 2021 NXP
> */
>
> #include "imx8mm-u-boot.dtsi"
> @@ -68,6 +68,23 @@
> u-boot,dm-spl;
> };
>
> +&crypto {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr0 {
> + u-boot,dm-spl;
> + status = "disabled";
> +};
> +
> +&sec_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr2 {
> + u-boot,dm-spl;
> +};
> +
> &usdhc1 {
> u-boot,dm-spl;
> };
> diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-
> evk-u-boot.dtsi
> index 1d3844437d..d8df863083 100644
> --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2019 NXP
> + * Copyright 2019, 2021 NXP
> */
>
> / {
> @@ -104,6 +104,23 @@
> u-boot,dm-spl;
> };
>
> +&crypto {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr0 {
> + u-boot,dm-spl;
> + status = "disabled";
> +};
> +
> +&sec_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr2 {
> + u-boot,dm-spl;
> +};
> +
> &usdhc1 {
> u-boot,dm-spl;
> };
> diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-
> boot.dtsi
> index ab849ebaac..f3f83ba303 100644
> --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2019 NXP
> + * Copyright 2019, 2021 NXP
> */
>
> #include "imx8mp-u-boot.dtsi"
> @@ -67,6 +67,23 @@
> u-boot,dm-spl;
> };
>
> +&crypto {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr0 {
> + u-boot,dm-spl;
> + status = "disabled";
> +};
> +
> +&sec_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr2 {
> + u-boot,dm-spl;
> +};
> +
> &i2c1 {
> u-boot,dm-spl;
> };
> diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-
> boot.dtsi
> index 6f9c81462e..8f1f942215 100644
> --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
> @@ -10,3 +10,7 @@
> sd-uhs-sdr104;
> sd-uhs-ddr50;
> };
> +
> +&sec_jr0 {
> + status = "disabled";
> +};
> --
> 2.17.1
Link: [1]: https://github.com/OP-TEE/optee_os/pull/5143
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL
2022-01-31 21:45 ` ZHIZHIKIN Andrey
@ 2022-01-31 22:02 ` Michael Walle
2022-02-03 5:27 ` [EXT] " Gaurav Jain
1 sibling, 0 replies; 23+ messages in thread
From: Michael Walle @ 2022-01-31 22:02 UTC (permalink / raw)
To: ZHIZHIKIN Andrey
Cc: Gaurav Jain, u-boot, Stefano Babic, Fabio Estevam, Peng Fan,
Simon Glass, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean
Hi,
Am 2022-01-31 22:45, schrieb ZHIZHIKIN Andrey:
>> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Gaurav Jain
>> Sent: Wednesday, January 12, 2022 2:31 PM
>> To: u-boot@lists.denx.de
>> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
>> <festevam@gmail.com>; Peng Fan
>> <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Michael Walle
>> <michael@walle.cc>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
>> <ye.li@nxp.com>;
>> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck
>> Lenormand
>> <franck.lenormand@nxp.com>; Silvano Di Ninno
>> <silvano.dininno@nxp.com>; Sahil
>> malhotra <sahil.malhotra@nxp.com>; Pankaj Gupta
>> <pankaj.gupta@nxp.com>; Varun
>> Sethi <V.Sethi@nxp.com>; NXP i . MX U-Boot Team <uboot-imx@nxp.com>;
>> Shengzhou
>> Liu <Shengzhou.Liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
>> Bhagat
>> <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
>> <meenakshi.aggarwal@nxp.com>; Wasim
>> Khan <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
>> Kumar
>> <pramod.kumar_1@nxp.com>; Tang Yuantian <andy.tang@nxp.com>; Adrian
>> Alonso
>> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>; Gaurav
>> Jain
>> <gaurav.jain@nxp.com>
>> Subject: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for
>> supporting DM
>> in SPL
>>
>> disabled use of JR0 in SPL and uboot, as JR0 is reserved
>> for secure boot.
>
> I'd like to return the original question here, which was not
> completely clarified
> during previous reviews: where does the reservation restriction is
> coming from?
>
> BootROM does reserve the JR0 and JR1, which are later released by ATF.
> NXP downstream
> ATF keeps the JR0 reserved, but upstream ATF does release *all* JRs to
> NS World.
>
> If this reservation is taken like the patch proposes and U-Boot is
> built with upstream
> ATF - this would eventually lead to the situation where the HW
> configuration is not
> aligned with what DTB indicates.
>
> Please note, that recent OP-TEE release has also re-mapped the JR it
> uses from JR0 to
> JR2, which can also lead to usage of the JR which is already taken by
> OP-TEE. There is
> an ongoing PR in OP-TEE to disable JR nodes via DT overlay for Linux
> [1], but I'm not
> sure if the same applies to U-Boot as well.
From the referenced PR:
| On imx8m platforms, OP-TEE has no direct access to the Linux device
| tree. The OP-TEE CAAM driver must disable the secure JR thought the
| device tree overlay.
Why is that the case? That "we create some kind of overlay and
hope it will fit" sounds very fragile to me. Who is applying this
overlay? Will it be applied for u-boot and linux or just for linux?
-michael
[1] https://github.com/OP-TEE/optee_os/pull/5143
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [EXT] RE: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL
2022-01-31 21:45 ` ZHIZHIKIN Andrey
2022-01-31 22:02 ` Michael Walle
@ 2022-02-03 5:27 ` Gaurav Jain
2022-02-11 9:48 ` Gaurav Jain
1 sibling, 1 reply; 23+ messages in thread
From: Gaurav Jain @ 2022-02-03 5:27 UTC (permalink / raw)
To: ZHIZHIKIN Andrey, u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil Malhotra, Pankaj Gupta,
Varun Sethi, dl-uboot-imx, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Andy Tang, Adrian Alonso, Vladimir Oltean
Hello Andrey
> -----Original Message-----
> From: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>
> Sent: Tuesday, February 1, 2022 3:15 AM
> To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>;
> Peng Fan <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Michael
> Walle <michael@walle.cc>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: [EXT] RE: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for
> supporting DM in SPL
>
> Caution: EXT Email
>
> Hello Gaurav,
>
> > -----Original Message-----
> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Gaurav Jain
> > Sent: Wednesday, January 12, 2022 2:31 PM
> > To: u-boot@lists.denx.de
> > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> > <sjg@chromium.org>; Michael Walle <michael@walle.cc>; Priyanka Jain
> > <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> > <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> > <franck.lenormand@nxp.com>; Silvano Di Ninno
> > <silvano.dininno@nxp.com>; Sahil malhotra <sahil.malhotra@nxp.com>;
> > Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> > NXP i . MX U-Boot Team <uboot-imx@nxp.com>; Shengzhou Liu
> > <Shengzhou.Liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> Alison
> > Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>;
> > Tang Yuantian <andy.tang@nxp.com>; Adrian Alonso
> > <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>; Gaurav
> > Jain <gaurav.jain@nxp.com>
> > Subject: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for
> > supporting DM in SPL
> >
> > disabled use of JR0 in SPL and uboot, as JR0 is reserved for secure
> > boot.
>
> I'd like to return the original question here, which was not completely clarified
> during previous reviews: where does the reservation restriction is coming from?
As mentioned earlier JR0 is being used by high assurance boot (HAB). This prevents JR0 being used by any other software layer.
>
> BootROM does reserve the JR0 and JR1, which are later released by ATF. NXP
> downstream ATF keeps the JR0 reserved, but upstream ATF does release *all*
> JRs to NS World.
>
> If this reservation is taken like the patch proposes and U-Boot is built with
> upstream ATF - this would eventually lead to the situation where the HW
> configuration is not aligned with what DTB indicates.
I agree with you, we will address this in the upstream ATF code base as well.
>
> Please note, that recent OP-TEE release has also re-mapped the JR it uses from
> JR0 to JR2, which can also lead to usage of the JR which is already taken by OP-
> TEE. There is an ongoing PR in OP-TEE to disable JR nodes via DT overlay for
> Linux [1], but I'm not sure if the same applies to U-Boot as well.
Yes, Sahil would be addressing this issue in the next version of his patch set.
Regards
Gaurav Jain
>
> >
> > Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> > Reviewed-by: Ye Li <ye.li@nxp.com>
> > ---
> > arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 ++++++++++++++++++-
> > arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++++++++++++++++++-
> > arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 ++++++++++++++++++-
> > arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4 ++++
> > 4 files changed, 58 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > b/arch/arm/dts/imx8mm-evk-u- boot.dtsi index 6b459831e7..e5682ca165
> > 100644
> > --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > @@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> > - * Copyright 2019 NXP
> > + * Copyright 2019, 2021 NXP
> > */
> >
> > #include "imx8mm-u-boot.dtsi"
> > @@ -68,6 +68,23 @@
> > u-boot,dm-spl;
> > };
> >
> > +&crypto {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&sec_jr0 {
> > + u-boot,dm-spl;
> > + status = "disabled";
> > +};
> > +
> > +&sec_jr1 {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&sec_jr2 {
> > + u-boot,dm-spl;
> > +};
> > +
> > &usdhc1 {
> > u-boot,dm-spl;
> > };
> > diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > b/arch/arm/dts/imx8mn-ddr4- evk-u-boot.dtsi index
> > 1d3844437d..d8df863083 100644
> > --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > @@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> > - * Copyright 2019 NXP
> > + * Copyright 2019, 2021 NXP
> > */
> >
> > / {
> > @@ -104,6 +104,23 @@
> > u-boot,dm-spl;
> > };
> >
> > +&crypto {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&sec_jr0 {
> > + u-boot,dm-spl;
> > + status = "disabled";
> > +};
> > +
> > +&sec_jr1 {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&sec_jr2 {
> > + u-boot,dm-spl;
> > +};
> > +
> > &usdhc1 {
> > u-boot,dm-spl;
> > };
> > diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> > b/arch/arm/dts/imx8mp-evk-u- boot.dtsi index ab849ebaac..f3f83ba303
> > 100644
> > --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> > +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> > @@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> > - * Copyright 2019 NXP
> > + * Copyright 2019, 2021 NXP
> > */
> >
> > #include "imx8mp-u-boot.dtsi"
> > @@ -67,6 +67,23 @@
> > u-boot,dm-spl;
> > };
> >
> > +&crypto {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&sec_jr0 {
> > + u-boot,dm-spl;
> > + status = "disabled";
> > +};
> > +
> > +&sec_jr1 {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&sec_jr2 {
> > + u-boot,dm-spl;
> > +};
> > +
> > &i2c1 {
> > u-boot,dm-spl;
> > };
> > diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
> > b/arch/arm/dts/imx8mq-evk-u- boot.dtsi index 6f9c81462e..8f1f942215
> > 100644
> > --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
> > +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
> > @@ -10,3 +10,7 @@
> > sd-uhs-sdr104;
> > sd-uhs-ddr50;
> > };
> > +
> > +&sec_jr0 {
> > + status = "disabled";
> > +};
> > --
> > 2.17.1
>
> Link: [1]:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.co
> m%2FOP-
> TEE%2Foptee_os%2Fpull%2F5143&data=04%7C01%7Cgaurav.jain%40nxp.
> com%7C86913a749ce04232bd0e08d9e502efa1%7C686ea1d3bc2b4c6fa92cd99
> c5c301635%7C0%7C0%7C637792623039930395%7CUnknown%7CTWFpbGZsb3
> d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7C3000&sdata=nTN7YN9G2vNgyhwnj6JrT8BdtGQn%2F0yILgpGdNg3mK
> g%3D&reserved=0
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [EXT] RE: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL
2022-02-03 5:27 ` [EXT] " Gaurav Jain
@ 2022-02-11 9:48 ` Gaurav Jain
2022-02-11 16:26 ` ZHIZHIKIN Andrey
0 siblings, 1 reply; 23+ messages in thread
From: Gaurav Jain @ 2022-02-11 9:48 UTC (permalink / raw)
To: ZHIZHIKIN Andrey, u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil Malhotra, Pankaj Gupta,
Varun Sethi, dl-uboot-imx, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Andy Tang, Adrian Alonso, Vladimir Oltean
Hello Andrey
I responded to your comments on this patch.
If you are good, can this patch series merged?
Regards
Gaurav Jain
> -----Original Message-----
> From: Gaurav Jain
> Sent: Thursday, February 3, 2022 10:58 AM
> To: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>; u-
> boot@lists.denx.de
> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>;
> Peng Fan <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Michael
> Walle <michael@walle.cc>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: RE: [EXT] RE: [PATCH v10 02/14] i.MX8M: crypto: updated device tree
> for supporting DM in SPL
>
> Hello Andrey
>
> > -----Original Message-----
> > From: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>
> > Sent: Tuesday, February 1, 2022 3:15 AM
> > To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
> > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> > <sjg@chromium.org>; Michael Walle <michael@walle.cc>; Priyanka Jain
> > <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> > <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> > <franck.lenormand@nxp.com>; Silvano Di Ninno
> > <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> > Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> > dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
> > <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> Alison
> > Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>;
> > Andy Tang <andy.tang@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> > Vladimir Oltean <olteanv@gmail.com>
> > Subject: [EXT] RE: [PATCH v10 02/14] i.MX8M: crypto: updated device
> > tree for supporting DM in SPL
> >
> > Caution: EXT Email
> >
> > Hello Gaurav,
> >
> > > -----Original Message-----
> > > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Gaurav Jain
> > > Sent: Wednesday, January 12, 2022 2:31 PM
> > > To: u-boot@lists.denx.de
> > > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> > > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> > > <sjg@chromium.org>; Michael Walle <michael@walle.cc>; Priyanka Jain
> > > <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> > > <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> > > <franck.lenormand@nxp.com>; Silvano Di Ninno
> > > <silvano.dininno@nxp.com>; Sahil malhotra <sahil.malhotra@nxp.com>;
> > > Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> > > NXP i . MX U-Boot Team <uboot-imx@nxp.com>; Shengzhou Liu
> > > <Shengzhou.Liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> > Alison
> > > Wang <alison.wang@nxp.com>; Pramod Kumar
> > <pramod.kumar_1@nxp.com>;
> > > Tang Yuantian <andy.tang@nxp.com>; Adrian Alonso
> > > <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>; Gaurav
> > > Jain <gaurav.jain@nxp.com>
> > > Subject: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for
> > > supporting DM in SPL
> > >
> > > disabled use of JR0 in SPL and uboot, as JR0 is reserved for secure
> > > boot.
> >
> > I'd like to return the original question here, which was not
> > completely clarified during previous reviews: where does the reservation
> restriction is coming from?
>
> As mentioned earlier JR0 is being used by high assurance boot (HAB). This
> prevents JR0 being used by any other software layer.
> >
> > BootROM does reserve the JR0 and JR1, which are later released by ATF.
> > NXP downstream ATF keeps the JR0 reserved, but upstream ATF does
> > release *all* JRs to NS World.
> >
> > If this reservation is taken like the patch proposes and U-Boot is
> > built with upstream ATF - this would eventually lead to the situation
> > where the HW configuration is not aligned with what DTB indicates.
>
> I agree with you, we will address this in the upstream ATF code base as well.
> >
> > Please note, that recent OP-TEE release has also re-mapped the JR it
> > uses from
> > JR0 to JR2, which can also lead to usage of the JR which is already
> > taken by OP- TEE. There is an ongoing PR in OP-TEE to disable JR nodes
> > via DT overlay for Linux [1], but I'm not sure if the same applies to U-Boot as
> well.
>
> Yes, Sahil would be addressing this issue in the next version of his patch set.
>
> Regards
> Gaurav Jain
> >
> > >
> > > Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> > > Reviewed-by: Ye Li <ye.li@nxp.com>
> > > ---
> > > arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 ++++++++++++++++++-
> > > arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++++++++++++++++++-
> > > arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 ++++++++++++++++++-
> > > arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4 ++++
> > > 4 files changed, 58 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > > b/arch/arm/dts/imx8mm-evk-u- boot.dtsi index 6b459831e7..e5682ca165
> > > 100644
> > > --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > > +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > > @@ -1,6 +1,6 @@
> > > // SPDX-License-Identifier: GPL-2.0+
> > > /*
> > > - * Copyright 2019 NXP
> > > + * Copyright 2019, 2021 NXP
> > > */
> > >
> > > #include "imx8mm-u-boot.dtsi"
> > > @@ -68,6 +68,23 @@
> > > u-boot,dm-spl;
> > > };
> > >
> > > +&crypto {
> > > + u-boot,dm-spl;
> > > +};
> > > +
> > > +&sec_jr0 {
> > > + u-boot,dm-spl;
> > > + status = "disabled";
> > > +};
> > > +
> > > +&sec_jr1 {
> > > + u-boot,dm-spl;
> > > +};
> > > +
> > > +&sec_jr2 {
> > > + u-boot,dm-spl;
> > > +};
> > > +
> > > &usdhc1 {
> > > u-boot,dm-spl;
> > > };
> > > diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > > b/arch/arm/dts/imx8mn-ddr4- evk-u-boot.dtsi index
> > > 1d3844437d..d8df863083 100644
> > > --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > > +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > > @@ -1,6 +1,6 @@
> > > // SPDX-License-Identifier: GPL-2.0+
> > > /*
> > > - * Copyright 2019 NXP
> > > + * Copyright 2019, 2021 NXP
> > > */
> > >
> > > / {
> > > @@ -104,6 +104,23 @@
> > > u-boot,dm-spl;
> > > };
> > >
> > > +&crypto {
> > > + u-boot,dm-spl;
> > > +};
> > > +
> > > +&sec_jr0 {
> > > + u-boot,dm-spl;
> > > + status = "disabled";
> > > +};
> > > +
> > > +&sec_jr1 {
> > > + u-boot,dm-spl;
> > > +};
> > > +
> > > +&sec_jr2 {
> > > + u-boot,dm-spl;
> > > +};
> > > +
> > > &usdhc1 {
> > > u-boot,dm-spl;
> > > };
> > > diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> > > b/arch/arm/dts/imx8mp-evk-u- boot.dtsi index ab849ebaac..f3f83ba303
> > > 100644
> > > --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> > > +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> > > @@ -1,6 +1,6 @@
> > > // SPDX-License-Identifier: GPL-2.0+
> > > /*
> > > - * Copyright 2019 NXP
> > > + * Copyright 2019, 2021 NXP
> > > */
> > >
> > > #include "imx8mp-u-boot.dtsi"
> > > @@ -67,6 +67,23 @@
> > > u-boot,dm-spl;
> > > };
> > >
> > > +&crypto {
> > > + u-boot,dm-spl;
> > > +};
> > > +
> > > +&sec_jr0 {
> > > + u-boot,dm-spl;
> > > + status = "disabled";
> > > +};
> > > +
> > > +&sec_jr1 {
> > > + u-boot,dm-spl;
> > > +};
> > > +
> > > +&sec_jr2 {
> > > + u-boot,dm-spl;
> > > +};
> > > +
> > > &i2c1 {
> > > u-boot,dm-spl;
> > > };
> > > diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
> > > b/arch/arm/dts/imx8mq-evk-u- boot.dtsi index 6f9c81462e..8f1f942215
> > > 100644
> > > --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
> > > +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
> > > @@ -10,3 +10,7 @@
> > > sd-uhs-sdr104;
> > > sd-uhs-ddr50;
> > > };
> > > +
> > > +&sec_jr0 {
> > > + status = "disabled";
> > > +};
> > > --
> > > 2.17.1
> >
> > Link: [1]:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> > ub.co
> > m%2FOP-
> >
> TEE%2Foptee_os%2Fpull%2F5143&data=04%7C01%7Cgaurav.jain%40nxp.
> >
> com%7C86913a749ce04232bd0e08d9e502efa1%7C686ea1d3bc2b4c6fa92cd99
> >
> c5c301635%7C0%7C0%7C637792623039930395%7CUnknown%7CTWFpbGZsb3
> >
> d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> >
> D%7C3000&sdata=nTN7YN9G2vNgyhwnj6JrT8BdtGQn%2F0yILgpGdNg3mK
> > g%3D&reserved=0
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [EXT] RE: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL
2022-02-11 9:48 ` Gaurav Jain
@ 2022-02-11 16:26 ` ZHIZHIKIN Andrey
0 siblings, 0 replies; 23+ messages in thread
From: ZHIZHIKIN Andrey @ 2022-02-11 16:26 UTC (permalink / raw)
To: Gaurav Jain, u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil Malhotra, Pankaj Gupta,
Varun Sethi, dl-uboot-imx, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Andy Tang, Adrian Alonso, Vladimir Oltean,
Rouven Czerwinski
Hello Gaurav,
Sorry, I somehow missed you last reply here.
Cc: Rouven
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Gaurav Jain
> Sent: Friday, February 11, 2022 10:48 AM
> To: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>; u-
> boot@lists.denx.de
> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan
> <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Michael Walle
> <michael@walle.cc>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>;
> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> <franck.lenormand@nxp.com>; Silvano Di Ninno <silvano.dininno@nxp.com>; Sahil
> Malhotra <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> Sethi <V.Sethi@nxp.com>; dl-uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
> <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat
> <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim
> Khan <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>; Adrian Alonso
> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: RE: [EXT] RE: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for
> supporting DM in SPL
>
> Hello Andrey
>
> I responded to your comments on this patch.
> If you are good, can this patch series merged?
>
> Regards
> Gaurav Jain
>
> > -----Original Message-----
> > From: Gaurav Jain
> > Sent: Thursday, February 3, 2022 10:58 AM
> > To: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>; u-
> > boot@lists.denx.de
> > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>;
> > Peng Fan <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Michael
> > Walle <michael@walle.cc>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> > <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> > <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> > Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> > Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> > uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> > Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> > Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> > <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> > Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> > Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> > Subject: RE: [EXT] RE: [PATCH v10 02/14] i.MX8M: crypto: updated device tree
> > for supporting DM in SPL
> >
> > Hello Andrey
> >
> > > -----Original Message-----
> > > From: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>
> > > Sent: Tuesday, February 1, 2022 3:15 AM
> > > To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
> > > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> > > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> > > <sjg@chromium.org>; Michael Walle <michael@walle.cc>; Priyanka Jain
> > > <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> > > <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> > > <franck.lenormand@nxp.com>; Silvano Di Ninno
> > > <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> > > Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> > > dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
> > > <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> > Alison
> > > Wang <alison.wang@nxp.com>; Pramod Kumar
> > <pramod.kumar_1@nxp.com>;
> > > Andy Tang <andy.tang@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> > > Vladimir Oltean <olteanv@gmail.com>
> > > Subject: [EXT] RE: [PATCH v10 02/14] i.MX8M: crypto: updated device
> > > tree for supporting DM in SPL
> > >
> > > Caution: EXT Email
> > >
> > > Hello Gaurav,
> > >
> > > > -----Original Message-----
> > > > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Gaurav Jain
> > > > Sent: Wednesday, January 12, 2022 2:31 PM
> > > > To: u-boot@lists.denx.de
> > > > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> > > > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> > > > <sjg@chromium.org>; Michael Walle <michael@walle.cc>; Priyanka Jain
> > > > <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> > > > <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> > > > <franck.lenormand@nxp.com>; Silvano Di Ninno
> > > > <silvano.dininno@nxp.com>; Sahil malhotra <sahil.malhotra@nxp.com>;
> > > > Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> > > > NXP i . MX U-Boot Team <uboot-imx@nxp.com>; Shengzhou Liu
> > > > <Shengzhou.Liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > > > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > > > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> > > Alison
> > > > Wang <alison.wang@nxp.com>; Pramod Kumar
> > > <pramod.kumar_1@nxp.com>;
> > > > Tang Yuantian <andy.tang@nxp.com>; Adrian Alonso
> > > > <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>; Gaurav
> > > > Jain <gaurav.jain@nxp.com>
> > > > Subject: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for
> > > > supporting DM in SPL
> > > >
> > > > disabled use of JR0 in SPL and uboot, as JR0 is reserved for secure
> > > > boot.
> > >
> > > I'd like to return the original question here, which was not
> > > completely clarified during previous reviews: where does the reservation
> > restriction is coming from?
> >
> > As mentioned earlier JR0 is being used by high assurance boot (HAB). This
> > prevents JR0 being used by any other software layer.
From what I understood reading AN4581 and companion AN12056, HAB requires
JR only in case when Encrypted Boot is performed. For image signature
verification it is not required, hence this reservation does sound a bit
artificial to me. Please correct me here if my understanding is not complete,
I was not able to get this information from all the answers you provided
before on the purpose of this reservation.
This fact, coupled with the one that upstream TF-A does release all JR to
NS-World, suggests that the reservation is not actually necessary, and
moreover - it will not reflect what the HW configuration it will have in
all combinations of BootROM->SPL->TF-A->(potentially OP-TEE)->Kernel.
Please note, that in case of downstream NXP TF-A is used here - this
reservation is rather valid, but it leads to "vendor locking" of
upstream U-Boot as it cannot be expected that all board/device vendors
are using downstream TF-A.
You do suggest below that this TF-A "mismatch" will be addressed in
upstream, but until this is done it is not reasonable to imply this
reservation IMHO.
As a side note: I had a patch series in the Kernel that performs
exactly the same reservation, but had to hold it back exactly because
of the reason I stated above: upstream TF-A does behave different from
downstream NXP one, hence booting Kernel with either one of those would
have different results with respect to JR0 reservation, see [1]. So you
can say that I'm and "interested party" here, since depending on how this
is solved in the boot chain would influence my next version of the patch
set to the Kernel.
> > >
> > > BootROM does reserve the JR0 and JR1, which are later released by ATF.
> > > NXP downstream ATF keeps the JR0 reserved, but upstream ATF does
> > > release *all* JRs to NS World.
> > >
> > > If this reservation is taken like the patch proposes and U-Boot is
> > > built with upstream ATF - this would eventually lead to the situation
> > > where the HW configuration is not aligned with what DTB indicates.
> >
> > I agree with you, we will address this in the upstream ATF code base as well.
That would be really great! I would personally consider this as a first
step before at least this reservation is performed. This would ensure the
consistency of HW description that DT provides.
> > >
> > > Please note, that recent OP-TEE release has also re-mapped the JR it
> > > uses from
> > > JR0 to JR2, which can also lead to usage of the JR which is already
> > > taken by OP- TEE. There is an ongoing PR in OP-TEE to disable JR nodes
> > > via DT overlay for Linux [1], but I'm not sure if the same applies to U-Boot
> as
> > well.
> >
> > Yes, Sahil would be addressing this issue in the next version of his patch
> set.
Michael had a share of comments regarding the approach chosen for LS family,
and I think once that is solved - same solution can be applied to imx8 family.
> >
> > Regards
> > Gaurav Jain
> > >
Link: [1]: https://lore.kernel.org/lkml/AM6PR06MB4691D4FCA4D82284E70A9F53A64E9@AM6PR06MB4691.eurprd06.prod.outlook.com/
-- andrey
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2022-02-11 16:26 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 01/14] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
2022-01-12 20:03 ` Simon Glass
2022-01-12 13:31 ` [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
2022-01-31 21:45 ` ZHIZHIKIN Andrey
2022-01-31 22:02 ` Michael Walle
2022-02-03 5:27 ` [EXT] " Gaurav Jain
2022-02-11 9:48 ` Gaurav Jain
2022-02-11 16:26 ` ZHIZHIKIN Andrey
2022-01-12 13:31 ` [PATCH v10 03/14] crypto/fsl: i.MX8M: Enable Job ring driver model Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 04/14] mx6sabre: Remove unnecessary SPL configs Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 05/14] i.MX6: Enable Job ring driver model Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 06/14] i.MX7: " Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 07/14] i.MX7ULP: " Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 08/14] i.MX8: Add crypto node in device tree Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 09/14] crypto/fsl: i.MX8: Enable Job ring driver model Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 10/14] Layerscape: Add crypto node in device tree Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 11/14] Layerscape: Enable Job ring driver model Gaurav Jain
2022-01-12 15:50 ` Michael Walle
2022-01-12 13:31 ` [PATCH v10 12/14] PPC: Add crypto node in device tree Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 13/14] PPC: Enable Job ring driver model Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 14/14] update CAAM MAINTAINER Gaurav Jain
2022-01-31 6:01 ` [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
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