From: Stefan Roese <sr@denx.de>
To: "Marek Behún" <kabel@kernel.org>
Cc: u-boot@lists.denx.de, "Pali Rohár" <pali@kernel.org>,
"Marek Behún" <marek.behun@nic.cz>
Subject: Re: [PATCH u-boot-marvell 02/10] arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c
Date: Fri, 12 Nov 2021 15:01:57 +0100 [thread overview]
Message-ID: <e3f5fab4-4bfe-e91f-5846-3b6ce7be0e28@denx.de> (raw)
In-Reply-To: <20211111153549.29111-3-kabel@kernel.org>
On 11/11/21 16:35, Marek Behún wrote:
> From: Pali Rohár <pali@kernel.org>
>
> As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't
> overwrite read-only SAR PCIe registers") it is required to set Maximum Link
> Width bits of PCIe Root Port Link Capabilities Register depending of number
> of used serdes lanes. As this register is part of PCIe address space and
> not serdes address space, move it into pci_mvebu.c driver.
>
> Read number of PCIe lanes from DT propery "num-lanes" which is used also by
> other PCIe controller drivers in Linux kernel. If this property is absent.
> default to 1. This property needs to be set to 4 for every mvebu board
> which use PEX_ROOT_COMPLEX_X4. Currently in U-Boot there is no such board.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Signed-off-by: Marek Behún <marek.behun@nic.cz>
> ---
> arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 4 ----
> .../serdes/a38x/high_speed_env_spec.c | 15 ---------------
> drivers/pci/pci_mvebu.c | 18 ++++++++++++++++++
> 3 files changed, 18 insertions(+), 19 deletions(-)
I'm wondering now, if and how this works on Armada XP, which uses the
same PCIe driver but a different serdes/axp/*. Did you take this into
account?
Thanks,
Stefan
> diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
> index 64193d5288..0df898c625 100644
> --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
> +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
> @@ -6,12 +6,8 @@
> #ifndef _CTRL_PEX_H
> #define _CTRL_PEX_H
>
> -#include <pci.h>
> #include "high_speed_env_spec.h"
>
> -/* Direct access to PEX0 Root Port's PCIe Capability structure */
> -#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60)
> -
> /* SOC_CONTROL_REG1 fields */
> #define PCIE0_ENABLE_OFFS 0
> #define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
> diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
> index d2bc3ab25c..ef4b89c96a 100644
> --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
> +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
> @@ -1720,21 +1720,6 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
> else
> reg_data &= ~0x4000;
> reg_write(SOC_CONTROL_REG1, reg_data);
> -
> - /*
> - * Set Maximum Link Width to X1 or X4 in Root
> - * Port's PCIe Link Capability register.
> - * This register is read-only but if is not set
> - * correctly then access to PCI config space of
> - * endpoint card behind this Root Port does not
> - * work.
> - */
> - reg_data = reg_read(PEX0_RP_PCIE_CFG_OFFSET +
> - PCI_EXP_LNKCAP);
> - reg_data &= ~PCI_EXP_LNKCAP_MLW;
> - reg_data |= (is_pex_by1 ? 1 : 4) << 4;
> - reg_write(PEX0_RP_PCIE_CFG_OFFSET +
> - PCI_EXP_LNKCAP, reg_data);
> }
>
> CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));
> diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
> index a3364d5a59..278dc2756f 100644
> --- a/drivers/pci/pci_mvebu.c
> +++ b/drivers/pci/pci_mvebu.c
> @@ -83,6 +83,7 @@ struct mvebu_pcie {
> struct resource io;
> u32 port;
> u32 lane;
> + bool is_x4;
> int devfn;
> u32 lane_mask;
> int first_busno;
> @@ -399,6 +400,18 @@ static int mvebu_pcie_probe(struct udevice *dev)
> reg |= PCIE_CTRL_RC_MODE;
> writel(reg, pcie->base + PCIE_CTRL_OFF);
>
> + /*
> + * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link
> + * Capability register. This register is defined by PCIe specification
> + * as read-only but this mvebu controller has it as read-write and must
> + * be set to number of SerDes PCIe lanes (1 or 4). If this register is
> + * not set correctly then link with endpoint card is not established.
> + */
> + reg = readl(pcie->base + PCIE_CAPAB_OFF + PCI_EXP_LNKCAP);
> + reg &= ~PCI_EXP_LNKCAP_MLW;
> + reg |= (pcie->is_x4 ? 4 : 1) << 4;
> + writel(reg, pcie->base + PCIE_CAPAB_OFF + PCI_EXP_LNKCAP);
> +
> /*
> * Change Class Code of PCI Bridge device to PCI Bridge (0x600400)
> * because default value is Memory controller (0x508000) which
> @@ -582,6 +595,7 @@ static int mvebu_get_tgt_attr(ofnode node, int devfn,
> static int mvebu_pcie_of_to_plat(struct udevice *dev)
> {
> struct mvebu_pcie *pcie = dev_get_plat(dev);
> + u32 num_lanes = 1;
> int ret = 0;
>
> /* Get port number, lane number and memory target / attr */
> @@ -594,6 +608,10 @@ static int mvebu_pcie_of_to_plat(struct udevice *dev)
> if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
> pcie->lane = 0;
>
> + if (!ofnode_read_u32(dev_ofnode(dev), "num-lanes", &num_lanes) &&
> + num_lanes == 4)
> + pcie->is_x4 = true;
> +
> sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
>
> /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
>
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de
next prev parent reply other threads:[~2021-11-12 14:02 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-11 15:35 [PATCH u-boot-marvell 00/10] PCI mvebu and aardvark changes Marek Behún
2021-11-11 15:35 ` [PATCH u-boot-marvell 01/10] pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe() Marek Behún
2021-11-12 13:59 ` Stefan Roese
2021-11-12 15:44 ` Pali Rohár
2021-11-12 16:07 ` Stefan Roese
2021-11-18 18:06 ` Pali Rohár
2021-11-11 15:35 ` [PATCH u-boot-marvell 02/10] arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c Marek Behún
2021-11-12 14:01 ` Stefan Roese [this message]
2021-11-18 18:01 ` Pali Rohár
2021-11-19 6:55 ` Stefan Roese
2021-11-23 15:59 ` Pali Rohár
2021-11-29 7:46 ` Stefan Roese
2021-11-29 9:06 ` Pali Rohár
2021-11-29 9:22 ` Stefan Roese
2021-11-29 11:47 ` Pali Rohár
2021-11-29 12:30 ` Stefan Roese
2021-11-29 13:27 ` Pali Rohár
2021-11-29 14:28 ` Pali Rohár
2021-11-29 16:07 ` Stefan Roese
2021-11-29 17:09 ` Marek Behún
2021-12-10 11:07 ` Pali Rohár
2021-12-10 14:23 ` Pali Rohár
2021-12-13 7:36 ` Stefan Roese
2021-12-13 10:28 ` Pali Rohár
2021-11-11 15:35 ` [PATCH u-boot-marvell 03/10] pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup Marek Behún
2021-11-12 14:02 ` Stefan Roese
2021-12-21 8:22 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 04/10] pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size() Marek Behún
2021-11-12 14:03 ` Stefan Roese
2021-12-21 8:23 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 05/10] pci: pci_mvebu, pci_aardvark: Fix size of configuration cache Marek Behún
2021-11-12 14:04 ` Stefan Roese
2021-12-15 10:57 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 06/10] pci: pci_mvebu: Do not allow setting ROM BAR on PCI Bridge Marek Behún
2021-11-12 14:05 ` Stefan Roese
2021-12-15 10:57 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 07/10] pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping Marek Behún
2021-11-12 14:18 ` Stefan Roese
2021-11-18 17:46 ` Pali Rohár
2021-11-19 6:27 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 08/10] pci: pci_mvebu: Remove unused DECLARE_GLOBAL_DATA_PTR Marek Behún
2021-11-12 14:19 ` Stefan Roese
2021-12-21 8:23 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 09/10] arm: a37xx: pci: Do not allow setting ROM BAR on PCI Bridge Marek Behún
2021-11-12 14:19 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 10/10] arm: mvebu: turris_mox: Remove extra newline after module topology Marek Behún
2021-11-12 14:20 ` Stefan Roese
2021-12-21 8:23 ` Stefan Roese
2021-12-12 11:23 ` [PATCH u-boot-marvell 00/10] PCI mvebu and aardvark changes Pali Rohár
2021-12-13 7:41 ` Stefan Roese
2021-12-13 10:27 ` Pali Rohár
2021-12-15 8:10 ` Stefan Roese
2021-12-16 10:28 ` Pali Rohár
2021-12-18 13:53 ` Stefan Roese
2021-12-20 13:30 ` Pali Rohár
2021-12-21 8:19 ` Stefan Roese
2021-12-21 10:57 ` Pali Rohár
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