From: Stefan Roese <sr@denx.de>
To: "Marek Behún" <kabel@kernel.org>
Cc: u-boot@lists.denx.de, "Pali Rohár" <pali@kernel.org>,
"Marek Behún" <marek.behun@nic.cz>
Subject: Re: [PATCH u-boot-marvell 03/10] pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup
Date: Tue, 21 Dec 2021 09:22:51 +0100 [thread overview]
Message-ID: <0b0d4f31-db5c-cef9-df00-1c5b71682fcd@denx.de> (raw)
In-Reply-To: <20211111153549.29111-4-kabel@kernel.org>
On 11/11/21 16:35, Marek Behún wrote:
> From: Pali Rohár <pali@kernel.org>
>
> Function mvebu_pcie_setup_wins() sets up all other BARs, so move setup of
> BAR[0] to this function to have common code at one place.
>
> In the past, commit 193a1e9f196b ("pci: pci_mvebu: set BAR0 after memory
> space is set") moved setup of BAR[0] to another location, due to ath10k
> not working in kernel, but the reason why was unknown, but it seems to
> work now, and we think the issue then was cause by the PCIe Root Port
> presenting itself as a Memory Controller and therefore U-Boot's code
> have overwritten the BAR. Since the driver now ignores any write
> operations to PCIe Root Port BARs, this should not be an issue anymore.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Signed-off-by: Marek Behún <marek.behun@nic.cz>
Applied to u-boot-marvell/next
Thanks,
Stefan
> ---
> drivers/pci/pci_mvebu.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
> index 278dc2756f..97c7b5604f 100644
> --- a/drivers/pci/pci_mvebu.c
> +++ b/drivers/pci/pci_mvebu.c
> @@ -335,7 +335,9 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
>
> /*
> * Setup PCIE BARs and Address Decode Wins:
> - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
> + * BAR[0] -> internal registers
> + * BAR[1] -> covers all DRAM banks
> + * BAR[2] -> disabled
> * WIN[0-3] -> DRAM bank[0-3]
> */
> static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
> @@ -386,6 +388,10 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
> writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
> writel(((size - 1) & 0xffff0000) | 0x1,
> pcie->base + PCIE_BAR_CTRL_OFF(1));
> +
> + /* Setup BAR[0] to internal registers. */
> + writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
> + writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
> }
>
> static int mvebu_pcie_probe(struct udevice *dev)
> @@ -501,10 +507,6 @@ static int mvebu_pcie_probe(struct udevice *dev)
> pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO);
> hose->region_count = 3;
>
> - /* Set BAR0 to internal registers */
> - writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
> - writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
> -
> /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
> pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
> PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
>
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de
next prev parent reply other threads:[~2021-12-21 8:23 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-11 15:35 [PATCH u-boot-marvell 00/10] PCI mvebu and aardvark changes Marek Behún
2021-11-11 15:35 ` [PATCH u-boot-marvell 01/10] pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe() Marek Behún
2021-11-12 13:59 ` Stefan Roese
2021-11-12 15:44 ` Pali Rohár
2021-11-12 16:07 ` Stefan Roese
2021-11-18 18:06 ` Pali Rohár
2021-11-11 15:35 ` [PATCH u-boot-marvell 02/10] arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c Marek Behún
2021-11-12 14:01 ` Stefan Roese
2021-11-18 18:01 ` Pali Rohár
2021-11-19 6:55 ` Stefan Roese
2021-11-23 15:59 ` Pali Rohár
2021-11-29 7:46 ` Stefan Roese
2021-11-29 9:06 ` Pali Rohár
2021-11-29 9:22 ` Stefan Roese
2021-11-29 11:47 ` Pali Rohár
2021-11-29 12:30 ` Stefan Roese
2021-11-29 13:27 ` Pali Rohár
2021-11-29 14:28 ` Pali Rohár
2021-11-29 16:07 ` Stefan Roese
2021-11-29 17:09 ` Marek Behún
2021-12-10 11:07 ` Pali Rohár
2021-12-10 14:23 ` Pali Rohár
2021-12-13 7:36 ` Stefan Roese
2021-12-13 10:28 ` Pali Rohár
2021-11-11 15:35 ` [PATCH u-boot-marvell 03/10] pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup Marek Behún
2021-11-12 14:02 ` Stefan Roese
2021-12-21 8:22 ` Stefan Roese [this message]
2021-11-11 15:35 ` [PATCH u-boot-marvell 04/10] pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size() Marek Behún
2021-11-12 14:03 ` Stefan Roese
2021-12-21 8:23 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 05/10] pci: pci_mvebu, pci_aardvark: Fix size of configuration cache Marek Behún
2021-11-12 14:04 ` Stefan Roese
2021-12-15 10:57 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 06/10] pci: pci_mvebu: Do not allow setting ROM BAR on PCI Bridge Marek Behún
2021-11-12 14:05 ` Stefan Roese
2021-12-15 10:57 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 07/10] pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping Marek Behún
2021-11-12 14:18 ` Stefan Roese
2021-11-18 17:46 ` Pali Rohár
2021-11-19 6:27 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 08/10] pci: pci_mvebu: Remove unused DECLARE_GLOBAL_DATA_PTR Marek Behún
2021-11-12 14:19 ` Stefan Roese
2021-12-21 8:23 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 09/10] arm: a37xx: pci: Do not allow setting ROM BAR on PCI Bridge Marek Behún
2021-11-12 14:19 ` Stefan Roese
2021-11-11 15:35 ` [PATCH u-boot-marvell 10/10] arm: mvebu: turris_mox: Remove extra newline after module topology Marek Behún
2021-11-12 14:20 ` Stefan Roese
2021-12-21 8:23 ` Stefan Roese
2021-12-12 11:23 ` [PATCH u-boot-marvell 00/10] PCI mvebu and aardvark changes Pali Rohár
2021-12-13 7:41 ` Stefan Roese
2021-12-13 10:27 ` Pali Rohár
2021-12-15 8:10 ` Stefan Roese
2021-12-16 10:28 ` Pali Rohár
2021-12-18 13:53 ` Stefan Roese
2021-12-20 13:30 ` Pali Rohár
2021-12-21 8:19 ` Stefan Roese
2021-12-21 10:57 ` Pali Rohár
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