From: "Woods, Brian" <Brian.Woods@amd.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Wei Liu <wei.liu2@citrix.com>,
Xen-devel <xen-devel@lists.xen.org>,
"Woods, Brian" <Brian.Woods@amd.com>,
Jan Beulich <JBeulich@suse.com>,
Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [PATCH 6/9] x86/amd: Allocate resources to cope with LS_CFG being per-core on Fam17h
Date: Thu, 6 Dec 2018 19:25:24 +0000 [thread overview]
Message-ID: <20181206192519.GA25201@amd.com> (raw)
In-Reply-To: <242d8e7c-d1b5-1947-467a-5f1ab0e471f5@citrix.com>
On Thu, Dec 06, 2018 at 06:46:51PM +0000, Andy Cooper wrote:
> On 06/12/2018 08:54, Jan Beulich wrote:
> >>>> On 05.12.18 at 18:05, <andrew.cooper3@citrix.com> wrote:
> >> On 05/12/2018 16:57, Jan Beulich wrote:
> >>>>>> On 03.12.18 at 17:18, <andrew.cooper3@citrix.com> wrote:
> >>>> --- a/xen/arch/x86/cpu/amd.c
> >>>> +++ b/xen/arch/x86/cpu/amd.c
> >>>> @@ -419,6 +419,97 @@ static void __init noinline amd_probe_legacy_ssbd(void)
> >>>> }
> >>>>
> >>>> /*
> >>>> + * This is all a gross hack, but Xen really doesn't have flexible-enough
> >>>> + * per-cpu infrastructure to do it properly. For Zen(v1) with SMT active,
> >>>> + * MSR_AMD64_LS_CFG is per-core rather than per-thread, so we need a per-core
> >>>> + * spinlock to synchronise updates of the MSR.
> >>>> + *
> >>>> + * We can't use per-cpu state because taking one CPU offline would free state
> >>>> + * under the feet of another. Ideally, we'd allocate memory on the AP boot
> >>>> + * path, but by the time the sibling information is calculated sufficiently
> >>>> + * for us to locate the per-core state, it's too late to fail the AP boot.
> >>>> + *
> >>>> + * We also can't afford to end up in a heterogeneous scenario with some CPUs
> >>>> + * unable to safely use LS_CFG.
> >>>> + *
> >>>> + * Therefore, we have to allocate for the worse-case scenario, which is
> >>>> + * believed to be 4 sockets. Any allocation failure cause us to turn LS_CFG
> >>>> + * off, as this is fractionally better than failing to boot.
> >>>> + */
> >>>> +static struct ssbd_ls_cfg {
> >>>> + spinlock_t lock;
> >>>> + unsigned int disable_count;
> >>>> +} *ssbd_ls_cfg[4];
> >>> Same question as to Brian for his original code: Instead of the
> >>> hard-coding of 4, can't you use nr_sockets here?
> >>> smp_prepare_cpus() runs before pre-SMP initcalls after all.
> >> nr_sockets has zero connection with reality as far as I can tell.
> >>
> >> On this particular box it reports 6 when the correct answer is 2. I've
> >> got some Intel boxes where nr_sockets reports 15 and the correct answer
> >> is 4.
> > If you look back at when it was introduced, the main goal was
> > for it to never be too low. Any improvements to its calculation
> > are welcome, provided they maintain that guarantee. To high
> > a socket count is imo still better than a hard-coded one.
>
> Even for the extra 2k of memory it will waste?
>
> ~Andrew
Just as a side note, for processors using MSR LS_CFG and have SMT
enabled (F17h), there should only be 2 physical sockets. The 4 was a
worst case (and before some other information was available).
Realistically, there should only be a max of 2 physical sockets when
this needed. Although, having 4 could be nice as a safe buffer and
only costs 16 bytes.
--
Brian Woods
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next prev parent reply other threads:[~2018-12-06 19:25 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-03 16:18 [PATCH 0/9] xen/amd: Support for guest MSR_VIRT_SPEC_CTRL support Andrew Cooper
2018-12-03 16:18 ` [PATCH 1/9] x86/spec-ctrl: Drop the bti= command line option Andrew Cooper
2018-12-04 16:19 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 2/9] x86/cpuid: Drop the synthetic X86_FEATURE_XEN_IBPB Andrew Cooper
2018-12-04 16:21 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 3/9] x86/cpuid: Extend the cpuid= command line option to support all named features Andrew Cooper
2018-12-04 16:28 ` Jan Beulich
2018-12-06 12:52 ` Wei Liu
2018-12-03 16:18 ` [PATCH 4/9] x86/amd: Introduce CPUID/MSR definitions for per-vcpu SSBD support Andrew Cooper
2018-12-04 16:06 ` Woods, Brian
2018-12-05 16:39 ` Jan Beulich
2018-12-05 17:50 ` Andrew Cooper
2018-12-06 8:49 ` Jan Beulich
2018-12-06 18:35 ` Andrew Cooper
2018-12-03 16:18 ` [PATCH 5/9] x86/amd: Probe for legacy SSBD interfaces on boot Andrew Cooper
2018-12-04 16:15 ` Woods, Brian
2018-12-05 16:50 ` Jan Beulich
2018-12-05 17:09 ` Andrew Cooper
2018-12-06 8:53 ` Jan Beulich
2018-12-06 10:59 ` Jan Beulich
2018-12-28 16:30 ` Andrew Cooper
2019-01-04 8:58 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 6/9] x86/amd: Allocate resources to cope with LS_CFG being per-core on Fam17h Andrew Cooper
2018-12-04 16:38 ` Woods, Brian
2018-12-05 16:57 ` Jan Beulich
2018-12-05 17:05 ` Andrew Cooper
2018-12-06 8:54 ` Jan Beulich
2018-12-06 18:46 ` Andrew Cooper
2018-12-06 19:25 ` Woods, Brian [this message]
2018-12-07 10:17 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 7/9] x86/amd: Support context switching legacy SSBD interface Andrew Cooper
2018-12-04 20:27 ` Woods, Brian
2018-12-06 10:51 ` Jan Beulich
2018-12-06 18:55 ` Andrew Cooper
2018-12-07 10:25 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 8/9] x86/amd: Virtualise MSR_VIRT_SPEC_CTRL for guests Andrew Cooper
2018-12-04 21:35 ` Woods, Brian
2018-12-05 8:41 ` Jan Beulich
2018-12-05 19:09 ` Andrew Cooper
2018-12-06 8:59 ` Jan Beulich
2018-12-06 19:41 ` Woods, Brian
2018-12-06 10:55 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 9/9] x86/amd: Offer MSR_VIRT_SPEC_CTRL to guests Andrew Cooper
2018-12-06 10:57 ` Jan Beulich
2018-12-03 16:24 ` [PATCH 0/9] xen/amd: Support for guest MSR_VIRT_SPEC_CTRL support Jan Beulich
2018-12-03 16:31 ` Andrew Cooper
2018-12-04 9:45 ` Jan Beulich
2018-12-04 11:26 ` Andrew Cooper
2018-12-04 12:45 ` Jan Beulich
2018-12-04 13:41 ` Andrew Cooper
2018-12-04 14:07 ` Jan Beulich
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