From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Wei Liu <wei.liu2@citrix.com>,
Xen-devel <xen-devel@lists.xen.org>,
Brian Woods <brian.woods@amd.com>,
Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [PATCH 4/9] x86/amd: Introduce CPUID/MSR definitions for per-vcpu SSBD support
Date: Wed, 5 Dec 2018 17:50:04 +0000 [thread overview]
Message-ID: <76dd7107-d69d-7a3f-b72a-4f0f0ee47c44@citrix.com> (raw)
In-Reply-To: <5C07FF2B02000078002033C5@prv1-mh.provo.novell.com>
On 05/12/2018 16:39, Jan Beulich wrote:
>>>> On 03.12.18 at 17:18, <andrew.cooper3@citrix.com> wrote:
>> At the time of writing, the spec is available from:
>>
>>
>> https://developer.amd.com/wp-content/resources/124441_AMD64_SpeculativeStoreB
>> ypassDisable_Whitepaper_final.pdf
>>
>> Future hardware (Zen v2) is expect to have hardware MSR_SPEC_CTRL support,
>> including SPEC_CTRL.SSBD, and with the expectation that this will be directly
>> passed through to guests for performance.
>>
>> On currently released hardware, the only mechanism available is the legacy
>> LS_CFG option, and this is very expensive to use. Furthermore, emulating
>> MSR_SPEC_CTRL via interception is prohibitively expensive, as certain OSes use
>> the write-discard flexibility to simplify their entry/exit logic.
> With this, ...
>
>> As an alternative, MSR_VIRT_SPEC_CTRL is specified as an architectural control
>> (with semantics equivilent to MSR_SPEC_CTRL) which is provided by the
>> hypervisor. This abstracts away the model-specific details of the LS_CFG
>> mechanism, which allows migration safety to be retained.
> ... how is this any less expensive, when it necessarily requires
> interception?
For an individual update? No difference.
For the case where a certain OS takes the presence of MSR_SPEC_CTRL to
mean that it needs to write MSR_SPEC_CTRL.IBRS wherever it would choose
to if IBRS was actually available, the perf difference is in the number
of writes which occur and get intercepted.
> At least the way things are worded, I'm getting
> the impression that you consider this less expensive.
>
>> --- a/tools/libxl/libxl_cpuid.c
>> +++ b/tools/libxl/libxl_cpuid.c
>> @@ -245,6 +245,11 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
>> {"invtsc", 0x80000007, NA, CPUID_REG_EDX, 8, 1},
>>
>> {"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1},
>> + {"amd_ibrs", 0x80000008, NA, CPUID_REG_EBX, 14, 1},
> While of the following two the names indeed clash with Intel's, the
> above one doesn't. Any reason you still gave it an amd_ prefix?
I really really wish we didn't have duplicate bits, or that I'd started
with blanket Intel and AMD prefixes.
I deliberately chose "IBRSB" for the Intel bit due to its double
meaning, but using just IBRS here on its own is liable to get confused
with the Intel bit.
>
>> + {"amd_stibp", 0x80000008, NA, CPUID_REG_EBX, 15, 1},
>> + {"amd_ssbd", 0x80000008, NA, CPUID_REG_EBX, 24, 1},
>> + {"virt_sc_ssbd", 0x80000008, NA, CPUID_REG_EBX, 25, 1},
>> + {"amd_ssb_no", 0x80000008, NA, CPUID_REG_EBX, 26, 1},
> Since you're at it, why not also introduce names for bits 16-18
> at this occasion?
I haven't previously filled in names for the sake of it.
The reason that ibrs/stibp/ssbd are here is because they're related and
I've also got a followon few patches to support MSR_VIRT_SPEC_CTRL on
Rome hardware via MSR_SPEC_CTRL, but I need an SDP and some
experimentation time before I'd be happy posting them.
But to address your question, I can't locate those bits at all. Not
even in the NDA docs or Linux source.
~Andrew
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next prev parent reply other threads:[~2018-12-05 17:50 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-03 16:18 [PATCH 0/9] xen/amd: Support for guest MSR_VIRT_SPEC_CTRL support Andrew Cooper
2018-12-03 16:18 ` [PATCH 1/9] x86/spec-ctrl: Drop the bti= command line option Andrew Cooper
2018-12-04 16:19 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 2/9] x86/cpuid: Drop the synthetic X86_FEATURE_XEN_IBPB Andrew Cooper
2018-12-04 16:21 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 3/9] x86/cpuid: Extend the cpuid= command line option to support all named features Andrew Cooper
2018-12-04 16:28 ` Jan Beulich
2018-12-06 12:52 ` Wei Liu
2018-12-03 16:18 ` [PATCH 4/9] x86/amd: Introduce CPUID/MSR definitions for per-vcpu SSBD support Andrew Cooper
2018-12-04 16:06 ` Woods, Brian
2018-12-05 16:39 ` Jan Beulich
2018-12-05 17:50 ` Andrew Cooper [this message]
2018-12-06 8:49 ` Jan Beulich
2018-12-06 18:35 ` Andrew Cooper
2018-12-03 16:18 ` [PATCH 5/9] x86/amd: Probe for legacy SSBD interfaces on boot Andrew Cooper
2018-12-04 16:15 ` Woods, Brian
2018-12-05 16:50 ` Jan Beulich
2018-12-05 17:09 ` Andrew Cooper
2018-12-06 8:53 ` Jan Beulich
2018-12-06 10:59 ` Jan Beulich
2018-12-28 16:30 ` Andrew Cooper
2019-01-04 8:58 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 6/9] x86/amd: Allocate resources to cope with LS_CFG being per-core on Fam17h Andrew Cooper
2018-12-04 16:38 ` Woods, Brian
2018-12-05 16:57 ` Jan Beulich
2018-12-05 17:05 ` Andrew Cooper
2018-12-06 8:54 ` Jan Beulich
2018-12-06 18:46 ` Andrew Cooper
2018-12-06 19:25 ` Woods, Brian
2018-12-07 10:17 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 7/9] x86/amd: Support context switching legacy SSBD interface Andrew Cooper
2018-12-04 20:27 ` Woods, Brian
2018-12-06 10:51 ` Jan Beulich
2018-12-06 18:55 ` Andrew Cooper
2018-12-07 10:25 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 8/9] x86/amd: Virtualise MSR_VIRT_SPEC_CTRL for guests Andrew Cooper
2018-12-04 21:35 ` Woods, Brian
2018-12-05 8:41 ` Jan Beulich
2018-12-05 19:09 ` Andrew Cooper
2018-12-06 8:59 ` Jan Beulich
2018-12-06 19:41 ` Woods, Brian
2018-12-06 10:55 ` Jan Beulich
2018-12-03 16:18 ` [PATCH 9/9] x86/amd: Offer MSR_VIRT_SPEC_CTRL to guests Andrew Cooper
2018-12-06 10:57 ` Jan Beulich
2018-12-03 16:24 ` [PATCH 0/9] xen/amd: Support for guest MSR_VIRT_SPEC_CTRL support Jan Beulich
2018-12-03 16:31 ` Andrew Cooper
2018-12-04 9:45 ` Jan Beulich
2018-12-04 11:26 ` Andrew Cooper
2018-12-04 12:45 ` Jan Beulich
2018-12-04 13:41 ` Andrew Cooper
2018-12-04 14:07 ` Jan Beulich
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