Re: [PATCH 4/9] x86/amd: Introduce CPUID/MSR definitions for per-vcpu SSBD support

From: "Jan Beulich" <JBeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Wei Liu <wei.liu2@citrix.com>,
	Xen-devel <xen-devel@lists.xen.org>,
	Brian Woods <brian.woods@amd.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [PATCH 4/9] x86/amd: Introduce CPUID/MSR definitions for per-vcpu SSBD support
Date: Thu, 06 Dec 2018 01:49:56 -0700	[thread overview]
Message-ID: <5C08E2B402000078002036DA@prv1-mh.provo.novell.com> (raw)
In-Reply-To: <76dd7107-d69d-7a3f-b72a-4f0f0ee47c44@citrix.com>

>>> On 05.12.18 at 18:50, <andrew.cooper3@citrix.com> wrote:
> On 05/12/2018 16:39, Jan Beulich wrote:
>>>>> On 03.12.18 at 17:18, <andrew.cooper3@citrix.com> wrote:
>>> As an alternative, MSR_VIRT_SPEC_CTRL is specified as an architectural control
>>> (with semantics equivilent to MSR_SPEC_CTRL) which is provided by the
>>> hypervisor.  This abstracts away the model-specific details of the LS_CFG
>>> mechanism, which allows migration safety to be retained.
>> ... how is this any less expensive, when it necessarily requires
>> interception?
> 
> For an individual update?  No difference.
> 
> For the case where a certain OS takes the presence of MSR_SPEC_CTRL to
> mean that it needs to write MSR_SPEC_CTRL.IBRS wherever it would choose
> to if IBRS was actually available, the perf difference is in the number
> of writes which occur and get intercepted.

So perhaps an OS anomaly; I'd certainly expect no difference in
behavior wrt the physical MSR's availability and the virtual one's.
Of course unless they've not implemented support for the virtual
one yet, but then as soon as they do the difference ought to
vanish.

>>> +        {"amd_stibp",    0x80000008, NA, CPUID_REG_EBX, 15,  1},
>>> +        {"amd_ssbd",     0x80000008, NA, CPUID_REG_EBX, 24,  1},
>>> +        {"virt_sc_ssbd", 0x80000008, NA, CPUID_REG_EBX, 25,  1},
>>> +        {"amd_ssb_no",   0x80000008, NA, CPUID_REG_EBX, 26,  1},
>> Since you're at it, why not also introduce names for bits 16-18
>> at this occasion?
> 
> I haven't previously filled in names for the sake of it.
> 
> The reason that ibrs/stibp/ssbd are here is because they're related and
> I've also got a followon few patches to support MSR_VIRT_SPEC_CTRL on
> Rome hardware via MSR_SPEC_CTRL, but I need an SDP and some
> experimentation time before I'd be happy posting them.
> 
> But to address your question, I can't locate those bits at all.  Not
> even in the NDA docs or Linux source.

Hmm, that's certainly odd. I've found them quite some time ago in this
public whitepaper:
https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf
They're all clearly IBRS/STIBP related.

Jan

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