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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Wei Liu <wei.liu2@citrix.com>,
	Xen-devel <xen-devel@lists.xen.org>,
	Brian Woods <brian.woods@amd.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [PATCH 7/9] x86/amd: Support context switching legacy SSBD interface
Date: Thu, 6 Dec 2018 18:55:07 +0000	[thread overview]
Message-ID: <67fb003a-1914-2051-2cd8-e1791e17a0cc@citrix.com> (raw)
In-Reply-To: <5C08FF1A02000078002039AC@prv1-mh.provo.novell.com>

On 06/12/2018 10:51, Jan Beulich wrote:
>
>> +	unsigned int socket = c->phys_proc_id, core = c->cpu_core_id;
>> +	struct ssbd_ls_cfg *cfg;
>> +	uint64_t val;
>> +
>> +	ASSERT(cpu_has_legacy_ssbd);
>> +
>> +	/*
>> +	 * Update hardware lazily, as these MSRs are expensive.  However, on
>> +	 * the boot paths which pass NULL, force a write to set a consistent
>> +	 * initial state.
>> +	 */
>> +	if (*this_ssbd == disable && next)
>> +		return;
>> +
>> +	if (cpu_has_virt_sc_ssbd) {
>> +		wrmsrl(MSR_VIRT_SPEC_CTRL,
>> +		       disable ? SPEC_CTRL_SSBD : 0);
>> +		goto done;
>> +	}
>> +
>> +	val = ls_cfg_base | (disable ? ls_cfg_ssbd_mask : 0);
>> +
>> +	if (c->x86 < 0x17 || c->x86_num_siblings == 1) {
>> +		/* No threads to be concerned with. */
>> +		wrmsrl(MSR_AMD64_LS_CFG, val);
>> +		goto done;
>> +	}
>> +
>> +	/* Check that we won't overflow the worse-case allocation. */
>> +	BUG_ON(socket >= ARRAY_SIZE(ssbd_ls_cfg));
>> +	BUG_ON(core   >= ssbd_max_cores);
> Wouldn't it be better to fail onlining of such CPUs?

How?  We've not currently got an ability to fail in the middle of
start_secondary(), which is why the previous patch really does go an
allocate the worst case.

These are here because I don't trust really trust the topology logic
(which turned out to be very wise, in retrospect), not because I
actually expect them to trigger from now on.

>
>> +	cfg = &ssbd_ls_cfg[socket][core];
>> +
>> +	if (disable) {
>> +		spin_lock(&cfg->lock);
>> +
>> +		/* First sibling to disable updates hardware. */
>> +		if (!cfg->disable_count)
>> +			wrmsrl(MSR_AMD64_LS_CFG, val);
>> +		cfg->disable_count++;
>> +
>> +		spin_unlock(&cfg->lock);
>> +	} else {
>> +		spin_lock(&cfg->lock);
>> +
>> +		/* Last sibling to enable updates hardware. */
>> +		cfg->disable_count--;
>> +		if (!cfg->disable_count)
>> +			wrmsrl(MSR_AMD64_LS_CFG, val);
>> +
>> +		spin_unlock(&cfg->lock);
>> +	}
> Any reason for duplicating the spin_{,un}lock() calls?

To avoid having a context-dependent jump in the critical region.  Then
again, I suppose that is completely dwarfed by the WRMSR.

~Andrew

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  reply	other threads:[~2018-12-06 18:55 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-03 16:18 [PATCH 0/9] xen/amd: Support for guest MSR_VIRT_SPEC_CTRL support Andrew Cooper
2018-12-03 16:18 ` [PATCH 1/9] x86/spec-ctrl: Drop the bti= command line option Andrew Cooper
2018-12-04 16:19   ` Jan Beulich
2018-12-03 16:18 ` [PATCH 2/9] x86/cpuid: Drop the synthetic X86_FEATURE_XEN_IBPB Andrew Cooper
2018-12-04 16:21   ` Jan Beulich
2018-12-03 16:18 ` [PATCH 3/9] x86/cpuid: Extend the cpuid= command line option to support all named features Andrew Cooper
2018-12-04 16:28   ` Jan Beulich
2018-12-06 12:52   ` Wei Liu
2018-12-03 16:18 ` [PATCH 4/9] x86/amd: Introduce CPUID/MSR definitions for per-vcpu SSBD support Andrew Cooper
2018-12-04 16:06   ` Woods, Brian
2018-12-05 16:39   ` Jan Beulich
2018-12-05 17:50     ` Andrew Cooper
2018-12-06  8:49       ` Jan Beulich
2018-12-06 18:35         ` Andrew Cooper
2018-12-03 16:18 ` [PATCH 5/9] x86/amd: Probe for legacy SSBD interfaces on boot Andrew Cooper
2018-12-04 16:15   ` Woods, Brian
2018-12-05 16:50   ` Jan Beulich
2018-12-05 17:09     ` Andrew Cooper
2018-12-06  8:53       ` Jan Beulich
2018-12-06 10:59   ` Jan Beulich
2018-12-28 16:30     ` Andrew Cooper
2019-01-04  8:58       ` Jan Beulich
2018-12-03 16:18 ` [PATCH 6/9] x86/amd: Allocate resources to cope with LS_CFG being per-core on Fam17h Andrew Cooper
2018-12-04 16:38   ` Woods, Brian
2018-12-05 16:57   ` Jan Beulich
2018-12-05 17:05     ` Andrew Cooper
2018-12-06  8:54       ` Jan Beulich
2018-12-06 18:46         ` Andrew Cooper
2018-12-06 19:25           ` Woods, Brian
2018-12-07 10:17           ` Jan Beulich
2018-12-03 16:18 ` [PATCH 7/9] x86/amd: Support context switching legacy SSBD interface Andrew Cooper
2018-12-04 20:27   ` Woods, Brian
2018-12-06 10:51   ` Jan Beulich
2018-12-06 18:55     ` Andrew Cooper [this message]
2018-12-07 10:25       ` Jan Beulich
2018-12-03 16:18 ` [PATCH 8/9] x86/amd: Virtualise MSR_VIRT_SPEC_CTRL for guests Andrew Cooper
2018-12-04 21:35   ` Woods, Brian
2018-12-05  8:41     ` Jan Beulich
2018-12-05 19:09       ` Andrew Cooper
2018-12-06  8:59         ` Jan Beulich
2018-12-06 19:41       ` Woods, Brian
2018-12-06 10:55   ` Jan Beulich
2018-12-03 16:18 ` [PATCH 9/9] x86/amd: Offer MSR_VIRT_SPEC_CTRL to guests Andrew Cooper
2018-12-06 10:57   ` Jan Beulich
2018-12-03 16:24 ` [PATCH 0/9] xen/amd: Support for guest MSR_VIRT_SPEC_CTRL support Jan Beulich
2018-12-03 16:31   ` Andrew Cooper
2018-12-04  9:45     ` Jan Beulich
2018-12-04 11:26       ` Andrew Cooper
2018-12-04 12:45         ` Jan Beulich
2018-12-04 13:41           ` Andrew Cooper
2018-12-04 14:07             ` Jan Beulich

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