* [v2, 00/16] Enable ARM Trusted Firmware for U-Boot
@ 2020-10-01 9:15 Siew Chin Lim
2020-10-01 9:15 ` [v2, 01/16] arm: socfpga: soc64: Remove CONFIG_OF_EMBED Siew Chin Lim
` (16 more replies)
0 siblings, 17 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:15 UTC (permalink / raw)
To: u-boot
This is the 2nd version of patchset to Enable ARM Trusted Firmware
for U-Boot.
New U-boot flow with ARM Trusted Firmware (ATF) support:
SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
SPL loads the u-boot.itb which consist of:
1) u-boot-nodtb.bin (U-Boot Proper image)
2) u-boot.dtb (U-Boot Proper DTB)
3) bl31.bin (ATF-BL31 image)
Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex)
Patch status:
Have changes: Patch 2, 8, 9, 10, 11, 16
Other patches unchanged.
Detail changelog can find in commit message.
v1->v2:
--------
Patch 2:
- Move soc64 folder from board/altera to board/intel folder
Patch 8:
- Updated comments
Patch 9:
- Code clean up without functionality change
Patch 10:
- Code clean up without functionality change
Patch 11:
- Print error message and return instead of hang in socfpga_bridges_reset()
when SMC call is failing.
Patch 16:
- Add CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
- Move board/altera/soc64/fit_spl_atf.sh to board/intel/soc64/fit_spl_atf.sh
History:
--------
[v1]: https://patchwork.ozlabs.org/project/uboot/list/?series=195854
These patchsets have dependency on:
arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
https://lists.denx.de/pipermail/u-boot/2020-August/423029.html
Rename Stratix10 FPGA driver and support Agilex
https://lists.denx.de/pipermail/u-boot/2020-August/422798.html
SoCFPGA mailbox driver fixes and enhancements
https://lists.denx.de/pipermail/u-boot/2020-August/423140.html
arm: socfpga: soc64: Initialize timer in SPL only
https://lists.denx.de/pipermail/u-boot/2020-July/419692.html
arm: socfpga: soc64: Remove PHY interface setup from misc arch init
https://lists.denx.de/pipermail/u-boot/2020-July/419690.html
Enable sysreset support for SoCFPGA SoC64 platforms
https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
Chee Hong Ang (16):
arm: socfpga: soc64: Remove CONFIG_OF_EMBED
arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
arm: socfpga: Add function for checking description from FIT image
arm: socfpga: soc64: Load FIT image with ATF support
arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
arm: socfpga: Disable "spin-table" method for booting Linux
arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
(64bits)
arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
services
mmc: dwmmc: socfpga: Add ATF support for MMC driver
net: designware: socfpga: Add ATF support for MAC driver
arm: socfpga: soc64: Add ATF support for Reset Manager driver
arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
mbox_reset_cold()
arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
arm: socfpga: soc64: Skip handoff data access in SSBL
configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
support
arch/arm/mach-socfpga/Kconfig | 2 -
arch/arm/mach-socfpga/Makefile | 4 +
arch/arm/mach-socfpga/board.c | 12 +-
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
arch/arm/mach-socfpga/smc_api.c | 56 ++
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +-
board/intel/soc64/fit_spl_atf.sh | 92 ++++
...ilex_defconfig => socfpga_agilex_atf_defconfig} | 23 +-
configs/socfpga_agilex_defconfig | 1 -
...0_defconfig => socfpga_stratix10_atf_defconfig} | 25 +-
configs/socfpga_stratix10_defconfig | 1 -
drivers/fpga/intel_sdm_mb.c | 139 +++++
drivers/mmc/socfpga_dw_mmc.c | 26 +-
drivers/net/dwmac_socfpga.c | 31 +-
include/configs/socfpga_soc64_common.h | 9 +
include/linux/intel-smc.h | 573 +++++++++++++++++++++
19 files changed, 1071 insertions(+), 33 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S
create mode 100644 arch/arm/mach-socfpga/smc_api.c
create mode 100755 board/intel/soc64/fit_spl_atf.sh
copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig} (79%)
copy configs/{socfpga_stratix10_defconfig => socfpga_stratix10_atf_defconfig} (79%)
create mode 100644 include/linux/intel-smc.h
--
2.13.0
^ permalink raw reply [flat|nested] 22+ messages in thread
* [v2, 01/16] arm: socfpga: soc64: Remove CONFIG_OF_EMBED
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
@ 2020-10-01 9:15 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 02/16] arm: socfpga: soc64: Add FIT generator script for pack itb with ATF Siew Chin Lim
` (15 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:15 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
CONFIG_OF_EMBED was primarily enabled to support the S10/Agilex
spl hex file requirements. Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
configs/socfpga_agilex_defconfig | 1 -
configs/socfpga_stratix10_defconfig | 1 -
2 files changed, 2 deletions(-)
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 03ed1f5619..3a9b3b5074 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -35,7 +35,6 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index e293b19e88..a48388f458 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -37,7 +37,6 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 02/16] arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
2020-10-01 9:15 ` [v2, 01/16] arm: socfpga: soc64: Remove CONFIG_OF_EMBED Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 03/16] arm: socfpga: Add function for checking description from FIT image Siew Chin Lim
` (14 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Generate a FIT image for Intel SOCFPGA (64bits) which
include U-boot proper, ATF and DTB for U-boot proper.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
v2:
- Move soc64 folder from board/altera to board/intel folder
---
board/intel/soc64/fit_spl_atf.sh | 92 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
create mode 100755 board/intel/soc64/fit_spl_atf.sh
diff --git a/board/intel/soc64/fit_spl_atf.sh b/board/intel/soc64/fit_spl_atf.sh
new file mode 100755
index 0000000000..40f0e20c05
--- /dev/null
+++ b/board/intel/soc64/fit_spl_atf.sh
@@ -0,0 +1,92 @@
+#!/bin/sh
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for Stratix 10 and
+# Agilex boards with U-Boot proper, ATF and device tree
+# for U-Boot proper.
+#
+# usage: $0 <DT_NAME>
+
+BL31="bl31.bin"
+if [ ! -f $BL31 ]; then
+ echo "BL31 file \"$BL31\" NOT found!" >&2
+ exit 1
+fi
+
+BL33="u-boot-nodtb.bin"
+if [ ! -f $BL33 ]; then
+ echo "BL33 file \"$BL33\" NOT found!" >&2
+ exit 1
+fi
+
+if [ -f "$1" ] ; then
+ DT_NAME="$1"
+else
+ echo "File not found: \"$1\"" >&2
+ exit 1
+fi
+
+cat << __PREAMBLE_EOF
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper, ATF bl31, U-Boot DTB";
+ #address-cells = <1>;
+
+__PREAMBLE_EOF
+
+cat << __IMAGES_EOF
+ images {
+ uboot {
+ description = "U-Boot SoC64";
+ data = /incbin/("$BL33");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x00200000>;
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ data = /incbin/("$BL31");
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x00001000>;
+ entry = <0x00001000>;
+ };
+
+ fdt {
+ description = "U-Boot SoC64 flat device-tree";
+ data = /incbin/("$DT_NAME");
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+__IMAGES_EOF
+
+cat << __CONFIGS_EOF
+ configurations {
+ default = "conf";
+ conf {
+ description = "Intel SoC64 FPGA";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+ };
+ };
+__CONFIGS_EOF
+
+cat << __END_EOF
+};
+__END_EOF
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 03/16] arm: socfpga: Add function for checking description from FIT image
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
2020-10-01 9:15 ` [v2, 01/16] arm: socfpga: soc64: Remove CONFIG_OF_EMBED Siew Chin Lim
2020-10-01 9:16 ` [v2, 02/16] arm: socfpga: soc64: Add FIT generator script for pack itb with ATF Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 04/16] arm: socfpga: soc64: Load FIT image with ATF support Siew Chin Lim
` (13 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/board.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 340abf9305..7993c27646 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -13,7 +13,7 @@
#include <asm/arch/clock_manager.h>
#include <asm/arch/misc.h>
#include <asm/io.h>
-
+#include <log.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
@@ -87,3 +87,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 04/16] arm: socfpga: soc64: Load FIT image with ATF support
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (2 preceding siblings ...)
2020-10-01 9:16 ` [v2, 03/16] arm: socfpga: Add function for checking description from FIT image Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 05/16] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF Siew Chin Lim
` (12 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
include/configs/socfpga_soc64_common.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index fb5e2e8aaf..cb9bb21597 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -193,6 +193,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
- CONFIG_SYS_SPL_MALLOC_SIZE)
/* SPL SDMMC boot support */
+#ifdef CONFIG_SPL_LOAD_FIT
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
+#else
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#endif
#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 05/16] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (3 preceding siblings ...)
2020-10-01 9:16 ` [v2, 04/16] arm: socfpga: soc64: Load FIT image with ATF support Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 06/16] arm: socfpga: Disable "spin-table" method for booting Linux Siew Chin Lim
` (11 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 418f543b20..c63162a5c6 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -29,6 +29,7 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
+obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
@@ -41,6 +42,7 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += clock_manager_agilex.o
+obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
new file mode 100644
index 0000000000..612ea8a037
--- /dev/null
+++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+ENTRY(lowlevel_init)
+ mov x29, lr /* Save LR */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+wait_for_atf:
+ ldr x4, =CPU_RELEASE_ADDR
+ ldr x5, [x4]
+ cbz x5, slave_wait_atf
+ br x5
+slave_wait_atf:
+ branch_if_slave x0, wait_for_atf
+#else
+ branch_if_slave x0, 1f
+#endif
+ ldr x0, =GICD_BASE
+ bl gic_init_secure
+1:
+#if defined(CONFIG_GICV3)
+ ldr x0, =GICR_BASE
+ bl gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+ ldr x0, =GICD_BASE
+ ldr x1, =GICC_BASE
+ bl gic_init_secure_percpu
+#endif
+#endif
+
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ branch_if_master x0, x1, 2f
+
+ /*
+ * Slave should wait for master clearing spin table.
+ * This sync prevent slaves observing incorrect
+ * value of spin table and jumping to wrong place.
+ */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+ ldr x0, =GICC_BASE
+#endif
+ bl gic_wait_for_interrupt
+#endif
+
+ /*
+ * All slaves will enter EL2 and optionally EL1.
+ */
+ adr x4, lowlevel_in_el2
+ ldr x5, =ES_TO_AARCH64
+ bl armv8_switch_to_el2
+
+lowlevel_in_el2:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x4, lowlevel_in_el1
+ ldr x5, =ES_TO_AARCH64
+ bl armv8_switch_to_el1
+
+lowlevel_in_el1:
+#endif
+
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+2:
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(lowlevel_init)
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 06/16] arm: socfpga: Disable "spin-table" method for booting Linux
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (4 preceding siblings ...)
2020-10-01 9:16 ` [v2, 05/16] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 07/16] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) Siew Chin Lim
` (10 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 37083ec0d8..38795265e5 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
- select ARMV8_SPIN_TABLE
select CLK
select FPGA_INTEL_SDM_MAILBOX
select NCORE_CACHE
@@ -79,7 +78,6 @@ config TARGET_SOCFPGA_STRATIX10
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
- select ARMV8_SPIN_TABLE
select FPGA_INTEL_SDM_MAILBOX
choice
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 07/16] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (5 preceding siblings ...)
2020-10-01 9:16 ` [v2, 06/16] arm: socfpga: Disable "spin-table" method for booting Linux Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 08/16] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services Siew Chin Lim
` (9 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +++++++
arch/arm/mach-socfpga/smc_api.c | 56 ++++++++++++++++++++++++++++
3 files changed, 71 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/smc_api.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c63162a5c6..0b05283a7a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -72,6 +72,8 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
endif
+else
+obj-$(CONFIG_SPL_ATF) += smc_api.o
endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h b/arch/arm/mach-socfpga/include/mach/smc_api.h
new file mode 100644
index 0000000000..bbefdd8dd9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/smc_api.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#ifndef _SMC_API_H_
+#define _SMC_API_H_
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+ u32 *resp_buf);
+
+#endif /* _SMC_API_H_ */
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
new file mode 100644
index 0000000000..085daba162
--- /dev/null
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <linux/intel-smc.h>
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+ struct pt_regs regs;
+
+ memset(®s, 0, sizeof(regs));
+ regs.regs[0] = func_id;
+
+ if (args)
+ memcpy(®s.regs[1], args, arg_len * sizeof(*args));
+
+ smc_call(®s);
+
+ if (ret_arg)
+ memcpy(ret_arg, ®s.regs[1], ret_len * sizeof(*ret_arg));
+
+ return regs.regs[0];
+}
+
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+ u32 *resp_buf)
+{
+ int ret;
+ u64 args[6];
+ u64 resp[3];
+
+ args[0] = cmd;
+ args[1] = (u64)arg;
+ args[2] = len;
+ args[3] = urgent;
+ args[4] = (u64)resp_buf;
+ if (resp_buf_len)
+ args[5] = *resp_buf_len;
+ else
+ args[5] = 0;
+
+ ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
+ resp, ARRAY_SIZE(resp));
+
+ if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) {
+ if (!resp[0])
+ *resp_buf_len = resp[1];
+ }
+
+ return (int)resp[0];
+}
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 08/16] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (6 preceding siblings ...)
2020-10-01 9:16 ` [v2, 07/16] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 09/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver Siew Chin Lim
` (8 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
This header file defines the Secure Monitor Call (SMC) message
protocol for ATF (BL31) PSCI runtime services. It includes all
the PSCI SiP function identifiers for the secure runtime services
provided by ATF. The secure runtime services include System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration, Remote
System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
v2:
- Updated comments:
- Changed string 'kernel tree' to 'u-boot tree'
- INTEL_SIP_SMC_STATUS_OK and INTEL_SIP_SMC_STATUS ERROR are not for
FPGA configuration only, they are common return values in
INTEL_SIP_SMC_* call.
---
include/linux/intel-smc.h | 573 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 573 insertions(+)
create mode 100644 include/linux/intel-smc.h
diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h
new file mode 100644
index 0000000000..cacb410691
--- /dev/null
+++ b/include/linux/intel-smc.h
@@ -0,0 +1,573 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2018, Intel Corporation
+ */
+
+#ifndef __INTEL_SMC_H
+#define __INTEL_SMC_H
+
+#include <linux/arm-smccc.h>
+#include <linux/bitops.h>
+
+/*
+ * This file defines the Secure Monitor Call (SMC) message protocol used for
+ * service layer driver in normal world (EL1) to communicate with secure
+ * monitor software in Secure Monitor Exception Level 3 (EL3).
+ *
+ * This file is shared with secure firmware (FW) which is out of u-boot tree.
+ *
+ * An ARM SMC instruction takes a function identifier and up to 6 64-bit
+ * register values as arguments, and can return up to 4 64-bit register
+ * values. The operation of the secure monitor is determined by the parameter
+ * values passed in through registers.
+
+ * EL1 and EL3 communicates pointer as physical address rather than the
+ * virtual address.
+ */
+
+/*
+ * Functions specified by ARM SMC Calling convention:
+ *
+ * FAST call executes atomic operations, returns when the requested operation
+ * has completed.
+ * STD call starts a operation which can be preempted by a non-secure
+ * interrupt. The call can return before the requested operation has
+ * completed.
+ *
+ * a0..a7 is used as register names in the descriptions below, on arm32
+ * that translates to r0..r7 and on arm64 to w0..w7.
+ */
+
+#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
+ ARM_SMCCC_OWNER_SIP, (func_num))
+
+#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
+ ARM_SMCCC_OWNER_SIP, (func_num))
+
+/*
+ * Return values in INTEL_SIP_SMC_* call
+ *
+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION:
+ * Secure monitor software doesn't recognize the request.
+ *
+ * INTEL_SIP_SMC_STATUS_OK:
+ * SMC call completed successfully,
+ * In case of FPGA configuration write operation, it means secure monitor
+ * software can accept the next chunk of FPGA configuration data.
+ *
+ * INTEL_SIP_SMC_STATUS_BUSY:
+ * In case of FPGA configuration write operation, it means secure monitor
+ * software is still processing previous data & can't accept the next chunk
+ * of data. Service driver needs to issue
+ * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the
+ * completed block(s).
+ *
+ * INTEL_SIP_SMC_STATUS_ERROR:
+ * There is error during the SMC call process.
+ *
+ * INTEL_SIP_SMC_REG_ERROR:
+ * There is error during a read or write operation of the protected
+ * registers.
+ */
+#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF
+#define INTEL_SIP_SMC_STATUS_OK 0x0
+#define INTEL_SIP_SMC_STATUS_BUSY 0x1
+#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
+#define INTEL_SIP_SMC_STATUS_ERROR 0x4
+#define INTEL_SIP_SMC_REG_ERROR 0x5
+#define INTEL_SIP_SMC_RSU_ERROR 0x7
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_START
+ *
+ * Sync call used by service driver at EL1 to request the FPGA in EL3 to
+ * be prepare to receive a new configuration.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_START.
+ * a1: flag for full or partial configuration
+ * 0 full reconfiguration.
+ * 1 partial reconfiguration.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
+#define INTEL_SIP_SMC_FPGA_CONFIG_START \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE
+ *
+ * Async call used by service driver at EL1 to provide FPGA configuration data
+ * to secure world.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE.
+ * a1: 64bit physical address of the configuration data memory block
+ * a2: Size of configuration data block.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY,
+ * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1: 64bit physical address of 1st completed memory block if any completed
+ * block, otherwise zero value.
+ * a2: 64bit physical address of 2nd completed memory block if any completed
+ * block, otherwise zero value.
+ * a3: 64bit physical address of 3rd completed memory block if any completed
+ * block, otherwise zero value.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2
+#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \
+ INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE
+ *
+ * Sync call used by service driver at EL1 to track the completed write
+ * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE
+ * call returns INTEL_SIP_SMC_STATUS_BUSY.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
+ * INTEL_SIP_SMC_STATUS_ERROR.
+ * a1: 64bit physical address of 1st completed memory block.
+ * a2: 64bit physical address of 2nd completed memory block if
+ * any completed block, otherwise zero value.
+ * a3: 64bit physical address of 3rd completed memory block if
+ * any completed block, otherwise zero value.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3
+#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \
+INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE
+ *
+ * Sync call used by service driver at EL1 to inform secure world that all
+ * data are sent, to check whether or not the secure world had completed
+ * the FPGA configuration process.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
+ * INTEL_SIP_SMC_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4
+#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM
+ *
+ * Sync call used by service driver at EL1 to query the physical address of
+ * memory block reserved by secure monitor software.
+ *
+ * Call register usage:
+ * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1: start of physical address of reserved memory block.
+ * a2: size of reserved memory block.
+ * a3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5
+#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK
+ *
+ * For SMC loop-back mode only, used for internal integration, debugging
+ * or troubleshooting.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6
+#define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
+
+/*
+ * Request INTEL_SIP_SMC_REG_READ
+ *
+ * Read a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_READ.
+ * a1: register address.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1: Value in the register
+ * a2-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_READ 7
+#define INTEL_SIP_SMC_REG_READ \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
+
+/*
+ * Request INTEL_SIP_SMC_REG_WRITE
+ *
+ * Write a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_WRITE.
+ * a1: register address
+ * a2: value to program into register.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
+#define INTEL_SIP_SMC_REG_WRITE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE
+ *
+ * Update one or more bits in a protected register using a
+ * read-modify-write operation.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_UPDATE.
+ * a1: register address
+ * a2: Write Mask.
+ * a3: Value to write.
+ * a4-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1-3: Not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9
+#define INTEL_SIP_SMC_REG_UPDATE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
+
+/*
+* Request INTEL_SIP_SMC_RSU_STATUS
+*
+* Sync call used by service driver at EL1 to query the RSU status
+*
+* Call register usage:
+* a0 INTEL_SIP_SMC_RSU_STATUS
+* a1-7 not used
+*
+* Return status
+* a0: Current Image
+* a1: Last Failing Image
+* a2: Version [width 32 bit] | State [width 32 bit]
+* a3: Error details [width 32 bit] | Error location [width 32 bit]
+*
+* Or
+*
+* a0: INTEL_SIP_SMC_RSU_ERROR
+*/
+#define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11
+#define INTEL_SIP_SMC_RSU_STATUS \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS)
+
+/*
+* Request INTEL_SIP_SMC_RSU_UPDATE
+*
+* Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE
+*
+* Call register usage:
+* a0 INTEL_SIP_SMC_RSU_UPDATE
+* a1 64bit physical address of the configuration data memory in flash
+* a2-7 not used
+*
+* Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+*/
+#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
+#define INTEL_SIP_SMC_RSU_UPDATE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
+
+/*
+ * Request INTEL_SIP_SMC_ECC_DBE
+ *
+ * Sync call used by service driver at EL1 alert EL3 that a Double Bit
+ * ECC error has occurred.
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_ECC_DBE
+ * a1 SysManager Double Bit Error value
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
+#define INTEL_SIP_SMC_ECC_DBE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
+
+/*
+* Request INTEL_SIP_SMC_RSU_NOTIFY
+*
+* Sync call used by service driver at EL1 to report HPS software execution stage
+*
+* Call register usage:
+* a0 INTEL_SIP_SMC_RSU_NOTIFY
+* a1 32bit HPS software execution stage
+* a2-7 not used
+*
+* Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+*/
+#define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14
+#define INTEL_SIP_SMC_RSU_NOTIFY \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER
+ *
+ * Sync call used by service driver at EL1 to query the RSU retry counter
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER
+ * a1-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_RSU_ERROR.
+ * a1 retry counter
+*/
+#define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15
+#define INTEL_SIP_SMC_RSU_RETRY_COUNTER \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_DCMF_VERSION
+ *
+ * Sync call used by service driver at EL1 to query DCMF version
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION
+ * a1-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ * a1 dcmf1 version | dcmf0 version
+ * a2 dcmf3 version | dcmf2 version
+ *
+ * Or
+ *
+ * a0 INTEL_SIP_SMC_RSU_ERROR
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION 16
+#define INTEL_SIP_SMC_RSU_DCMF_VERSION \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION
+ *
+ * Sync call used by SSBL (EL2) to copy DCMF version to ATF memory
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION
+ * a1 dcmf1 version | dcmf0 version
+ * a2 dcmf3 version | dcmf2 version
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION 17
+#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_MAX_RETRY
+ *
+ * Sync call used by service driver at EL1 to query max_retry parameter
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_MAX_RETRY
+ * a1-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ * a1 max_retry
+ *
+ * Or
+ *
+ * a0 INTEL_SIP_SMC_RSU_ERROR
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY 18
+#define INTEL_SIP_SMC_RSU_MAX_RETRY \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_COPY_MAX_RETRY
+ *
+ * Sync call used by SSBL (EL2) to copy RSU 'max retry' to ATF memory
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_COPY_MAX_RETRY
+ * a1 max retry
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY 19
+#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_DCMF_STATUS
+ *
+ * Sync call used by service driver at EL1 to query DCMF status
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_DCMF_STATUS
+ * a1-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ * a1 dcmf3 status | dcmf2 status | dcmf1 status | dcmf0 status
+ *
+ * Or
+ *
+ * a0 INTEL_SIP_SMC_RSU_ERROR
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS 20
+#define INTEL_SIP_SMC_RSU_DCMF_STATUS \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS
+ *
+ * Sync call used by SSBL (EL2) to copy RSU 'dcmf status' to ATF memory
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS
+ * a1 dcmf status
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS 21
+#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS)
+
+/*
+ * Request INTEL_SIP_SMC_HPS_SET_BRIDGES
+ *
+ * Enable/disable the SoC FPGA bridges
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES
+ * a1 Set bridges status:
+ * 0 - Disable
+ * 1 - Enable
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES 50
+#define INTEL_SIP_SMC_HPS_SET_BRIDGES \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES)
+
+/*
+ * Request INTEL_SIP_SMC_MBOX_SEND_CMD
+ *
+ * Send mailbox command to SDM
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_MBOX_SEND_CMD
+ * a1 Mailbox command
+ * a2 64bit physical address pointer to command's arguments
+ * a3 Length of the argument
+ * a4 Urgent command:
+ * 0 - Disable
+ * 1 - Enable
+ * a5 64bit physical address pointer to a buffer for receiving responses
+ * a6 Length of the buffer
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
+ * a1 Status of mailbox response
+ * a2 Received length in the buffer
+ */
+#define INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD 60
+#define INTEL_SIP_SMC_MBOX_SEND_CMD \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD)
+
+/*
+ * Request INTEL_SIP_SMC_HPS_SET_PHYINTF
+ *
+ * Select EMACx PHY interface
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF
+ * a1 EMAC number:
+ * 0 - EMAC0
+ * 1 - EMAC1
+ * 2 - EMAC2
+ * a2 Type of PHY interface:
+ * 0 - GMII_MII
+ * 1 - RGMII
+ * 2 - RMII
+ * 3 - RESET
+ * a3-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
+ */
+#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61
+#define INTEL_SIP_SMC_HPS_SET_PHYINTF \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF)
+
+/*
+ * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
+ *
+ * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
+ * a1 Select which phase shift of the clock for cclk_in_drv (drvsel):
+ * 0 - 0 degree
+ * 1 - 45 degrees
+ * 2 - 90 degrees
+ * 3 - 135 degrees
+ * 4 - 180 degrees
+ * 5 - 225 degrees
+ * 6 - 270 degrees
+ * 7 - 315 degrees
+ * a2 Select which phase shift of the clock for cclk_in_sample (smplsel):
+ * (Same as above)
+ * a3-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK 62
+#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK)
+
+#endif
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 09/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (7 preceding siblings ...)
2020-10-01 9:16 ` [v2, 08/16] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 10/16] net: designware: socfpga: Add ATF support for MAC driver Siew Chin Lim
` (7 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
v2:
- Code clean up without functionality change:
- Changed socfpga_dwmci_fw_clksel() to socfpga_dwmci_do_clksel().
This function will be called in both legacy and ATF boot flow.
- Move #ifdef .. #endif switch into socfpga_dwmci_do_clksel().
- Remove #ifdef .. #endif switch from socfpga_dwmci_clksel(),
Directly call socfpga_dwmci_do_clksel() in socfpga_dwmci_clksel().
---
drivers/mmc/socfpga_dw_mmc.c | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0022f943bd..404dd2c91a 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <log.h>
#include <asm/arch/clock_manager.h>
+#include <asm/arch/smc_api.h>
#include <asm/arch/system_manager.h>
#include <clk.h>
#include <dm.h>
@@ -13,6 +14,7 @@
#include <errno.h>
#include <fdtdec.h>
#include <dm/device_compat.h>
+#include <linux/intel-smc.h>
#include <linux/libfdt.h>
#include <linux/err.h>
#include <malloc.h>
@@ -46,6 +48,26 @@ static void socfpga_dwmci_reset(struct udevice *dev)
reset_deassert_bulk(&reset_bulk);
}
+static void socfpga_dwmci_do_clksel(u32 sdmmc_mask)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 args[2];
+
+ /* drvsel */
+ args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7;
+ /* smplsel */
+ args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7;
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2, NULL, 0))
+ dev_err(host->dev, "SMC call failed in %s\n", __func__);
+
+#else
+ writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
+
+ debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
+ readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
+}
+
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
@@ -58,10 +80,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
- writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
- debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
- readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+ socfpga_dwmci_do_clksel(sdmmc_mask);
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 10/16] net: designware: socfpga: Add ATF support for MAC driver
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (8 preceding siblings ...)
2020-10-01 9:16 ` [v2, 09/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 11/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver Siew Chin Lim
` (6 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
v2:
- Code clean up without functionality change:
- Changed dwmac_socfpga_fw_setphy() to dwmac_socfpga_do_setphy().
This function will be called in both legacy and ATF boot flow.
- Use phy_intf value from phandle in dwmac_socfpga_do_setphy().
- Move #ifdef .. #endif switch into dwmac_socfpga_do_setphy(),
and directly call it in dwmac_socfpga_probe().
---
drivers/net/dwmac_socfpga.c | 31 +++++++++++++++++++++++++++----
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561dffa..2528577b34 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -17,7 +17,9 @@
#include <dm/device_compat.h>
#include <linux/err.h>
+#include <asm/arch/smc_api.h>
#include <asm/arch/system_manager.h>
+#include <linux/intel-smc.h>
struct dwmac_socfpga_platdata {
struct dw_eth_pdata dw_eth_pdata;
@@ -64,6 +66,28 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
return designware_eth_ofdata_to_platdata(dev);
}
+static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
+{
+ struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 args[2];
+ int ret;
+
+ args[0] = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
+ SYSMGR_SOC64_EMAC0) >> 2;
+ args[1] = modereg;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_PHYINTF, args, 2, NULL, 0))
+ return -EIO;
+#else
+ clrsetbits_le32(pdata->phy_intf, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
+ pdata->reg_shift, modereg << pdata->reg_shift);
+#endif
+
+ return 0;
+}
+
static int dwmac_socfpga_probe(struct udevice *dev)
{
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +95,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct reset_ctl_bulk reset_bulk;
int ret;
u32 modereg;
- u32 modemask;
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_MII:
@@ -97,9 +120,9 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(&reset_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+ ret = dwmac_socfpga_do_setphy(dev, modereg);
+ if (ret)
+ return ret;
reset_release_bulk(&reset_bulk);
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 11/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (9 preceding siblings ...)
2020-10-01 9:16 ` [v2, 10/16] net: designware: socfpga: Add ATF support for MAC driver Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 12/16] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver Siew Chin Lim
` (5 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
v2:
- Print error message and return instead of hang in
socfpga_bridges_reset() when SMC call is failing.
---
arch/arm/mach-socfpga/reset_manager_s10.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 3746e6a60c..af8f2c0873 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,11 +5,14 @@
*/
#include <common.h>
+#include <hang.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
+#include <asm/arch/smc_api.h>
#include <asm/arch/system_manager.h>
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <linux/iopoll.h>
+#include <linux/intel-smc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +58,15 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 arg = enable;
+
+ int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
+ if (ret) {
+ printf("SMC call failed with error %d in %s.\n", ret, __func__);
+ return;
+ }
+#else
u32 reg;
if (enable) {
@@ -101,6 +113,7 @@ void socfpga_bridges_reset(int enable)
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+#endif
}
/*
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 12/16] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (10 preceding siblings ...)
2020-10-01 9:16 ` [v2, 11/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 13/16] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() Siew Chin Lim
` (4 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
drivers/fpga/intel_sdm_mb.c | 139 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 9a1dc2c0c8..f5fd9a14c2 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -8,11 +8,149 @@
#include <log.h>
#include <watchdog.h>
#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/smc_api.h>
#include <linux/delay.h>
+#include <linux/intel-smc.h>
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#define BITSTREAM_CHUNK_SIZE 0xFFFF0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+ NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ return -ETIMEDOUT; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ WATCHDOG_RESET();
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bitstream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, ARRAY_SIZE(res_buf));
+ if (!ret) {
+ for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(20000);
+ }
+ WATCHDOG_RESET();
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+ u64 arg = 1;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bitstream(rbf_data, rbf_size);
+ if (ret) {
+ puts("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ puts("FPGA reconfiguration failed!");
+ return ret;
+ }
+
+ puts("FPGA reconfiguration OK!\n");
+
+ return ret;
+}
+
+#else
+
static const struct mbox_cfgstat_state {
int err_no;
const char *error_name;
@@ -286,3 +424,4 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
return ret;
}
+#endif
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 13/16] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (11 preceding siblings ...)
2020-10-01 9:16 ` [v2, 12/16] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 14/16] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM Siew Chin Lim
` (3 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 18d44924e6..429444f069 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -11,6 +11,7 @@
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/system_manager.h>
#include <asm/secure.h>
+#include <asm/system.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -398,6 +399,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -406,6 +410,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 14/16] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (12 preceding siblings ...)
2020-10-01 9:16 ` [v2, 13/16] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 15/16] arm: socfpga: soc64: Skip handoff data access in SSBL Siew Chin Lim
` (2 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Since SSBL is running in DRAM, it shall setup the stack in DRAM
instead of OCRAM which is occupied by SPL and handoff data.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
include/configs/socfpga_soc64_common.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index cb9bb21597..dadd21b0ba 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -40,9 +40,14 @@
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
+ CONFIG_SYS_INIT_RAM_SIZE \
- S10_HANDOFF_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \
+ + 0x100000)
+#endif
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 15/16] arm: socfpga: soc64: Skip handoff data access in SSBL
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (13 preceding siblings ...)
2020-10-01 9:16 ` [v2, 14/16] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 9:16 ` [v2, 16/16] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim
2020-10-01 16:52 ` [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Michal Simek
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 3da85791a1..049c5711a8 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -12,6 +12,7 @@
const struct cm_config * const cm_get_default_config(void)
{
+#ifdef CONFIG_SPL_BUILD
struct cm_config *cm_handoff_cfg = (struct cm_config *)
(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
u32 *conversion = (u32 *)cm_handoff_cfg;
@@ -26,7 +27,7 @@ const struct cm_config * const cm_get_default_config(void)
} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
return cm_handoff_cfg;
}
-
+#endif
return NULL;
}
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 16/16] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (14 preceding siblings ...)
2020-10-01 9:16 ` [v2, 15/16] arm: socfpga: soc64: Skip handoff data access in SSBL Siew Chin Lim
@ 2020-10-01 9:16 ` Siew Chin Lim
2020-10-01 16:52 ` [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Michal Simek
16 siblings, 0 replies; 22+ messages in thread
From: Siew Chin Lim @ 2020-10-01 9:16 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Booting Agilex and Stratix 10 with ATF support.
SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:
SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)
U-Boot proper now starts at 0x200000 (CONFIG_SYS_TEXT_BASE).
ATF will occupy the address range starting from 0x1000.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
v2:
- Add CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
- Move board/altera/soc64/fit_spl_atf.sh to
board/intel/soc64/fit_spl_atf.sh
---
configs/socfpga_agilex_atf_defconfig | 72 ++++++++++++++++++++++++++++++++
configs/socfpga_stratix10_atf_defconfig | 74 +++++++++++++++++++++++++++++++++
2 files changed, 146 insertions(+)
create mode 100644 configs/socfpga_agilex_atf_defconfig
create mode 100644 configs/socfpga_stratix10_atf_defconfig
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
new file mode 100644
index 0000000000..73ca8d1cca
--- /dev/null
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -0,0 +1,72 @@
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_DM_GPIO=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_agilex"
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+CONFIG_SPL_FIT_GENERATOR="board/intel/soc64/fit_spl_atf.sh"
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon"
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_PANIC_HANG=y
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
new file mode 100644
index 0000000000..e0b9c6964c
--- /dev/null
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_DM_GPIO=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_stratix10"
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+CONFIG_SPL_FIT_GENERATOR="board/intel/soc64/fit_spl_atf.sh"
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon"
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_FPGA_INTEL_PR=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_PANIC_HANG=y
--
2.13.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [v2, 00/16] Enable ARM Trusted Firmware for U-Boot
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
` (15 preceding siblings ...)
2020-10-01 9:16 ` [v2, 16/16] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim
@ 2020-10-01 16:52 ` Michal Simek
2020-10-01 18:37 ` Simon Glass
16 siblings, 1 reply; 22+ messages in thread
From: Michal Simek @ 2020-10-01 16:52 UTC (permalink / raw)
To: u-boot
On 01. 10. 20 11:15, Siew Chin Lim wrote:
> This is the 2nd version of patchset to Enable ARM Trusted Firmware
> for U-Boot.
>
> New U-boot flow with ARM Trusted Firmware (ATF) support:
> SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
>
> SPL loads the u-boot.itb which consist of:
> 1) u-boot-nodtb.bin (U-Boot Proper image)
> 2) u-boot.dtb (U-Boot Proper DTB)
> 3) bl31.bin (ATF-BL31 image)
>
> Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex)
>
> Patch status:
> Have changes: Patch 2, 8, 9, 10, 11, 16
> Other patches unchanged.
>
> Detail changelog can find in commit message.
>
> v1->v2:
> --------
> Patch 2:
> - Move soc64 folder from board/altera to board/intel folder
>
> Patch 8:
> - Updated comments
>
> Patch 9:
> - Code clean up without functionality change
>
> Patch 10:
> - Code clean up without functionality change
>
> Patch 11:
> - Print error message and return instead of hang in socfpga_bridges_reset()
> when SMC call is failing.
>
> Patch 16:
> - Add CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
> - Move board/altera/soc64/fit_spl_atf.sh to board/intel/soc64/fit_spl_atf.sh
>
> History:
> --------
> [v1]: https://patchwork.ozlabs.org/project/uboot/list/?series=195854
>
>
> These patchsets have dependency on:
> arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
> https://lists.denx.de/pipermail/u-boot/2020-August/423029.html
>
> Rename Stratix10 FPGA driver and support Agilex
> https://lists.denx.de/pipermail/u-boot/2020-August/422798.html
>
> SoCFPGA mailbox driver fixes and enhancements
> https://lists.denx.de/pipermail/u-boot/2020-August/423140.html
>
> arm: socfpga: soc64: Initialize timer in SPL only
> https://lists.denx.de/pipermail/u-boot/2020-July/419692.html
>
> arm: socfpga: soc64: Remove PHY interface setup from misc arch init
> https://lists.denx.de/pipermail/u-boot/2020-July/419690.html
>
> Enable sysreset support for SoCFPGA SoC64 platforms
> https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
>
> arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
> https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
>
> Chee Hong Ang (16):
> arm: socfpga: soc64: Remove CONFIG_OF_EMBED
> arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
> arm: socfpga: Add function for checking description from FIT image
> arm: socfpga: soc64: Load FIT image with ATF support
> arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
> arm: socfpga: Disable "spin-table" method for booting Linux
> arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
> (64bits)
> arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
> services
> mmc: dwmmc: socfpga: Add ATF support for MMC driver
> net: designware: socfpga: Add ATF support for MAC driver
> arm: socfpga: soc64: Add ATF support for Reset Manager driver
> arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
> arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
> mbox_reset_cold()
> arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
> arm: socfpga: soc64: Skip handoff data access in SSBL
> configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
> support
>
> arch/arm/mach-socfpga/Kconfig | 2 -
> arch/arm/mach-socfpga/Makefile | 4 +
> arch/arm/mach-socfpga/board.c | 12 +-
> arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
> arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++
> arch/arm/mach-socfpga/mailbox_s10.c | 5 +
> arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
> arch/arm/mach-socfpga/smc_api.c | 56 ++
> arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +-
> board/intel/soc64/fit_spl_atf.sh | 92 ++++
The patch
commit f4a43d292527ac671dee616ac973899d90a43401
Author: Simon Glass <sjg@chromium.org>
AuthorDate: Sun Jul 19 13:56:11 2020 -0600
Commit: Simon Glass <sjg@chromium.org>
CommitDate: Tue Jul 28 19:30:39 2020 -0600
Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR
Add warning to migrate to binman. It means do it directly.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
^ permalink raw reply [flat|nested] 22+ messages in thread
* [v2, 00/16] Enable ARM Trusted Firmware for U-Boot
2020-10-01 16:52 ` [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Michal Simek
@ 2020-10-01 18:37 ` Simon Glass
2020-10-01 18:48 ` Marek Vasut
0 siblings, 1 reply; 22+ messages in thread
From: Simon Glass @ 2020-10-01 18:37 UTC (permalink / raw)
To: u-boot
Hi Siew,
On Thu, 1 Oct 2020 at 10:52, Michal Simek <monstr@monstr.eu> wrote:
>
>
>
> On 01. 10. 20 11:15, Siew Chin Lim wrote:
> > This is the 2nd version of patchset to Enable ARM Trusted Firmware
> > for U-Boot.
> >
> > New U-boot flow with ARM Trusted Firmware (ATF) support:
> > SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
> >
> > SPL loads the u-boot.itb which consist of:
> > 1) u-boot-nodtb.bin (U-Boot Proper image)
> > 2) u-boot.dtb (U-Boot Proper DTB)
> > 3) bl31.bin (ATF-BL31 image)
> >
> > Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex)
> >
> > Patch status:
> > Have changes: Patch 2, 8, 9, 10, 11, 16
> > Other patches unchanged.
> >
> > Detail changelog can find in commit message.
> >
> > v1->v2:
> > --------
> > Patch 2:
> > - Move soc64 folder from board/altera to board/intel folder
> >
> > Patch 8:
> > - Updated comments
> >
> > Patch 9:
> > - Code clean up without functionality change
> >
> > Patch 10:
> > - Code clean up without functionality change
> >
> > Patch 11:
> > - Print error message and return instead of hang in socfpga_bridges_reset()
> > when SMC call is failing.
> >
> > Patch 16:
> > - Add CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
> > - Move board/altera/soc64/fit_spl_atf.sh to board/intel/soc64/fit_spl_atf.sh
> >
> > History:
> > --------
> > [v1]: https://patchwork.ozlabs.org/project/uboot/list/?series=195854
> >
> >
> > These patchsets have dependency on:
> > arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
> > https://lists.denx.de/pipermail/u-boot/2020-August/423029.html
> >
> > Rename Stratix10 FPGA driver and support Agilex
> > https://lists.denx.de/pipermail/u-boot/2020-August/422798.html
> >
> > SoCFPGA mailbox driver fixes and enhancements
> > https://lists.denx.de/pipermail/u-boot/2020-August/423140.html
> >
> > arm: socfpga: soc64: Initialize timer in SPL only
> > https://lists.denx.de/pipermail/u-boot/2020-July/419692.html
> >
> > arm: socfpga: soc64: Remove PHY interface setup from misc arch init
> > https://lists.denx.de/pipermail/u-boot/2020-July/419690.html
> >
> > Enable sysreset support for SoCFPGA SoC64 platforms
> > https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
> >
> > arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
> > https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
> >
> > Chee Hong Ang (16):
> > arm: socfpga: soc64: Remove CONFIG_OF_EMBED
> > arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
> > arm: socfpga: Add function for checking description from FIT image
> > arm: socfpga: soc64: Load FIT image with ATF support
> > arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
> > arm: socfpga: Disable "spin-table" method for booting Linux
> > arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
> > (64bits)
> > arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
> > services
> > mmc: dwmmc: socfpga: Add ATF support for MMC driver
> > net: designware: socfpga: Add ATF support for MAC driver
> > arm: socfpga: soc64: Add ATF support for Reset Manager driver
> > arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
> > arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
> > mbox_reset_cold()
> > arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
> > arm: socfpga: soc64: Skip handoff data access in SSBL
> > configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
> > support
> >
> > arch/arm/mach-socfpga/Kconfig | 2 -
> > arch/arm/mach-socfpga/Makefile | 4 +
> > arch/arm/mach-socfpga/board.c | 12 +-
> > arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
> > arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++
> > arch/arm/mach-socfpga/mailbox_s10.c | 5 +
> > arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
> > arch/arm/mach-socfpga/smc_api.c | 56 ++
> > arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +-
> > board/intel/soc64/fit_spl_atf.sh | 92 ++++
>
> The patch
>
> commit f4a43d292527ac671dee616ac973899d90a43401
> Author: Simon Glass <sjg@chromium.org>
> AuthorDate: Sun Jul 19 13:56:11 2020 -0600
> Commit: Simon Glass <sjg@chromium.org>
> CommitDate: Tue Jul 28 19:30:39 2020 -0600
>
> Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR
>
> Add warning to migrate to binman. It means do it directly.
>
Yes, no more scripts please.
Let me know if you need help.
Regards,
Simon
^ permalink raw reply [flat|nested] 22+ messages in thread
* [v2, 00/16] Enable ARM Trusted Firmware for U-Boot
2020-10-01 18:37 ` Simon Glass
@ 2020-10-01 18:48 ` Marek Vasut
2020-10-01 20:33 ` Tom Rini
2020-10-01 21:46 ` Simon Glass
0 siblings, 2 replies; 22+ messages in thread
From: Marek Vasut @ 2020-10-01 18:48 UTC (permalink / raw)
To: u-boot
On 10/1/20 8:37 PM, Simon Glass wrote:
> Hi Siew,
>
> On Thu, 1 Oct 2020 at 10:52, Michal Simek <monstr@monstr.eu> wrote:
>>
>>
>>
>> On 01. 10. 20 11:15, Siew Chin Lim wrote:
>>> This is the 2nd version of patchset to Enable ARM Trusted Firmware
>>> for U-Boot.
>>>
>>> New U-boot flow with ARM Trusted Firmware (ATF) support:
>>> SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
>>>
>>> SPL loads the u-boot.itb which consist of:
>>> 1) u-boot-nodtb.bin (U-Boot Proper image)
>>> 2) u-boot.dtb (U-Boot Proper DTB)
>>> 3) bl31.bin (ATF-BL31 image)
>>>
>>> Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex)
>>>
>>> Patch status:
>>> Have changes: Patch 2, 8, 9, 10, 11, 16
>>> Other patches unchanged.
>>>
>>> Detail changelog can find in commit message.
>>>
>>> v1->v2:
>>> --------
>>> Patch 2:
>>> - Move soc64 folder from board/altera to board/intel folder
>>>
>>> Patch 8:
>>> - Updated comments
>>>
>>> Patch 9:
>>> - Code clean up without functionality change
>>>
>>> Patch 10:
>>> - Code clean up without functionality change
>>>
>>> Patch 11:
>>> - Print error message and return instead of hang in socfpga_bridges_reset()
>>> when SMC call is failing.
>>>
>>> Patch 16:
>>> - Add CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
>>> - Move board/altera/soc64/fit_spl_atf.sh to board/intel/soc64/fit_spl_atf.sh
>>>
>>> History:
>>> --------
>>> [v1]: https://patchwork.ozlabs.org/project/uboot/list/?series=195854
>>>
>>>
>>> These patchsets have dependency on:
>>> arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
>>> https://lists.denx.de/pipermail/u-boot/2020-August/423029.html
>>>
>>> Rename Stratix10 FPGA driver and support Agilex
>>> https://lists.denx.de/pipermail/u-boot/2020-August/422798.html
>>>
>>> SoCFPGA mailbox driver fixes and enhancements
>>> https://lists.denx.de/pipermail/u-boot/2020-August/423140.html
>>>
>>> arm: socfpga: soc64: Initialize timer in SPL only
>>> https://lists.denx.de/pipermail/u-boot/2020-July/419692.html
>>>
>>> arm: socfpga: soc64: Remove PHY interface setup from misc arch init
>>> https://lists.denx.de/pipermail/u-boot/2020-July/419690.html
>>>
>>> Enable sysreset support for SoCFPGA SoC64 platforms
>>> https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
>>>
>>> arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
>>> https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
>>>
>>> Chee Hong Ang (16):
>>> arm: socfpga: soc64: Remove CONFIG_OF_EMBED
>>> arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
>>> arm: socfpga: Add function for checking description from FIT image
>>> arm: socfpga: soc64: Load FIT image with ATF support
>>> arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
>>> arm: socfpga: Disable "spin-table" method for booting Linux
>>> arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
>>> (64bits)
>>> arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
>>> services
>>> mmc: dwmmc: socfpga: Add ATF support for MMC driver
>>> net: designware: socfpga: Add ATF support for MAC driver
>>> arm: socfpga: soc64: Add ATF support for Reset Manager driver
>>> arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
>>> arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
>>> mbox_reset_cold()
>>> arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
>>> arm: socfpga: soc64: Skip handoff data access in SSBL
>>> configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
>>> support
>>>
>>> arch/arm/mach-socfpga/Kconfig | 2 -
>>> arch/arm/mach-socfpga/Makefile | 4 +
>>> arch/arm/mach-socfpga/board.c | 12 +-
>>> arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
>>> arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++
>>> arch/arm/mach-socfpga/mailbox_s10.c | 5 +
>>> arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
>>> arch/arm/mach-socfpga/smc_api.c | 56 ++
>>> arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +-
>>> board/intel/soc64/fit_spl_atf.sh | 92 ++++
>>
>> The patch
>>
>> commit f4a43d292527ac671dee616ac973899d90a43401
>> Author: Simon Glass <sjg@chromium.org>
>> AuthorDate: Sun Jul 19 13:56:11 2020 -0600
>> Commit: Simon Glass <sjg@chromium.org>
>> CommitDate: Tue Jul 28 19:30:39 2020 -0600
>>
>> Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR
>>
>> Add warning to migrate to binman. It means do it directly.
>>
>
> Yes, no more scripts please.
Does that mean we now have more, additional dependencies, instead of
plain bourne shell ?
^ permalink raw reply [flat|nested] 22+ messages in thread
* [v2, 00/16] Enable ARM Trusted Firmware for U-Boot
2020-10-01 18:48 ` Marek Vasut
@ 2020-10-01 20:33 ` Tom Rini
2020-10-01 21:46 ` Simon Glass
1 sibling, 0 replies; 22+ messages in thread
From: Tom Rini @ 2020-10-01 20:33 UTC (permalink / raw)
To: u-boot
On Thu, Oct 01, 2020 at 08:48:44PM +0200, Marek Vasut wrote:
> On 10/1/20 8:37 PM, Simon Glass wrote:
> > Hi Siew,
> >
> > On Thu, 1 Oct 2020 at 10:52, Michal Simek <monstr@monstr.eu> wrote:
> >>
> >>
> >>
> >> On 01. 10. 20 11:15, Siew Chin Lim wrote:
> >>> This is the 2nd version of patchset to Enable ARM Trusted Firmware
> >>> for U-Boot.
> >>>
> >>> New U-boot flow with ARM Trusted Firmware (ATF) support:
> >>> SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
> >>>
> >>> SPL loads the u-boot.itb which consist of:
> >>> 1) u-boot-nodtb.bin (U-Boot Proper image)
> >>> 2) u-boot.dtb (U-Boot Proper DTB)
> >>> 3) bl31.bin (ATF-BL31 image)
> >>>
> >>> Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex)
> >>>
> >>> Patch status:
> >>> Have changes: Patch 2, 8, 9, 10, 11, 16
> >>> Other patches unchanged.
> >>>
> >>> Detail changelog can find in commit message.
> >>>
> >>> v1->v2:
> >>> --------
> >>> Patch 2:
> >>> - Move soc64 folder from board/altera to board/intel folder
> >>>
> >>> Patch 8:
> >>> - Updated comments
> >>>
> >>> Patch 9:
> >>> - Code clean up without functionality change
> >>>
> >>> Patch 10:
> >>> - Code clean up without functionality change
> >>>
> >>> Patch 11:
> >>> - Print error message and return instead of hang in socfpga_bridges_reset()
> >>> when SMC call is failing.
> >>>
> >>> Patch 16:
> >>> - Add CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
> >>> - Move board/altera/soc64/fit_spl_atf.sh to board/intel/soc64/fit_spl_atf.sh
> >>>
> >>> History:
> >>> --------
> >>> [v1]: https://patchwork.ozlabs.org/project/uboot/list/?series=195854
> >>>
> >>>
> >>> These patchsets have dependency on:
> >>> arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
> >>> https://lists.denx.de/pipermail/u-boot/2020-August/423029.html
> >>>
> >>> Rename Stratix10 FPGA driver and support Agilex
> >>> https://lists.denx.de/pipermail/u-boot/2020-August/422798.html
> >>>
> >>> SoCFPGA mailbox driver fixes and enhancements
> >>> https://lists.denx.de/pipermail/u-boot/2020-August/423140.html
> >>>
> >>> arm: socfpga: soc64: Initialize timer in SPL only
> >>> https://lists.denx.de/pipermail/u-boot/2020-July/419692.html
> >>>
> >>> arm: socfpga: soc64: Remove PHY interface setup from misc arch init
> >>> https://lists.denx.de/pipermail/u-boot/2020-July/419690.html
> >>>
> >>> Enable sysreset support for SoCFPGA SoC64 platforms
> >>> https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
> >>>
> >>> arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
> >>> https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
> >>>
> >>> Chee Hong Ang (16):
> >>> arm: socfpga: soc64: Remove CONFIG_OF_EMBED
> >>> arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
> >>> arm: socfpga: Add function for checking description from FIT image
> >>> arm: socfpga: soc64: Load FIT image with ATF support
> >>> arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
> >>> arm: socfpga: Disable "spin-table" method for booting Linux
> >>> arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
> >>> (64bits)
> >>> arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
> >>> services
> >>> mmc: dwmmc: socfpga: Add ATF support for MMC driver
> >>> net: designware: socfpga: Add ATF support for MAC driver
> >>> arm: socfpga: soc64: Add ATF support for Reset Manager driver
> >>> arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
> >>> arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
> >>> mbox_reset_cold()
> >>> arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
> >>> arm: socfpga: soc64: Skip handoff data access in SSBL
> >>> configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
> >>> support
> >>>
> >>> arch/arm/mach-socfpga/Kconfig | 2 -
> >>> arch/arm/mach-socfpga/Makefile | 4 +
> >>> arch/arm/mach-socfpga/board.c | 12 +-
> >>> arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
> >>> arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++
> >>> arch/arm/mach-socfpga/mailbox_s10.c | 5 +
> >>> arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
> >>> arch/arm/mach-socfpga/smc_api.c | 56 ++
> >>> arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +-
> >>> board/intel/soc64/fit_spl_atf.sh | 92 ++++
> >>
> >> The patch
> >>
> >> commit f4a43d292527ac671dee616ac973899d90a43401
> >> Author: Simon Glass <sjg@chromium.org>
> >> AuthorDate: Sun Jul 19 13:56:11 2020 -0600
> >> Commit: Simon Glass <sjg@chromium.org>
> >> CommitDate: Tue Jul 28 19:30:39 2020 -0600
> >>
> >> Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR
> >>
> >> Add warning to migrate to binman. It means do it directly.
> >>
> >
> > Yes, no more scripts please.
>
> Does that mean we now have more, additional dependencies, instead of
> plain bourne shell ?
Yes, it means the tools we provide need to be used and re-used rather
than every SoC making an ad-hoc slightly different script to do almost
but not quite the same thing. Looking over patch #2, which introduces
the script here, I would expect it to be easy to enable the provided
generator instead.
--
Tom
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [v2, 00/16] Enable ARM Trusted Firmware for U-Boot
2020-10-01 18:48 ` Marek Vasut
2020-10-01 20:33 ` Tom Rini
@ 2020-10-01 21:46 ` Simon Glass
1 sibling, 0 replies; 22+ messages in thread
From: Simon Glass @ 2020-10-01 21:46 UTC (permalink / raw)
To: u-boot
Hi Marek,
On Thu, 1 Oct 2020 at 12:48, Marek Vasut <marex@denx.de> wrote:
>
> On 10/1/20 8:37 PM, Simon Glass wrote:
> > Hi Siew,
> >
> > On Thu, 1 Oct 2020 at 10:52, Michal Simek <monstr@monstr.eu> wrote:
> >>
> >>
> >>
> >> On 01. 10. 20 11:15, Siew Chin Lim wrote:
> >>> This is the 2nd version of patchset to Enable ARM Trusted Firmware
> >>> for U-Boot.
> >>>
> >>> New U-boot flow with ARM Trusted Firmware (ATF) support:
> >>> SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
> >>>
> >>> SPL loads the u-boot.itb which consist of:
> >>> 1) u-boot-nodtb.bin (U-Boot Proper image)
> >>> 2) u-boot.dtb (U-Boot Proper DTB)
> >>> 3) bl31.bin (ATF-BL31 image)
> >>>
> >>> Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex)
> >>>
> >>> Patch status:
> >>> Have changes: Patch 2, 8, 9, 10, 11, 16
> >>> Other patches unchanged.
> >>>
> >>> Detail changelog can find in commit message.
> >>>
> >>> v1->v2:
> >>> --------
> >>> Patch 2:
> >>> - Move soc64 folder from board/altera to board/intel folder
> >>>
> >>> Patch 8:
> >>> - Updated comments
> >>>
> >>> Patch 9:
> >>> - Code clean up without functionality change
> >>>
> >>> Patch 10:
> >>> - Code clean up without functionality change
> >>>
> >>> Patch 11:
> >>> - Print error message and return instead of hang in socfpga_bridges_reset()
> >>> when SMC call is failing.
> >>>
> >>> Patch 16:
> >>> - Add CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
> >>> - Move board/altera/soc64/fit_spl_atf.sh to board/intel/soc64/fit_spl_atf.sh
> >>>
> >>> History:
> >>> --------
> >>> [v1]: https://patchwork.ozlabs.org/project/uboot/list/?series=195854
> >>>
> >>>
> >>> These patchsets have dependency on:
> >>> arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
> >>> https://lists.denx.de/pipermail/u-boot/2020-August/423029.html
> >>>
> >>> Rename Stratix10 FPGA driver and support Agilex
> >>> https://lists.denx.de/pipermail/u-boot/2020-August/422798.html
> >>>
> >>> SoCFPGA mailbox driver fixes and enhancements
> >>> https://lists.denx.de/pipermail/u-boot/2020-August/423140.html
> >>>
> >>> arm: socfpga: soc64: Initialize timer in SPL only
> >>> https://lists.denx.de/pipermail/u-boot/2020-July/419692.html
> >>>
> >>> arm: socfpga: soc64: Remove PHY interface setup from misc arch init
> >>> https://lists.denx.de/pipermail/u-boot/2020-July/419690.html
> >>>
> >>> Enable sysreset support for SoCFPGA SoC64 platforms
> >>> https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
> >>>
> >>> arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
> >>> https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
> >>>
> >>> Chee Hong Ang (16):
> >>> arm: socfpga: soc64: Remove CONFIG_OF_EMBED
> >>> arm: socfpga: soc64: Add FIT generator script for pack itb with ATF
> >>> arm: socfpga: Add function for checking description from FIT image
> >>> arm: socfpga: soc64: Load FIT image with ATF support
> >>> arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
> >>> arm: socfpga: Disable "spin-table" method for booting Linux
> >>> arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
> >>> (64bits)
> >>> arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
> >>> services
> >>> mmc: dwmmc: socfpga: Add ATF support for MMC driver
> >>> net: designware: socfpga: Add ATF support for MAC driver
> >>> arm: socfpga: soc64: Add ATF support for Reset Manager driver
> >>> arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
> >>> arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
> >>> mbox_reset_cold()
> >>> arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
> >>> arm: socfpga: soc64: Skip handoff data access in SSBL
> >>> configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
> >>> support
> >>>
> >>> arch/arm/mach-socfpga/Kconfig | 2 -
> >>> arch/arm/mach-socfpga/Makefile | 4 +
> >>> arch/arm/mach-socfpga/board.c | 12 +-
> >>> arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
> >>> arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++
> >>> arch/arm/mach-socfpga/mailbox_s10.c | 5 +
> >>> arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
> >>> arch/arm/mach-socfpga/smc_api.c | 56 ++
> >>> arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +-
> >>> board/intel/soc64/fit_spl_atf.sh | 92 ++++
> >>
> >> The patch
> >>
> >> commit f4a43d292527ac671dee616ac973899d90a43401
> >> Author: Simon Glass <sjg@chromium.org>
> >> AuthorDate: Sun Jul 19 13:56:11 2020 -0600
> >> Commit: Simon Glass <sjg@chromium.org>
> >> CommitDate: Tue Jul 28 19:30:39 2020 -0600
> >>
> >> Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR
> >>
> >> Add warning to migrate to binman. It means do it directly.
> >>
> >
> > Yes, no more scripts please.
>
> Does that mean we now have more, additional dependencies, instead of
> plain bourne shell ?
Yes, binman is written in Python. So is dtoc, the tool that enables
smaller SPL binaries. I know it is a pain to have extra dependencies,
but a bunch of vendor-specific scripts, each slightly different,
generating a .dts file in bash is not great, IMO. In 5 years it could
really get out of hand.
Regards,
Simon
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2020-10-01 21:46 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-01 9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
2020-10-01 9:15 ` [v2, 01/16] arm: socfpga: soc64: Remove CONFIG_OF_EMBED Siew Chin Lim
2020-10-01 9:16 ` [v2, 02/16] arm: socfpga: soc64: Add FIT generator script for pack itb with ATF Siew Chin Lim
2020-10-01 9:16 ` [v2, 03/16] arm: socfpga: Add function for checking description from FIT image Siew Chin Lim
2020-10-01 9:16 ` [v2, 04/16] arm: socfpga: soc64: Load FIT image with ATF support Siew Chin Lim
2020-10-01 9:16 ` [v2, 05/16] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF Siew Chin Lim
2020-10-01 9:16 ` [v2, 06/16] arm: socfpga: Disable "spin-table" method for booting Linux Siew Chin Lim
2020-10-01 9:16 ` [v2, 07/16] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) Siew Chin Lim
2020-10-01 9:16 ` [v2, 08/16] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services Siew Chin Lim
2020-10-01 9:16 ` [v2, 09/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver Siew Chin Lim
2020-10-01 9:16 ` [v2, 10/16] net: designware: socfpga: Add ATF support for MAC driver Siew Chin Lim
2020-10-01 9:16 ` [v2, 11/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver Siew Chin Lim
2020-10-01 9:16 ` [v2, 12/16] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver Siew Chin Lim
2020-10-01 9:16 ` [v2, 13/16] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() Siew Chin Lim
2020-10-01 9:16 ` [v2, 14/16] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM Siew Chin Lim
2020-10-01 9:16 ` [v2, 15/16] arm: socfpga: soc64: Skip handoff data access in SSBL Siew Chin Lim
2020-10-01 9:16 ` [v2, 16/16] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim
2020-10-01 16:52 ` [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Michal Simek
2020-10-01 18:37 ` Simon Glass
2020-10-01 18:48 ` Marek Vasut
2020-10-01 20:33 ` Tom Rini
2020-10-01 21:46 ` Simon Glass
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