From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair Francis <Alistair.Francis@wdc.com>, Kito Cheng <kito.cheng@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Subject: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line Date: Wed, 18 Nov 2020 16:29:53 +0800 [thread overview] Message-ID: <20201118083044.13992-16-frank.chang@sifive.com> (raw) In-Reply-To: <20201118083044.13992-1-frank.chang@sifive.com> From: Kito Cheng <kito.cheng@sifive.com> B-extension is default off, use cpu rv32 or rv64 with x-b=true to enable B-extension. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f4574..bc29e118c6d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_h) { target_misa |= RVH; } + if (cpu->cfg.ext_b) { + target_misa |= RVB; + } if (cpu->cfg.ext_v) { target_misa |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de4705bb578..c1c77c58a87 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVB RV('B') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -278,6 +279,7 @@ struct RISCVCPU { bool ext_f; bool ext_d; bool ext_c; + bool ext_b; bool ext_s; bool ext_u; bool ext_h; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Kito Cheng <kito.cheng@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Subject: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line Date: Wed, 18 Nov 2020 16:29:53 +0800 [thread overview] Message-ID: <20201118083044.13992-16-frank.chang@sifive.com> (raw) In-Reply-To: <20201118083044.13992-1-frank.chang@sifive.com> From: Kito Cheng <kito.cheng@sifive.com> B-extension is default off, use cpu rv32 or rv64 with x-b=true to enable B-extension. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f4574..bc29e118c6d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_h) { target_misa |= RVH; } + if (cpu->cfg.ext_b) { + target_misa |= RVB; + } if (cpu->cfg.ext_v) { target_misa |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de4705bb578..c1c77c58a87 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVB RV('B') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -278,6 +279,7 @@ struct RISCVCPU { bool ext_f; bool ext_d; bool ext_c; + bool ext_b; bool ext_s; bool ext_u; bool ext_h; -- 2.17.1
next prev parent reply other threads:[~2020-11-18 8:46 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-18 8:29 [RFC 00/15] support subsets of bitmanip extension frank.chang 2020-11-18 8:29 ` [RFC 01/15] target/riscv: reformat @sh format encoding for B-extension frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:03 ` Richard Henderson 2020-11-19 19:03 ` Richard Henderson 2020-11-18 8:29 ` [RFC 02/15] target/riscv: rvb: count leading/trailing zeros frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:24 ` Richard Henderson 2020-11-19 19:24 ` Richard Henderson 2020-11-19 19:48 ` Richard Henderson 2020-11-19 19:48 ` Richard Henderson 2020-11-18 8:29 ` [RFC 03/15] target/riscv: rvb: count bits set frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:27 ` Richard Henderson 2020-11-19 19:27 ` Richard Henderson 2020-11-18 8:29 ` [RFC 04/15] target/riscv: rvb: logic-with-negate frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:28 ` Richard Henderson 2020-11-19 19:28 ` Richard Henderson 2020-11-18 8:29 ` [RFC 05/15] target/riscv: rvb: pack two words into one register frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:43 ` Richard Henderson 2020-11-19 19:43 ` Richard Henderson 2020-11-18 8:29 ` [RFC 06/15] target/riscv: rvb: min/max instructions frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:46 ` Richard Henderson 2020-11-19 19:46 ` Richard Henderson 2020-11-18 8:29 ` [RFC 07/15] target/riscv: rvb: sign-extend instructions frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:48 ` Richard Henderson 2020-11-19 19:48 ` Richard Henderson 2020-11-18 8:29 ` [RFC 08/15] target/riscv: rvb: single-bit instructions frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 20:05 ` Richard Henderson 2020-11-19 20:05 ` Richard Henderson 2020-11-19 20:35 ` Richard Henderson 2020-11-19 20:35 ` Richard Henderson 2020-11-19 21:04 ` Richard Henderson 2020-11-19 21:04 ` Richard Henderson 2020-12-04 17:10 ` Frank Chang 2020-12-04 17:10 ` Frank Chang 2020-11-18 8:29 ` [RFC 09/15] target/riscv: rvb: shift ones frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 20:54 ` Richard Henderson 2020-11-19 20:54 ` Richard Henderson 2020-11-18 8:29 ` [RFC 10/15] target/riscv: rvb: rotate (left/right) frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:06 ` Richard Henderson 2020-11-19 21:06 ` Richard Henderson 2020-11-18 8:29 ` [RFC 11/15] target/riscv: rvb: generalized reverse frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:24 ` Richard Henderson 2020-11-19 21:24 ` Richard Henderson 2020-11-18 8:29 ` [RFC 12/15] target/riscv: rvb: generalized or-combine frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:28 ` Richard Henderson 2020-11-19 21:28 ` Richard Henderson 2020-11-18 8:29 ` [RFC 13/15] target/riscv: rvb: address calculation frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:38 ` Richard Henderson 2020-11-19 21:38 ` Richard Henderson 2020-11-18 8:29 ` [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 22:15 ` Richard Henderson 2020-11-19 22:15 ` Richard Henderson 2020-11-18 8:29 ` frank.chang [this message] 2020-11-18 8:29 ` [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line frank.chang 2020-11-19 18:54 ` Alistair Francis 2020-11-19 18:54 ` Alistair Francis 2020-11-20 3:02 ` Kito Cheng 2020-11-20 3:02 ` Kito Cheng 2020-11-20 16:24 ` Alistair Francis 2020-11-20 16:24 ` Alistair Francis 2020-11-23 1:22 ` Frank Chang 2020-11-23 1:22 ` Frank Chang 2020-11-19 22:26 ` [RFC 00/15] support subsets of bitmanip extension Richard Henderson 2020-11-20 1:45 ` Frank Chang 2020-11-20 1:45 ` Frank Chang
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