From: Richard Henderson <richard.henderson@linaro.org> To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Kito Cheng <kito.cheng@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu> Subject: Re: [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend Date: Thu, 19 Nov 2020 14:15:24 -0800 [thread overview] Message-ID: <3f4a11d5-97e0-75c7-75e8-f4f0a9bdd46e@linaro.org> (raw) In-Reply-To: <20201118083044.13992-15-frank.chang@sifive.com> On 11/18/20 12:29 AM, frank.chang@sifive.com wrote: > +addwu 0000101 .......... 000 ..... 0111011 @r > +subwu 0100101 .......... 000 ..... 0111011 @r > +addu_w 0000100 .......... 000 ..... 0111011 @r > > sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 > sbclriw 0100100 .......... 001 ..... 0011011 @sh5 > @@ -116,3 +119,7 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5 > roriw 0110000 .......... 101 ..... 0011011 @sh5 > greviw 0110100 .......... 101 ..... 0011011 @sh5 > gorciw 0010100 .......... 101 ..... 0011011 @sh5 > + > +addiwu ................. 100 ..... 0011011 @i > + > +slliu_w 000010 ........... 001 ..... 0011011 @sh addwu, subwu, addiwu have been removed in the current draft. > +static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a) > +{ > + TCGv source1; > + source1 = tcg_temp_new(); > + gen_get_gpr(source1, a->rs1); > + > + tcg_gen_ext32u_tl(source1, source1); > + tcg_gen_shli_tl(source1, source1, a->shamt); > + gen_set_gpr(a->rd, source1); if (a->shamt < 32) { tcg_gen_deposit_z_i64(source1, source1, a->shamt, 32); } else { tcg_gen_shli_i64(source1, source1, a->shamt); } r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org> To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Kito Cheng <kito.cheng@sifive.com> Subject: Re: [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend Date: Thu, 19 Nov 2020 14:15:24 -0800 [thread overview] Message-ID: <3f4a11d5-97e0-75c7-75e8-f4f0a9bdd46e@linaro.org> (raw) In-Reply-To: <20201118083044.13992-15-frank.chang@sifive.com> On 11/18/20 12:29 AM, frank.chang@sifive.com wrote: > +addwu 0000101 .......... 000 ..... 0111011 @r > +subwu 0100101 .......... 000 ..... 0111011 @r > +addu_w 0000100 .......... 000 ..... 0111011 @r > > sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 > sbclriw 0100100 .......... 001 ..... 0011011 @sh5 > @@ -116,3 +119,7 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5 > roriw 0110000 .......... 101 ..... 0011011 @sh5 > greviw 0110100 .......... 101 ..... 0011011 @sh5 > gorciw 0010100 .......... 101 ..... 0011011 @sh5 > + > +addiwu ................. 100 ..... 0011011 @i > + > +slliu_w 000010 ........... 001 ..... 0011011 @sh addwu, subwu, addiwu have been removed in the current draft. > +static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a) > +{ > + TCGv source1; > + source1 = tcg_temp_new(); > + gen_get_gpr(source1, a->rs1); > + > + tcg_gen_ext32u_tl(source1, source1); > + tcg_gen_shli_tl(source1, source1, a->shamt); > + gen_set_gpr(a->rd, source1); if (a->shamt < 32) { tcg_gen_deposit_z_i64(source1, source1, a->shamt, 32); } else { tcg_gen_shli_i64(source1, source1, a->shamt); } r~
next prev parent reply other threads:[~2020-11-19 22:23 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-18 8:29 [RFC 00/15] support subsets of bitmanip extension frank.chang 2020-11-18 8:29 ` [RFC 01/15] target/riscv: reformat @sh format encoding for B-extension frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:03 ` Richard Henderson 2020-11-19 19:03 ` Richard Henderson 2020-11-18 8:29 ` [RFC 02/15] target/riscv: rvb: count leading/trailing zeros frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:24 ` Richard Henderson 2020-11-19 19:24 ` Richard Henderson 2020-11-19 19:48 ` Richard Henderson 2020-11-19 19:48 ` Richard Henderson 2020-11-18 8:29 ` [RFC 03/15] target/riscv: rvb: count bits set frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:27 ` Richard Henderson 2020-11-19 19:27 ` Richard Henderson 2020-11-18 8:29 ` [RFC 04/15] target/riscv: rvb: logic-with-negate frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:28 ` Richard Henderson 2020-11-19 19:28 ` Richard Henderson 2020-11-18 8:29 ` [RFC 05/15] target/riscv: rvb: pack two words into one register frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:43 ` Richard Henderson 2020-11-19 19:43 ` Richard Henderson 2020-11-18 8:29 ` [RFC 06/15] target/riscv: rvb: min/max instructions frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:46 ` Richard Henderson 2020-11-19 19:46 ` Richard Henderson 2020-11-18 8:29 ` [RFC 07/15] target/riscv: rvb: sign-extend instructions frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:48 ` Richard Henderson 2020-11-19 19:48 ` Richard Henderson 2020-11-18 8:29 ` [RFC 08/15] target/riscv: rvb: single-bit instructions frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 20:05 ` Richard Henderson 2020-11-19 20:05 ` Richard Henderson 2020-11-19 20:35 ` Richard Henderson 2020-11-19 20:35 ` Richard Henderson 2020-11-19 21:04 ` Richard Henderson 2020-11-19 21:04 ` Richard Henderson 2020-12-04 17:10 ` Frank Chang 2020-12-04 17:10 ` Frank Chang 2020-11-18 8:29 ` [RFC 09/15] target/riscv: rvb: shift ones frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 20:54 ` Richard Henderson 2020-11-19 20:54 ` Richard Henderson 2020-11-18 8:29 ` [RFC 10/15] target/riscv: rvb: rotate (left/right) frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:06 ` Richard Henderson 2020-11-19 21:06 ` Richard Henderson 2020-11-18 8:29 ` [RFC 11/15] target/riscv: rvb: generalized reverse frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:24 ` Richard Henderson 2020-11-19 21:24 ` Richard Henderson 2020-11-18 8:29 ` [RFC 12/15] target/riscv: rvb: generalized or-combine frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:28 ` Richard Henderson 2020-11-19 21:28 ` Richard Henderson 2020-11-18 8:29 ` [RFC 13/15] target/riscv: rvb: address calculation frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:38 ` Richard Henderson 2020-11-19 21:38 ` Richard Henderson 2020-11-18 8:29 ` [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 22:15 ` Richard Henderson [this message] 2020-11-19 22:15 ` Richard Henderson 2020-11-18 8:29 ` [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 18:54 ` Alistair Francis 2020-11-19 18:54 ` Alistair Francis 2020-11-20 3:02 ` Kito Cheng 2020-11-20 3:02 ` Kito Cheng 2020-11-20 16:24 ` Alistair Francis 2020-11-20 16:24 ` Alistair Francis 2020-11-23 1:22 ` Frank Chang 2020-11-23 1:22 ` Frank Chang 2020-11-19 22:26 ` [RFC 00/15] support subsets of bitmanip extension Richard Henderson 2020-11-20 1:45 ` Frank Chang 2020-11-20 1:45 ` Frank Chang
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