From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>, Frank Chang <frank.chang@sifive.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Kito Cheng <kito.cheng@sifive.com> Subject: [RFC 08/15] target/riscv: rvb: single-bit instructions Date: Wed, 18 Nov 2020 16:29:46 +0800 [thread overview] Message-ID: <20201118083044.13992-9-frank.chang@sifive.com> (raw) In-Reply-To: <20201118083044.13992-1-frank.chang@sifive.com> From: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Kito Cheng <kito.cheng@sifive.com> --- target/riscv/insn32-64.decode | 8 ++ target/riscv/insn32.decode | 9 ++ target/riscv/insn_trans/trans_rvb.c.inc | 90 ++++++++++++++ target/riscv/translate.c | 155 ++++++++++++++++++++++++ 4 files changed, 262 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 2f00f96e36b..92f3aaac3b6 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -94,3 +94,11 @@ pcntw 011000000010 ..... 001 ..... 0011011 @r2 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r +sbsetw 0010100 .......... 001 ..... 0111011 @r +sbclrw 0100100 .......... 001 ..... 0111011 @r +sbinvw 0110100 .......... 001 ..... 0111011 @r +sbextw 0100100 .......... 101 ..... 0111011 @r + +sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 +sbclriw 0100100 .......... 001 ..... 0011011 @sh5 +sbinviw 0110100 .......... 001 ..... 0011011 @sh5 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 626641333c6..69e542da19c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -611,3 +611,12 @@ min 0000101 .......... 100 ..... 0110011 @r minu 0000101 .......... 101 ..... 0110011 @r max 0000101 .......... 110 ..... 0110011 @r maxu 0000101 .......... 111 ..... 0110011 @r +sbset 0010100 .......... 001 ..... 0110011 @r +sbclr 0100100 .......... 001 ..... 0110011 @r +sbinv 0110100 .......... 001 ..... 0110011 @r +sbext 0100100 .......... 101 ..... 0110011 @r + +sbseti 001010 ........... 001 ..... 0010011 @sh +sbclri 010010 ........... 001 ..... 0010011 @sh +sbinvi 011010 ........... 001 ..... 0010011 @sh +sbexti 010010 ........... 101 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index bf15611f85a..dabf8e09c3d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) return gen_unary(ctx, a, &tcg_gen_ext16s_tl); } +static bool trans_sbset(DisasContext *ctx, arg_sbset *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbset); +} + +static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbset); +} + +static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbclr); +} + +static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbclr); +} + +static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbinv); +} + +static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbinv); +} + +static bool trans_sbext(DisasContext *ctx, arg_sbext *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbext); +} + +static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbext); +} + { /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -141,4 +189,46 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) return gen_arith(ctx, a, &gen_packuw); } +static bool trans_sbsetw(DisasContext *ctx, arg_sbsetw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbsetw); +} + +static bool trans_sbsetiw(DisasContext *ctx, arg_sbsetiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbsetw); +} + +static bool trans_sbclrw(DisasContext *ctx, arg_sbclrw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbclrw); +} + +static bool trans_sbclriw(DisasContext *ctx, arg_sbclriw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbclrw); +} + +static bool trans_sbinvw(DisasContext *ctx, arg_sbinvw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbinvw); +} + +static bool trans_sbinviw(DisasContext *ctx, arg_sbinviw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbinvw); +} + +static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbextw); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fb30ee83aa8..e7d9e4a1abf 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -647,6 +647,24 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, return true; } +static bool gen_arith_shamt_tl(DisasContext *ctx, arg_shift *a, + void (*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1, source2; + source1 = tcg_temp_new(); + source2 = tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + tcg_gen_movi_tl(source2, a->shamt); + + (*func)(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + #ifdef TARGET_RISCV64 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) { @@ -801,6 +819,74 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(higher); } +static void gen_sbop_shamt(TCGv ret, TCGv shamt) +{ + tcg_gen_andi_tl(ret, shamt, TARGET_LONG_BITS - 1); +} + +static void gen_sbop_common(TCGv ret, TCGv shamt) +{ + TCGv t; + t = tcg_temp_new(); + + gen_sbop_shamt(ret, shamt); + + tcg_gen_movi_tl(t, 1); + tcg_gen_shl_tl(ret, t, ret); + + tcg_temp_free(t); +} + +static void gen_sbset(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbop_common(mask, arg2); + + tcg_gen_or_tl(ret, arg1, mask); + + tcg_temp_free(mask); +} + +static void gen_sbclr(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbop_common(mask, arg2); + + tcg_gen_not_tl(mask, mask); + tcg_gen_and_tl(ret, arg1, mask); + + tcg_temp_free(mask); +} + +static void gen_sbinv(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbop_common(mask, arg2); + + tcg_gen_xor_tl(ret, arg1, mask); + + tcg_temp_free(mask); +} + +static void gen_sbext(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv shamt; + shamt = tcg_temp_new(); + + gen_sbop_shamt(shamt, arg2); + tcg_gen_shr_tl(ret, arg1, shamt); + + tcg_gen_andi_tl(ret, ret, 1); + + tcg_temp_free(shamt); +} + #ifdef TARGET_RISCV64 @@ -867,6 +953,75 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(higher); } +static void gen_sbopw_shamt(TCGv ret, TCGv shamt) +{ + tcg_gen_andi_tl(ret, shamt, 31); +} + +static void gen_sbopw_common(TCGv ret, TCGv shamt) +{ + TCGv t; + t = tcg_temp_new(); + + gen_sbopw_shamt(ret, shamt); + tcg_gen_movi_tl(t, 1); + tcg_gen_shl_tl(ret, t, ret); + + tcg_temp_free(t); +} + +static void gen_sbsetw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbopw_common(mask, arg2); + tcg_gen_or_tl(ret, arg1, mask); + + tcg_gen_ext32s_tl(ret, ret); + + tcg_temp_free(mask); +} + +static void gen_sbclrw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbopw_common(mask, arg2); + tcg_gen_not_tl(mask, mask); + tcg_gen_and_tl(ret, arg1, mask); + + tcg_gen_ext32s_tl(ret, ret); + + tcg_temp_free(mask); +} + +static void gen_sbinvw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbopw_common(mask, arg2); + tcg_gen_xor_tl(ret, arg1, mask); + + tcg_gen_ext32s_tl(ret, ret); + + tcg_temp_free(mask); +} + +static void gen_sbextw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv shamt; + shamt = tcg_temp_new(); + + gen_sbopw_shamt(shamt, arg2); + tcg_gen_shr_tl(ret, arg1, shamt); + tcg_gen_andi_tl(ret, ret, 1); + + tcg_temp_free(shamt); +} + #endif static bool gen_arith(DisasContext *ctx, arg_r *a, -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Kito Cheng <kito.cheng@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Frank Chang <frank.chang@sifive.com> Subject: [RFC 08/15] target/riscv: rvb: single-bit instructions Date: Wed, 18 Nov 2020 16:29:46 +0800 [thread overview] Message-ID: <20201118083044.13992-9-frank.chang@sifive.com> (raw) In-Reply-To: <20201118083044.13992-1-frank.chang@sifive.com> From: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Kito Cheng <kito.cheng@sifive.com> --- target/riscv/insn32-64.decode | 8 ++ target/riscv/insn32.decode | 9 ++ target/riscv/insn_trans/trans_rvb.c.inc | 90 ++++++++++++++ target/riscv/translate.c | 155 ++++++++++++++++++++++++ 4 files changed, 262 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 2f00f96e36b..92f3aaac3b6 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -94,3 +94,11 @@ pcntw 011000000010 ..... 001 ..... 0011011 @r2 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r +sbsetw 0010100 .......... 001 ..... 0111011 @r +sbclrw 0100100 .......... 001 ..... 0111011 @r +sbinvw 0110100 .......... 001 ..... 0111011 @r +sbextw 0100100 .......... 101 ..... 0111011 @r + +sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 +sbclriw 0100100 .......... 001 ..... 0011011 @sh5 +sbinviw 0110100 .......... 001 ..... 0011011 @sh5 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 626641333c6..69e542da19c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -611,3 +611,12 @@ min 0000101 .......... 100 ..... 0110011 @r minu 0000101 .......... 101 ..... 0110011 @r max 0000101 .......... 110 ..... 0110011 @r maxu 0000101 .......... 111 ..... 0110011 @r +sbset 0010100 .......... 001 ..... 0110011 @r +sbclr 0100100 .......... 001 ..... 0110011 @r +sbinv 0110100 .......... 001 ..... 0110011 @r +sbext 0100100 .......... 101 ..... 0110011 @r + +sbseti 001010 ........... 001 ..... 0010011 @sh +sbclri 010010 ........... 001 ..... 0010011 @sh +sbinvi 011010 ........... 001 ..... 0010011 @sh +sbexti 010010 ........... 101 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index bf15611f85a..dabf8e09c3d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) return gen_unary(ctx, a, &tcg_gen_ext16s_tl); } +static bool trans_sbset(DisasContext *ctx, arg_sbset *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbset); +} + +static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbset); +} + +static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbclr); +} + +static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbclr); +} + +static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbinv); +} + +static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbinv); +} + +static bool trans_sbext(DisasContext *ctx, arg_sbext *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbext); +} + +static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbext); +} + { /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -141,4 +189,46 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) return gen_arith(ctx, a, &gen_packuw); } +static bool trans_sbsetw(DisasContext *ctx, arg_sbsetw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbsetw); +} + +static bool trans_sbsetiw(DisasContext *ctx, arg_sbsetiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbsetw); +} + +static bool trans_sbclrw(DisasContext *ctx, arg_sbclrw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbclrw); +} + +static bool trans_sbclriw(DisasContext *ctx, arg_sbclriw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbclrw); +} + +static bool trans_sbinvw(DisasContext *ctx, arg_sbinvw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbinvw); +} + +static bool trans_sbinviw(DisasContext *ctx, arg_sbinviw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_sbinvw); +} + +static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sbextw); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fb30ee83aa8..e7d9e4a1abf 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -647,6 +647,24 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, return true; } +static bool gen_arith_shamt_tl(DisasContext *ctx, arg_shift *a, + void (*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1, source2; + source1 = tcg_temp_new(); + source2 = tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + tcg_gen_movi_tl(source2, a->shamt); + + (*func)(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + #ifdef TARGET_RISCV64 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) { @@ -801,6 +819,74 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(higher); } +static void gen_sbop_shamt(TCGv ret, TCGv shamt) +{ + tcg_gen_andi_tl(ret, shamt, TARGET_LONG_BITS - 1); +} + +static void gen_sbop_common(TCGv ret, TCGv shamt) +{ + TCGv t; + t = tcg_temp_new(); + + gen_sbop_shamt(ret, shamt); + + tcg_gen_movi_tl(t, 1); + tcg_gen_shl_tl(ret, t, ret); + + tcg_temp_free(t); +} + +static void gen_sbset(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbop_common(mask, arg2); + + tcg_gen_or_tl(ret, arg1, mask); + + tcg_temp_free(mask); +} + +static void gen_sbclr(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbop_common(mask, arg2); + + tcg_gen_not_tl(mask, mask); + tcg_gen_and_tl(ret, arg1, mask); + + tcg_temp_free(mask); +} + +static void gen_sbinv(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbop_common(mask, arg2); + + tcg_gen_xor_tl(ret, arg1, mask); + + tcg_temp_free(mask); +} + +static void gen_sbext(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv shamt; + shamt = tcg_temp_new(); + + gen_sbop_shamt(shamt, arg2); + tcg_gen_shr_tl(ret, arg1, shamt); + + tcg_gen_andi_tl(ret, ret, 1); + + tcg_temp_free(shamt); +} + #ifdef TARGET_RISCV64 @@ -867,6 +953,75 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(higher); } +static void gen_sbopw_shamt(TCGv ret, TCGv shamt) +{ + tcg_gen_andi_tl(ret, shamt, 31); +} + +static void gen_sbopw_common(TCGv ret, TCGv shamt) +{ + TCGv t; + t = tcg_temp_new(); + + gen_sbopw_shamt(ret, shamt); + tcg_gen_movi_tl(t, 1); + tcg_gen_shl_tl(ret, t, ret); + + tcg_temp_free(t); +} + +static void gen_sbsetw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbopw_common(mask, arg2); + tcg_gen_or_tl(ret, arg1, mask); + + tcg_gen_ext32s_tl(ret, ret); + + tcg_temp_free(mask); +} + +static void gen_sbclrw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbopw_common(mask, arg2); + tcg_gen_not_tl(mask, mask); + tcg_gen_and_tl(ret, arg1, mask); + + tcg_gen_ext32s_tl(ret, ret); + + tcg_temp_free(mask); +} + +static void gen_sbinvw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv mask; + mask = tcg_temp_new(); + + gen_sbopw_common(mask, arg2); + tcg_gen_xor_tl(ret, arg1, mask); + + tcg_gen_ext32s_tl(ret, ret); + + tcg_temp_free(mask); +} + +static void gen_sbextw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv shamt; + shamt = tcg_temp_new(); + + gen_sbopw_shamt(shamt, arg2); + tcg_gen_shr_tl(ret, arg1, shamt); + tcg_gen_andi_tl(ret, ret, 1); + + tcg_temp_free(shamt); +} + #endif static bool gen_arith(DisasContext *ctx, arg_r *a, -- 2.17.1
next prev parent reply other threads:[~2020-11-18 8:38 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-18 8:29 [RFC 00/15] support subsets of bitmanip extension frank.chang 2020-11-18 8:29 ` [RFC 01/15] target/riscv: reformat @sh format encoding for B-extension frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:03 ` Richard Henderson 2020-11-19 19:03 ` Richard Henderson 2020-11-18 8:29 ` [RFC 02/15] target/riscv: rvb: count leading/trailing zeros frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:24 ` Richard Henderson 2020-11-19 19:24 ` Richard Henderson 2020-11-19 19:48 ` Richard Henderson 2020-11-19 19:48 ` Richard Henderson 2020-11-18 8:29 ` [RFC 03/15] target/riscv: rvb: count bits set frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:27 ` Richard Henderson 2020-11-19 19:27 ` Richard Henderson 2020-11-18 8:29 ` [RFC 04/15] target/riscv: rvb: logic-with-negate frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:28 ` Richard Henderson 2020-11-19 19:28 ` Richard Henderson 2020-11-18 8:29 ` [RFC 05/15] target/riscv: rvb: pack two words into one register frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:43 ` Richard Henderson 2020-11-19 19:43 ` Richard Henderson 2020-11-18 8:29 ` [RFC 06/15] target/riscv: rvb: min/max instructions frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:46 ` Richard Henderson 2020-11-19 19:46 ` Richard Henderson 2020-11-18 8:29 ` [RFC 07/15] target/riscv: rvb: sign-extend instructions frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 19:48 ` Richard Henderson 2020-11-19 19:48 ` Richard Henderson 2020-11-18 8:29 ` frank.chang [this message] 2020-11-18 8:29 ` [RFC 08/15] target/riscv: rvb: single-bit instructions frank.chang 2020-11-19 20:05 ` Richard Henderson 2020-11-19 20:05 ` Richard Henderson 2020-11-19 20:35 ` Richard Henderson 2020-11-19 20:35 ` Richard Henderson 2020-11-19 21:04 ` Richard Henderson 2020-11-19 21:04 ` Richard Henderson 2020-12-04 17:10 ` Frank Chang 2020-12-04 17:10 ` Frank Chang 2020-11-18 8:29 ` [RFC 09/15] target/riscv: rvb: shift ones frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 20:54 ` Richard Henderson 2020-11-19 20:54 ` Richard Henderson 2020-11-18 8:29 ` [RFC 10/15] target/riscv: rvb: rotate (left/right) frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:06 ` Richard Henderson 2020-11-19 21:06 ` Richard Henderson 2020-11-18 8:29 ` [RFC 11/15] target/riscv: rvb: generalized reverse frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:24 ` Richard Henderson 2020-11-19 21:24 ` Richard Henderson 2020-11-18 8:29 ` [RFC 12/15] target/riscv: rvb: generalized or-combine frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:28 ` Richard Henderson 2020-11-19 21:28 ` Richard Henderson 2020-11-18 8:29 ` [RFC 13/15] target/riscv: rvb: address calculation frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 21:38 ` Richard Henderson 2020-11-19 21:38 ` Richard Henderson 2020-11-18 8:29 ` [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 22:15 ` Richard Henderson 2020-11-19 22:15 ` Richard Henderson 2020-11-18 8:29 ` [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line frank.chang 2020-11-18 8:29 ` frank.chang 2020-11-19 18:54 ` Alistair Francis 2020-11-19 18:54 ` Alistair Francis 2020-11-20 3:02 ` Kito Cheng 2020-11-20 3:02 ` Kito Cheng 2020-11-20 16:24 ` Alistair Francis 2020-11-20 16:24 ` Alistair Francis 2020-11-23 1:22 ` Frank Chang 2020-11-23 1:22 ` Frank Chang 2020-11-19 22:26 ` [RFC 00/15] support subsets of bitmanip extension Richard Henderson 2020-11-20 1:45 ` Frank Chang 2020-11-20 1:45 ` Frank Chang
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