From: "Larson, Bradley" <Bradley.Larson@amd.com> To: Rob Herring <robh@kernel.org>, Brad Larson <brad@pensando.io> Cc: "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>, "adrian.hunter@intel.com" <adrian.hunter@intel.com>, "alcooperx@gmail.com" <alcooperx@gmail.com>, "andy.shevchenko@gmail.com" <andy.shevchenko@gmail.com>, "arnd@arndb.de" <arnd@arndb.de>, "brijeshkumar.singh@amd.com" <brijeshkumar.singh@amd.com>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "gsomlo@gmail.com" <gsomlo@gmail.com>, "gerg@linux-m68k.org" <gerg@linux-m68k.org>, "krzk@kernel.org" <krzk@kernel.org>, "krzysztof.kozlowski+dt@linaro.org" <krzysztof.kozlowski+dt@linaro.org>, "lee.jones@linaro.org" <lee.jones@linaro.org>, "broonie@kernel.org" <broonie@kernel.org>, "yamada.masahiro@socionext.com" <yamada.masahiro@socionext.com>, "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>, "piotrs@cadence.com" <piotrs@cadence.com>, "p.yadav@ti.com" <p.yadav@ti.com>, "rdunlap@infradead.org" <rdunlap@infradead.org>, "samuel@sholland.org" <samuel@sholland.org>, "fancer.lancer@gmail.com" <fancer.lancer@gmail.com>, "Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>, "Lendacky, Thomas" <Thomas.Lendacky@amd.com>, "ulf.hansson@linaro.org" <ulf.hansson@linaro.org>, "will@kernel.org" <will@kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org> Subject: Re: [PATCH v6 06/17] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando Elba System Resource chip Date: Wed, 31 Aug 2022 23:01:27 +0000 [thread overview] Message-ID: <554f33b4-d235-5516-e8ff-5bf80d63a9b9@amd.com> (raw) In-Reply-To: <20220822142544.GA3770388-robh@kernel.org> On 8/22/22 7:25 AM, Rob Herring wrote: > On Sat, Aug 20, 2022 at 12:57:39PM -0700, Brad Larson wrote: >> From: Brad Larson <blarson@amd.com> >> >> Add support for the AMD Pensando Elba SoC System Resource chip >> using the SPI interface. The Elba SR is a Multi-function Device >> supporting device register access using CS0, smbus interface for >> FRU and board peripherals using CS1, dual Lattice I2C masters for >> transceiver management using CS2, and CS3 for flash access. >> >> Signed-off-by: Brad Larson <blarson@amd.com> >> --- >> .../bindings/mfd/amd,pensando-elbasr.yaml | 97 +++++++++++++++++++ >> 1 file changed, 97 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml >> >> diff --git a/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml >> new file mode 100644 >> index 000000000000..ded347c3352c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml >> @@ -0,0 +1,97 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fmfd%2Famd%2Cpensando-elbasr.yaml%23&data=05%7C01%7CBradley.Larson%40amd.com%7Cd02c183f9a29492180fb08da844a3458%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637967751571358185%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=WHkA6tPbaDanQuMSaAiWUG3fBTfDVlWXMdeaO5t%2F3Ok%3D&reserved=0 >> +$schema: https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7CBradley.Larson%40amd.com%7Cd02c183f9a29492180fb08da844a3458%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637967751571358185%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=FDig31luqeo4pOZXfuOAGiOLi0kVqFU8ExnBi5gorlY%3D&reserved=0 >> + >> +title: AMD Pensando Elba SoC Resource Controller bindings >> + >> +description: | >> + AMD Pensando Elba SoC Resource Controller is a set of >> + miscellaneous control/status registers accessed on CS0, >> + a designware i2c master/slave on CS1, a Lattice rd1173 >> + dual i2c master on CS2, and flash on CS3. The /dev interfaces >> + created are /dev/pensr0.<CS>. Hardware reset of the eMMC > /dev is a Linux thing and not relevant for the bindings. > Removed mention of the dev interfaces >> + is implemented by a sub-device reset-controller which accesses >> + a CS0 control register. >> + >> +maintainers: >> + - Brad Larson <blarson@amd.com> >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - amd,pensando-elbasr >> + >> + spi-max-frequency: >> + description: Maximum SPI frequency of the device in Hz. > No need for generic descriptions of common properties. Changed to "spi-max-frequency: true" and moved to end of properties. >> + >> + reg: >> + maxItems: 1 >> + >> + '#address-cells': >> + const: 1 >> + >> + '#size-cells': >> + const: 0 >> + >> + interrupts: >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + - spi-max-frequency >> + >> +patternProperties: >> + '^reset-controller@[a-f0-9]+$': >> + $ref: /schemas/reset/amd,pensando-elbasr-reset.yaml >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> + spi { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + num-cs = <4>; >> + >> + sysc: system-controller@0 { >> + compatible = "amd,pensando-elbasr"; >> + reg = <0>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + spi-max-frequency = <12000000>; >> + >> + rstc: reset-controller@0 { >> + compatible = "amd,pensando-elbasr-reset"; >> + reg = <0>; > What does 0 represent here? A register address within 'elbasr' device? Removed, I recall a check threw a warning or error without reg. > Why do you need a child node for this? Are there other sub-devices and > your binding is incomplete? Just put '#reset-cells' in the parent. Without a reset-controller node and booting the function __of_reset_control_get(...) fails to find a match in the list here list_for_each_entry(r, &reset_controller_list, list) { if (args.np == r->of_node) { rcdev = r; break; } } where in sdhci_cdns_probe(...) this lookup fails priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, "hw"); which results in a non-functioning mmc hardware reset. >> + #reset-cells = <1>; >> + }; >> + }; >> + >> + i2c1: i2c@1 { >> + compatible = "amd,pensando-elbasr"; > You can't reuse the same compatible to represent different things. Changed to system-controller@1 and adjusted description above >> + reg = <1>; >> + spi-max-frequency = <12000000>; >> + }; >> + >> + i2c2: i2c@2 { >> + compatible = "amd,pensando-elbasr"; > As this is a Lattice RD1173, I would expect a compatible based on that. > Same as above, changed this to system-controller@2 >> + reg = <2>; >> + spi-max-frequency = <12000000>; >> + interrupt-parent = <&porta>; >> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; >> + }; >> + >> + flash@3 { >> + compatible = "amd,pensando-elbasr"; > Isn't this a flash device? A userspace utility understands how to program this internal flash. Changed to system-controller@3 Regards, Brad
WARNING: multiple messages have this Message-ID (diff)
From: "Larson, Bradley" <Bradley.Larson@amd.com> To: Rob Herring <robh@kernel.org>, Brad Larson <brad@pensando.io> Cc: "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>, "adrian.hunter@intel.com" <adrian.hunter@intel.com>, "alcooperx@gmail.com" <alcooperx@gmail.com>, "andy.shevchenko@gmail.com" <andy.shevchenko@gmail.com>, "arnd@arndb.de" <arnd@arndb.de>, "brijeshkumar.singh@amd.com" <brijeshkumar.singh@amd.com>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "gsomlo@gmail.com" <gsomlo@gmail.com>, "gerg@linux-m68k.org" <gerg@linux-m68k.org>, "krzk@kernel.org" <krzk@kernel.org>, "krzysztof.kozlowski+dt@linaro.org" <krzysztof.kozlowski+dt@linaro.org>, "lee.jones@linaro.org" <lee.jones@linaro.org>, "broonie@kernel.org" <broonie@kernel.org>, "yamada.masahiro@socionext.com" <yamada.masahiro@socionext.com>, "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>, "piotrs@cadence.com" <piotrs@cadence.com>, "p.yadav@ti.com" <p.yadav@ti.com>, "rdunlap@infradead.org" <rdunlap@infradead.org>, "samuel@sholland.org" <samuel@sholland.org>, "fancer.lancer@gmail.com" <fancer.lancer@gmail.com>, "Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>, "Lendacky, Thomas" <Thomas.Lendacky@amd.com>, "ulf.hansson@linaro.org" <ulf.hansson@linaro.org>, "will@kernel.org" <will@kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org> Subject: Re: [PATCH v6 06/17] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando Elba System Resource chip Date: Wed, 31 Aug 2022 23:01:27 +0000 [thread overview] Message-ID: <554f33b4-d235-5516-e8ff-5bf80d63a9b9@amd.com> (raw) In-Reply-To: <20220822142544.GA3770388-robh@kernel.org> On 8/22/22 7:25 AM, Rob Herring wrote: > On Sat, Aug 20, 2022 at 12:57:39PM -0700, Brad Larson wrote: >> From: Brad Larson <blarson@amd.com> >> >> Add support for the AMD Pensando Elba SoC System Resource chip >> using the SPI interface. The Elba SR is a Multi-function Device >> supporting device register access using CS0, smbus interface for >> FRU and board peripherals using CS1, dual Lattice I2C masters for >> transceiver management using CS2, and CS3 for flash access. >> >> Signed-off-by: Brad Larson <blarson@amd.com> >> --- >> .../bindings/mfd/amd,pensando-elbasr.yaml | 97 +++++++++++++++++++ >> 1 file changed, 97 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml >> >> diff --git a/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml >> new file mode 100644 >> index 000000000000..ded347c3352c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml >> @@ -0,0 +1,97 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fmfd%2Famd%2Cpensando-elbasr.yaml%23&data=05%7C01%7CBradley.Larson%40amd.com%7Cd02c183f9a29492180fb08da844a3458%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637967751571358185%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=WHkA6tPbaDanQuMSaAiWUG3fBTfDVlWXMdeaO5t%2F3Ok%3D&reserved=0 >> +$schema: https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7CBradley.Larson%40amd.com%7Cd02c183f9a29492180fb08da844a3458%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637967751571358185%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=FDig31luqeo4pOZXfuOAGiOLi0kVqFU8ExnBi5gorlY%3D&reserved=0 >> + >> +title: AMD Pensando Elba SoC Resource Controller bindings >> + >> +description: | >> + AMD Pensando Elba SoC Resource Controller is a set of >> + miscellaneous control/status registers accessed on CS0, >> + a designware i2c master/slave on CS1, a Lattice rd1173 >> + dual i2c master on CS2, and flash on CS3. The /dev interfaces >> + created are /dev/pensr0.<CS>. Hardware reset of the eMMC > /dev is a Linux thing and not relevant for the bindings. > Removed mention of the dev interfaces >> + is implemented by a sub-device reset-controller which accesses >> + a CS0 control register. >> + >> +maintainers: >> + - Brad Larson <blarson@amd.com> >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - amd,pensando-elbasr >> + >> + spi-max-frequency: >> + description: Maximum SPI frequency of the device in Hz. > No need for generic descriptions of common properties. Changed to "spi-max-frequency: true" and moved to end of properties. >> + >> + reg: >> + maxItems: 1 >> + >> + '#address-cells': >> + const: 1 >> + >> + '#size-cells': >> + const: 0 >> + >> + interrupts: >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + - spi-max-frequency >> + >> +patternProperties: >> + '^reset-controller@[a-f0-9]+$': >> + $ref: /schemas/reset/amd,pensando-elbasr-reset.yaml >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> + spi { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + num-cs = <4>; >> + >> + sysc: system-controller@0 { >> + compatible = "amd,pensando-elbasr"; >> + reg = <0>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + spi-max-frequency = <12000000>; >> + >> + rstc: reset-controller@0 { >> + compatible = "amd,pensando-elbasr-reset"; >> + reg = <0>; > What does 0 represent here? A register address within 'elbasr' device? Removed, I recall a check threw a warning or error without reg. > Why do you need a child node for this? Are there other sub-devices and > your binding is incomplete? Just put '#reset-cells' in the parent. Without a reset-controller node and booting the function __of_reset_control_get(...) fails to find a match in the list here list_for_each_entry(r, &reset_controller_list, list) { if (args.np == r->of_node) { rcdev = r; break; } } where in sdhci_cdns_probe(...) this lookup fails priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, "hw"); which results in a non-functioning mmc hardware reset. >> + #reset-cells = <1>; >> + }; >> + }; >> + >> + i2c1: i2c@1 { >> + compatible = "amd,pensando-elbasr"; > You can't reuse the same compatible to represent different things. Changed to system-controller@1 and adjusted description above >> + reg = <1>; >> + spi-max-frequency = <12000000>; >> + }; >> + >> + i2c2: i2c@2 { >> + compatible = "amd,pensando-elbasr"; > As this is a Lattice RD1173, I would expect a compatible based on that. > Same as above, changed this to system-controller@2 >> + reg = <2>; >> + spi-max-frequency = <12000000>; >> + interrupt-parent = <&porta>; >> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; >> + }; >> + >> + flash@3 { >> + compatible = "amd,pensando-elbasr"; > Isn't this a flash device? A userspace utility understands how to program this internal flash. Changed to system-controller@3 Regards, Brad _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-08-31 23:01 UTC|newest] Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-20 19:57 [PATCH v6 00/17] Support AMD Pensando Elba SoC Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-20 19:57 ` [PATCH v6 01/17] dt-bindings: arm: add AMD Pensando boards Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-22 18:15 ` Krzysztof Kozlowski 2022-08-22 18:15 ` Krzysztof Kozlowski 2022-08-31 22:40 ` Larson, Bradley 2022-08-31 22:40 ` Larson, Bradley 2022-08-20 19:57 ` [PATCH v6 02/17] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-22 21:29 ` Rob Herring 2022-08-22 21:29 ` Rob Herring 2022-08-31 22:36 ` Larson, Bradley 2022-08-31 22:36 ` Larson, Bradley 2022-08-20 19:57 ` [PATCH v6 03/17] dt-bindings: spi: cdns: Add compatible for " Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-22 18:22 ` Krzysztof Kozlowski 2022-08-22 18:22 ` Krzysztof Kozlowski 2022-08-31 18:37 ` Larson, Bradley 2022-08-31 18:37 ` Larson, Bradley 2022-08-20 19:57 ` [PATCH v6 04/17] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller bindings Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-21 17:49 ` Serge Semin 2022-08-21 17:49 ` Serge Semin 2022-08-31 18:28 ` Larson, Bradley 2022-08-31 18:28 ` Larson, Bradley 2022-09-11 18:34 ` Serge Semin 2022-09-11 18:34 ` Serge Semin 2022-09-14 18:47 ` Larson, Bradley 2022-09-14 18:47 ` Larson, Bradley 2022-08-22 18:19 ` Krzysztof Kozlowski 2022-08-22 18:19 ` Krzysztof Kozlowski 2022-08-31 18:45 ` Larson, Bradley 2022-08-31 18:45 ` Larson, Bradley 2022-08-20 19:57 ` [PATCH v6 05/17] dt-bindings: mfd: syscon: Add amd,pensando-elba-syscon compatible Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-22 18:23 ` Krzysztof Kozlowski 2022-08-22 18:23 ` Krzysztof Kozlowski 2022-08-31 18:35 ` Larson, Bradley 2022-08-31 18:35 ` Larson, Bradley 2022-08-20 19:57 ` [PATCH v6 06/17] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando Elba System Resource chip Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-21 20:21 ` Rob Herring 2022-08-21 20:21 ` Rob Herring 2022-08-22 14:25 ` Rob Herring 2022-08-22 14:25 ` Rob Herring 2022-08-31 23:01 ` Larson, Bradley [this message] 2022-08-31 23:01 ` Larson, Bradley 2022-09-01 7:20 ` Krzysztof Kozlowski 2022-09-01 7:20 ` Krzysztof Kozlowski 2022-09-01 20:37 ` Larson, Bradley 2022-09-01 20:37 ` Larson, Bradley 2022-09-08 11:27 ` Krzysztof Kozlowski 2022-09-08 11:27 ` Krzysztof Kozlowski 2022-09-13 21:57 ` Larson, Bradley 2022-09-13 21:57 ` Larson, Bradley 2022-09-16 9:56 ` Krzysztof Kozlowski 2022-09-16 9:56 ` Krzysztof Kozlowski 2022-09-29 22:50 ` Larson, Bradley 2022-09-29 22:50 ` Larson, Bradley 2022-10-07 15:53 ` Krzysztof Kozlowski 2022-10-07 15:53 ` Krzysztof Kozlowski 2022-08-20 19:57 ` [PATCH v6 07/17] dt-bindings: reset: amd,pensando-elbasr-reset: Add AMD Pensando SR Reset Controller bindings Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-21 20:21 ` Rob Herring 2022-08-21 20:21 ` Rob Herring 2022-08-20 19:57 ` [PATCH v6 08/17] MAINTAINERS: Add entry for AMD PENSANDO Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-20 19:57 ` [PATCH v6 09/17] arm64: Add config for AMD Pensando SoC platforms Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-20 19:57 ` [PATCH v6 10/17] arm64: dts: Add AMD Pensando Elba SoC support Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-09-30 7:27 ` Krzysztof Kozlowski 2022-09-30 7:27 ` Krzysztof Kozlowski 2022-10-04 19:46 ` Larson, Bradley 2022-10-04 19:46 ` Larson, Bradley 2022-08-20 19:57 ` [PATCH v6 11/17] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-20 19:57 ` [PATCH v6 12/17] spi: dw: Add support " Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-21 18:18 ` Serge Semin 2022-08-21 18:18 ` Serge Semin 2022-08-31 18:04 ` Larson, Bradley 2022-08-31 18:04 ` Larson, Bradley 2022-09-11 18:20 ` Serge Semin 2022-09-11 18:20 ` Serge Semin 2022-09-14 17:03 ` Larson, Bradley 2022-09-14 17:03 ` Larson, Bradley 2022-08-20 19:57 ` [PATCH v6 13/17] mmc: sdhci-cadence: Enable device specific override of writel() Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-20 19:57 ` [PATCH v6 14/17] mfd: pensando-elbasr: Add AMD Pensando Elba System Resource chip Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-20 19:57 ` [PATCH v6 15/17] reset: elbasr: Add AMD Pensando Elba SR Reset Controller Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-22 7:04 ` Philipp Zabel 2022-08-22 7:04 ` Philipp Zabel 2022-08-20 19:57 ` [PATCH v6 16/17] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-20 19:57 ` [PATCH v6 17/17] mmc: sdhci-cadence: Support mmc hardware reset Brad Larson 2022-08-20 19:57 ` Brad Larson 2022-08-22 7:03 ` Philipp Zabel 2022-08-22 7:03 ` Philipp Zabel 2022-08-31 22:49 ` Larson, Bradley 2022-08-31 22:49 ` Larson, Bradley 2022-08-22 10:53 ` Ulf Hansson 2022-08-22 10:53 ` Ulf Hansson 2022-08-22 12:25 ` Mark Brown 2022-08-22 12:25 ` Mark Brown 2022-08-31 23:29 ` Larson, Bradley 2022-08-31 23:29 ` Larson, Bradley
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