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From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Manasi Navare" <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+
Date: Wed, 13 Jan 2021 22:34:42 -0000	[thread overview]
Message-ID: <161057728272.11119.15295314724379066897@emeril.freedesktop.org> (raw)
In-Reply-To: <20210113220935.4151-1-manasi.d.navare@intel.com>

== Series Details ==

Series: VRR/Adaptive Sync Enabling on DP/eDP for TGL+
URL   : https://patchwork.freedesktop.org/series/85831/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9d81944ab3b3 drm/i915/display/vrr: Create VRR file and add VRR capability check
-:36: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#36: 
new file mode 100644

-:41: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_vrr.c', please use '//' instead
#41: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:1:
+/* SPDX-License-Identifier: MIT */

-:41: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#41: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:1:
+/* SPDX-License-Identifier: MIT */

-:82: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#82: FILE: drivers/gpu/drm/i915/display/intel_vrr.h:4:
+ * Copyright © 2019 Intel Corporation
+*/

total: 0 errors, 4 warnings, 0 checks, 62 lines checked
be5b431abcca drm/i915/display/dp: Attach and set drm connector VRR property
e42f3141b758 drm/i915: Store framestart_delay in dev_priv
7caaca7f5a5d drm/i915: Extract intel_mode_vblank_start()
762167321220 drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()
a07503674c3c drm/i915/display/dp: Compute VRR state in atomic_check
6bea0561c8ab drm/i915/display/dp: Do not enable PSR if VRR is enabled
0061e69b29f3 drm/i915/display: VRR + DRRS cannot be enabled together
-:22: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 0 checks, 9 lines checked
5729930e732b drm/i915: Rename VRR_CTL reg fields
1e53166817ac drm/i915/display/vrr: Configure and enable VRR in modeset enable
31bb5d8efd39 drm/i915/display/vrr: Send VRR push to flip the frame
259a9c3dcc00 drm/i915/display/vrr: Disable VRR in modeset disable path
510a51a72bed drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
b857d16e4dd6 drm/i915/display: Add HW state readout for VRR
-:55: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:164:
+		crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);

-:57: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#57: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:166:
+		crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;

total: 0 errors, 2 warnings, 0 checks, 46 lines checked
6185d7835cbe drm/i915/display: Helpers for VRR vblank min and max start
6a48576a1fa4 drm/i915: Add vrr state dump
96df6e91917c drm/i915: Fix vblank timestamps with VRR
-:11: WARNING:TYPO_SPELLING: 'minumum' may be misspelled - perhaps 'minimum'?
#11: 
off the scanline counter when it exceeds the minumum vtotal.
                                             ^^^^^^^

-:83: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#83: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:683:
+#define I915_MODE_FLAG_VRR (1<<6)
                              ^

-:138: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line (or did you mean 'else if'?)
#138: FILE: drivers/gpu/drm/i915/i915_irq.c:909:
+	} if (use_scanline_counter) {

total: 1 errors, 1 warnings, 1 checks, 81 lines checked
ac9c147c77da drm/i915: Fix vblank evasion with vrr


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  parent reply	other threads:[~2021-01-13 22:34 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-13 22:09 [Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 02/18] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-21 22:32   ` Navare, Manasi
2021-01-22 12:20     ` Ville Syrjälä
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-21 22:36   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-21 22:52   ` Navare, Manasi
2021-01-21 23:07     ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Manasi Navare
2021-01-14 17:15   ` Ville Syrjälä
2021-01-21 22:58     ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields Manasi Navare
2021-01-21 22:59   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 14/18] drm/i915/display: Add HW state readout for VRR Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start Manasi Navare
2021-01-19 19:07   ` Ville Syrjälä
2021-01-21 23:00     ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-21 23:02   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-21 23:05   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-21 23:06   ` Navare, Manasi
2021-01-13 22:34 ` Patchwork [this message]
2021-01-13 22:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Patchwork
2021-01-13 23:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-19 18:59 ` [Intel-gfx] [PATCH v4 00/18] " Ville Syrjälä

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