From: "Navare, Manasi" <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()
Date: Thu, 21 Jan 2021 14:52:11 -0800 [thread overview]
Message-ID: <20210121225209.GB26331@labuser-Z97X-UD5H> (raw)
In-Reply-To: <20210113220935.4151-6-manasi.d.navare@intel.com>
On Wed, Jan 13, 2021 at 02:09:22PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract intel_crtc_scanlines_since_frame_timestamp() from
> __intel_get_crtc_scanline_from_timestamp(). We'll reuse this
> for VRR vblank timestamps.
I dont see the intel_crtc_scanlines_since_frame_timestamp() getting used
later in the series.
Should this be moved to the intel display poller rest of the patches you might have?
Manasi
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 38 +++++++++++++++++++++------------
> 1 file changed, 24 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index dd1971040bbc..8505ceca87d5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -718,25 +718,15 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
> return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));
> }
>
> -/*
> - * On certain encoders on certain platforms, pipe
> - * scanline register will not work to get the scanline,
> - * since the timings are driven from the PORT or issues
> - * with scanline register updates.
> - * This function will use Framestamp and current
> - * timestamp registers to calculate the scanline.
> - */
> -static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
> +static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct drm_vblank_crtc *vblank =
> &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
> const struct drm_display_mode *mode = &vblank->hwmode;
> - u32 vblank_start = mode->crtc_vblank_start;
> - u32 vtotal = mode->crtc_vtotal;
> u32 htotal = mode->crtc_htotal;
> u32 clock = mode->crtc_clock;
> - u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
> + u32 scan_prev_time, scan_curr_time, scan_post_time;
>
> /*
> * To avoid the race condition where we might cross into the
> @@ -763,8 +753,28 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
> PIPE_FRMTMSTMP(crtc->pipe));
> } while (scan_post_time != scan_prev_time);
>
> - scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
> - clock), 1000 * htotal);
> + return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
> + clock), 1000 * htotal);
> +}
> +
> +/*
> + * On certain encoders on certain platforms, pipe
> + * scanline register will not work to get the scanline,
> + * since the timings are driven from the PORT or issues
> + * with scanline register updates.
> + * This function will use Framestamp and current
> + * timestamp registers to calculate the scanline.
> + */
> +static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
> +{
> + struct drm_vblank_crtc *vblank =
> + &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
> + const struct drm_display_mode *mode = &vblank->hwmode;
> + u32 vblank_start = mode->crtc_vblank_start;
> + u32 vtotal = mode->crtc_vtotal;
> + u32 scanline;
> +
> + scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
> scanline = min(scanline, vtotal - 1);
> scanline = (scanline + vblank_start) % vtotal;
>
> --
> 2.19.1
>
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> Intel-gfx@lists.freedesktop.org
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next prev parent reply other threads:[~2021-01-21 22:47 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-13 22:09 [Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 02/18] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-21 22:32 ` Navare, Manasi
2021-01-22 12:20 ` Ville Syrjälä
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-21 22:36 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-21 22:52 ` Navare, Manasi [this message]
2021-01-21 23:07 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Manasi Navare
2021-01-14 17:15 ` Ville Syrjälä
2021-01-21 22:58 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields Manasi Navare
2021-01-21 22:59 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 14/18] drm/i915/display: Add HW state readout for VRR Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start Manasi Navare
2021-01-19 19:07 ` Ville Syrjälä
2021-01-21 23:00 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-21 23:02 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-21 23:05 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-21 23:06 ` Navare, Manasi
2021-01-13 22:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Patchwork
2021-01-13 22:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-13 23:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-19 18:59 ` [Intel-gfx] [PATCH v4 00/18] " Ville Syrjälä
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