From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v4 02/18] drm/i915/display/dp: Attach and set drm connector VRR property
Date: Wed, 13 Jan 2021 14:09:19 -0800 [thread overview]
Message-ID: <20210113220935.4151-3-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20210113220935.4151-1-manasi.d.navare@intel.com>
From: Aditya Swarup <aditya.swarup@intel.com>
This function sets the VRR property for connector based
on the platform support, EDID monitor range and DP sink
DPCD capability of outputing video without msa
timing information.
v8:
* Use HAS_VRR, remove drm_conn declaration (Jani N)
* Fix typos in Comment (Jani N)
v7:
* Move the helper to separate file (Manasi)
v6:
* Remove unset of prop
v5:
* Fix the vrr prop not being set in kernel (Manasi)
* Unset the prop on connector disconnect (Manasi)
v4:
* Rebase (Mansi)
v3:
* intel_dp_is_vrr_capable can be used for debugfs, make it
non static (Manasi)
v2:
* Just set this in intel_dp_get_modes instead of new hook (Jani)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++
drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0433b6394137..dd093ae5b8bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -62,6 +62,7 @@
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
+#include "intel_vrr.h"
#define DP_DPRX_ESI_LEN 14
@@ -7235,6 +7236,10 @@ static int intel_dp_get_modes(struct drm_connector *connector)
edid = intel_connector->detect_edid;
if (edid) {
int ret = intel_connector_update_modes(connector, edid);
+
+ if (intel_vrr_is_capable(connector))
+ drm_connector_set_vrr_capable_property(connector,
+ true);
if (ret)
return ret;
}
@@ -7719,6 +7724,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
}
+
+ if (HAS_VRR(dev_priv))
+ drm_connector_attach_vrr_capable_property(connector);
}
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8a427c152341..869e41aa8396 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -20,10 +20,10 @@ bool intel_vrr_is_capable(struct drm_connector *connector)
intel_dp = intel_attached_dp(to_intel_connector(connector));
/*
- * DP Sink is capable of Variable refresh video timings if
+ * DP Sink is capable of VRR video timings if
* Ignore MSA bit is set in DPCD.
* EDID monitor range also should be atleast 10 for reasonable
- * Adaptive sync/ VRR end user experience.
+ * Adaptive Sync or Variable Refresh Rate end user experience.
*/
return HAS_VRR(i915) &&
drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
--
2.19.1
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next prev parent reply other threads:[~2021-01-13 22:05 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-13 22:09 [Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-13 22:09 ` Manasi Navare [this message]
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-21 22:32 ` Navare, Manasi
2021-01-22 12:20 ` Ville Syrjälä
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-21 22:36 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-21 22:52 ` Navare, Manasi
2021-01-21 23:07 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Manasi Navare
2021-01-14 17:15 ` Ville Syrjälä
2021-01-21 22:58 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields Manasi Navare
2021-01-21 22:59 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 14/18] drm/i915/display: Add HW state readout for VRR Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start Manasi Navare
2021-01-19 19:07 ` Ville Syrjälä
2021-01-21 23:00 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-21 23:02 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-21 23:05 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-21 23:06 ` Navare, Manasi
2021-01-13 22:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Patchwork
2021-01-13 22:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-13 23:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-19 18:59 ` [Intel-gfx] [PATCH v4 00/18] " Ville Syrjälä
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