intel-gfx.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together
Date: Wed, 13 Jan 2021 14:09:25 -0800	[thread overview]
Message-ID: <20210113220935.4151-9-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20210113220935.4151-1-manasi.d.navare@intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

If VRR is enabled, DRRS cannot be enabled, so make this check
in atomic check.
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a275303c0c5c..869a9d291e1b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2845,6 +2845,9 @@ intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
+	if (pipe_config->vrr.enable)
+		return;
+
 	/*
 	 * DRRS and PSR can't be enable together, so giving preference to PSR
 	 * as it allows more power-savings by complete shutting down display,
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-01-13 22:05 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-13 22:09 [Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 02/18] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-21 22:32   ` Navare, Manasi
2021-01-22 12:20     ` Ville Syrjälä
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-21 22:36   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-21 22:52   ` Navare, Manasi
2021-01-21 23:07     ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-13 22:09 ` Manasi Navare [this message]
2021-01-14 17:15   ` [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Ville Syrjälä
2021-01-21 22:58     ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields Manasi Navare
2021-01-21 22:59   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 14/18] drm/i915/display: Add HW state readout for VRR Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start Manasi Navare
2021-01-19 19:07   ` Ville Syrjälä
2021-01-21 23:00     ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-21 23:02   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-21 23:05   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-21 23:06   ` Navare, Manasi
2021-01-13 22:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Patchwork
2021-01-13 22:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-13 23:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-19 18:59 ` [Intel-gfx] [PATCH v4 00/18] " Ville Syrjälä

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210113220935.4151-9-manasi.d.navare@intel.com \
    --to=manasi.d.navare@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).