From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+
Date: Tue, 19 Jan 2021 20:59:41 +0200 [thread overview]
Message-ID: <YAcsHeudU0Xqx7ky@intel.com> (raw)
In-Reply-To: <20210113220935.4151-1-manasi.d.navare@intel.com>
On Wed, Jan 13, 2021 at 02:09:17PM -0800, Manasi Navare wrote:
> This series address review comments from Ville
> and incorporates some suggested fixes plus his
> patches.
>
> Aditya Swarup (1):
> drm/i915/display/dp: Attach and set drm connector VRR property
>
> Manasi Navare (8):
> drm/i915/display/vrr: Create VRR file and add VRR capability check
> drm/i915/display/dp: Compute VRR state in atomic_check
> drm/i915/display/dp: Do not enable PSR if VRR is enabled
> drm/i915/display/vrr: Configure and enable VRR in modeset enable
> drm/i915/display/vrr: Send VRR push to flip the frame
> drm/i915/display/vrr: Disable VRR in modeset disable path
> drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
> drm/i915/display: Add HW state readout for VRR
All of the above is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Ville Syrjälä (9):
> drm/i915: Store framestart_delay in dev_priv
> drm/i915: Extract intel_mode_vblank_start()
> drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()
> drm/i915/display: VRR + DRRS cannot be enabled together
> drm/i915: Rename VRR_CTL reg fields
> drm/i915/display: Helpers for VRR vblank min and max start
> drm/i915: Add vrr state dump
> drm/i915: Fix vblank timestamps with VRR
> drm/i915: Fix vblank evasion with vrr
>
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 24 ++
> drivers/gpu/drm/i915/display/intel_display.c | 58 +++--
> .../drm/i915/display/intel_display_types.h | 11 +
> drivers/gpu/drm/i915/display/intel_dp.c | 12 +
> .../drm/i915/display/intel_dp_link_training.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 7 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
> drivers/gpu/drm/i915/display/intel_vrr.c | 209 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.h | 33 +++
> drivers/gpu/drm/i915/i915_drv.h | 4 +
> drivers/gpu/drm/i915/i915_irq.c | 53 +++--
> drivers/gpu/drm/i915/i915_reg.h | 14 +-
> 13 files changed, 408 insertions(+), 41 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h
>
> --
> 2.19.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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prev parent reply other threads:[~2021-01-19 18:59 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-13 22:09 [Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 02/18] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-21 22:32 ` Navare, Manasi
2021-01-22 12:20 ` Ville Syrjälä
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-21 22:36 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-21 22:52 ` Navare, Manasi
2021-01-21 23:07 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Manasi Navare
2021-01-14 17:15 ` Ville Syrjälä
2021-01-21 22:58 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields Manasi Navare
2021-01-21 22:59 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 14/18] drm/i915/display: Add HW state readout for VRR Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start Manasi Navare
2021-01-19 19:07 ` Ville Syrjälä
2021-01-21 23:00 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-21 23:02 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-21 23:05 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-21 23:06 ` Navare, Manasi
2021-01-13 22:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Patchwork
2021-01-13 22:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-13 23:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-19 18:59 ` Ville Syrjälä [this message]
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