From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields
Date: Wed, 13 Jan 2021 14:09:26 -0800 [thread overview]
Message-ID: <20210113220935.4151-10-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20210113220935.4151-1-manasi.d.navare@intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Give the pipeline full line count bits more descriptive names
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 249a81575b9d..307c613cbc57 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4346,13 +4346,13 @@ enum {
#define _TRANS_VRR_CTL_B 0x61420
#define _TRANS_VRR_CTL_C 0x62420
#define _TRANS_VRR_CTL_D 0x63420
-#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
-#define VRR_CTL_VRR_ENABLE REG_BIT(31)
-#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
-#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
-#define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3)
-#define VRR_CTL_LINE_COUNT(x) REG_FIELD_PREP(VRR_CTL_LINE_COUNT_MASK, (x))
-#define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0)
+#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
+#define VRR_CTL_VRR_ENABLE REG_BIT(31)
+#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
+#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
+#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
+#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
+#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
#define _TRANS_VRR_VMAX_A 0x60424
#define _TRANS_VRR_VMAX_B 0x61424
--
2.19.1
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next prev parent reply other threads:[~2021-01-13 22:05 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-13 22:09 [Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 02/18] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-21 22:32 ` Navare, Manasi
2021-01-22 12:20 ` Ville Syrjälä
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-21 22:36 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-21 22:52 ` Navare, Manasi
2021-01-21 23:07 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Manasi Navare
2021-01-14 17:15 ` Ville Syrjälä
2021-01-21 22:58 ` Navare, Manasi
2021-01-13 22:09 ` Manasi Navare [this message]
2021-01-21 22:59 ` [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 14/18] drm/i915/display: Add HW state readout for VRR Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start Manasi Navare
2021-01-19 19:07 ` Ville Syrjälä
2021-01-21 23:00 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-21 23:02 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-21 23:05 ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-21 23:06 ` Navare, Manasi
2021-01-13 22:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Patchwork
2021-01-13 22:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-13 23:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-19 18:59 ` [Intel-gfx] [PATCH v4 00/18] " Ville Syrjälä
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