From: Borislav Petkov <bp@alien8.de>
To: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
tony.luck@intel.com, x86@kernel.org, Avadhut.Naik@amd.com,
John.Allen@amd.com
Subject: Re: [PATCH v2 05/16] x86/mce/amd: Clean up SMCA configuration
Date: Wed, 24 Apr 2024 04:29:01 +0200 [thread overview]
Message-ID: <20240424022822.GAZihuRjwlK6kOF0ya@fat_crate.local> (raw)
In-Reply-To: <eb9c5d9b-07d2-4b56-98dd-c2616ef73a0a@amd.com>
On Tue, Apr 23, 2024 at 03:32:00PM -0400, Yazen Ghannam wrote:
> This is not the same.
>
> "CFG_DFR_INT_TYPE" is a register field.
>
> "INTR_TYPE_APIC" is a value. And this same value can be used in other register
> fields.
I don't care - this was just an example of how it should look like. Like
the rest of the code around the kernel and not like an obfuscated
C contest mess.
> I think it's fair to just use logical AND for single bit checks instead of the
> FIELD_GET() macro.
>
> But the FIELD_PREP() macro does help for setting bitfields. I think it's
> clearer than manually doing the proper shifts and masks.
To you maybe.
Pls stick to how common code does masks generation and manipulation so
that this remains readable. This FIELD* crap is not helping.
> Okay. I was thinking to keep the names shorter since they are only used in
> this file. But I'll change them.
If you want to keep them shorter, then think of an overall shorter
scheme of how the register *and* the fields which belong to it, should
be named. But there's a point in having the same prefix for register and
bits which belong to it.
> Okay. I'll include the follow up patches in the next revision of this set.
Pls do.
Thanks.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2024-04-24 2:29 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-04 15:13 [PATCH v2 00/16] MCA Updates Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 01/16] x86/mce: Define mce_setup() helpers for common and per-CPU fields Yazen Ghannam
2024-04-16 10:02 ` Borislav Petkov
2024-04-17 13:50 ` Yazen Ghannam
2024-04-22 8:13 ` Borislav Petkov
2024-04-04 15:13 ` [PATCH v2 02/16] x86/mce: Use mce_setup() helpers for apei_smca_report_x86_error() Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 03/16] x86/mce/amd: Use fixed bank number for quirks Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 04/16] x86/mce/amd: Look up bank type by IPID Yazen Ghannam
2024-04-23 17:06 ` Borislav Petkov
2024-04-23 19:16 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 05/16] x86/mce/amd: Clean up SMCA configuration Yazen Ghannam
2024-04-23 19:06 ` Borislav Petkov
2024-04-23 19:32 ` Yazen Ghannam
2024-04-24 2:29 ` Borislav Petkov [this message]
2024-04-24 13:44 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 06/16] x86/mce/amd: Prep DFR handler before enabling banks Yazen Ghannam
2024-04-24 18:34 ` Borislav Petkov
2024-04-25 13:31 ` Yazen Ghannam
2024-04-29 12:38 ` Borislav Petkov
2024-04-29 13:22 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 07/16] x86/mce/amd: Simplify DFR handler setup Yazen Ghannam
2024-04-24 19:06 ` Borislav Petkov
2024-04-25 14:12 ` Yazen Ghannam
2024-04-29 12:59 ` Borislav Petkov
2024-04-29 13:56 ` Yazen Ghannam
2024-04-29 14:12 ` Borislav Petkov
2024-04-29 14:25 ` Yazen Ghannam
2024-04-30 13:47 ` Borislav Petkov
2024-04-29 18:34 ` Robert Richter
2024-04-30 18:06 ` Borislav Petkov
2024-05-02 16:02 ` Yazen Ghannam
2024-05-02 18:48 ` Robert Richter
2024-05-04 14:37 ` Borislav Petkov
2024-04-04 15:13 ` [PATCH v2 08/16] x86/mce/amd: Clean up enable_deferred_error_interrupt() Yazen Ghannam
2024-04-29 13:12 ` Borislav Petkov
2024-04-29 14:18 ` Yazen Ghannam
2024-05-04 14:41 ` Borislav Petkov
2024-04-04 15:13 ` [PATCH v2 09/16] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2024-04-29 13:40 ` Borislav Petkov
2024-04-29 14:36 ` Yazen Ghannam
2024-05-04 14:52 ` Borislav Petkov
2024-05-07 16:25 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 10/16] x86/mce: Unify AMD DFR " Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 11/16] x86/mce: Skip AMD threshold init if no threshold banks found Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 12/16] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 13/16] x86/mce: Add wrapper for struct mce to export vendor specific info Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 14/16] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 15/16] x86/mce/apei: Handle variable register array size Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 16/16] EDAC/mce_amd: Add support for FRU Text in MCA Yazen Ghannam
2024-04-05 16:06 ` Luck, Tony
2024-04-07 13:19 ` Yazen Ghannam
2024-04-08 19:47 ` Naik, Avadhut
2024-04-08 19:57 ` Luck, Tony
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