Re: [PATCH v2 09/16] x86/mce: Unify AMD THR handler with MCA Polling

From: Borislav Petkov <bp@alien8.de>
To: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
	tony.luck@intel.com, x86@kernel.org, Avadhut.Naik@amd.com,
	John.Allen@amd.com
Subject: Re: [PATCH v2 09/16] x86/mce: Unify AMD THR handler with MCA Polling
Date: Sat, 4 May 2024 16:52:53 +0200	[thread overview]
Message-ID: <20240504145253.GFZjZLxf3lzAHGaHhh@fat_crate.local> (raw)
In-Reply-To: <7b68f364-a324-4e2c-87be-19cdef4e3ad2@amd.com>

On Mon, Apr 29, 2024 at 10:36:57AM -0400, Yazen Ghannam wrote:
> Related to this, I've been thinking that banks with thresholding enabled
> should be removed from the list of polling banks. This is done on Intel but
> not on AMD.
> 
> I wanted to give it more thought, because I think folks have come to expect
> polling and thresholding to be independent on AMD.

Yes, this whole thing sounds weird.

On the one hand, you have a special interrupt for errors which have
reached a threshold *just* *so* you don't have to poll. Because polling
is ok but getting a a special interrupt is better and such notification
systems always want to have a special interrupt and not have to poll.

On the other hand, you're marrying the two which sounds weird. Why?

What is wrong with getting thresholding interrupts?

Why can't we simply stop the polling and do THR only if available? That
would save a lot of energy.

So why can't we program the THR to raise an interrupt on a single error
and disable polling completely?

Because that would be a lot better as the hardware would be doing the
work for us.

In any case, I'm missing the strategy here so no cleanups without
a clear goal first please.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette