From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: yazen.ghannam@amd.com, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org, tony.luck@intel.com,
x86@kernel.org, Avadhut.Naik@amd.com, John.Allen@amd.com
Subject: Re: [PATCH v2 05/16] x86/mce/amd: Clean up SMCA configuration
Date: Tue, 23 Apr 2024 15:32:00 -0400 [thread overview]
Message-ID: <eb9c5d9b-07d2-4b56-98dd-c2616ef73a0a@amd.com> (raw)
In-Reply-To: <20240423190641.GDZigGwXXEPeDnfOsr@fat_crate.local>
On 4/23/2024 3:06 PM, Borislav Petkov wrote:
> On Thu, Apr 04, 2024 at 10:13:48AM -0500, Yazen Ghannam wrote:
>> + /*
>> + * OS is required to set the MCAX enable bit to acknowledge that it is
>> + * now using the new MSR ranges and new registers under each
>> + * bank. It also means that the OS will configure deferred
>> + * errors in the new MCA_CONFIG register. If the bit is not set,
>> + * uncorrectable errors will cause a system panic.
>> + */
>> + mca_config |= FIELD_PREP(CFG_MCAX_EN, 0x1);
>
> Can we please drop this cryptic crap?
>
> mca_config |= SMCA_MCI_CONFIG_MCAX_ENABLE;
>
> if I trust the PPR.
>
Okay.
>> - this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));
>> + /*
>> + * SMCA sets the Deferred Error Interrupt type per bank.
>> + *
>> + * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
>> + * if the DeferredIntType bit field is available.
>> + *
>> + * MCA_CONFIG[DeferredIntType] is bits [38:37]. OS should set
>> + * this to 0x1 to enable APIC based interrupt. First, check that
>> + * no interrupt has been set.
>> + */
>> + if (FIELD_GET(CFG_DFR_INT_SUPP, mca_config) && !FIELD_GET(CFG_DFR_INT_TYPE, mca_config))
>> + mca_config |= FIELD_PREP(CFG_DFR_INT_TYPE, INTR_TYPE_APIC);
>
> Ditto:
>
> if (mca_config & CFG_DFR_INT_SUPP &&
> !(mca_config & CFG_DFR_INT_TYPE))
> mca_config |= CFG_DFR_INT_TYPE | CFG_INTR_TYPE_APIC;
>
> Plain and simple. Not this unreadable mess.
>
This is not the same.
"CFG_DFR_INT_TYPE" is a register field.
"INTR_TYPE_APIC" is a value. And this same value can be used in other register
fields.
I think it's fair to just use logical AND for single bit checks instead of the
FIELD_GET() macro.
But the FIELD_PREP() macro does help for setting bitfields. I think it's
clearer than manually doing the proper shifts and masks.
> And use proper prefixes with the register name in them:
>
> SMCA_MCI_CONFIG_
>
> or so, for example.
>
Okay. I was thinking to keep the names shorter since they are only used in
this file. But I'll change them.
>>
>> - wrmsr(smca_config, low, high);
>> - }
>> + if (FIELD_GET(CFG_LSB_IN_STATUS, mca_config))
>> + this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = true;
>> +
>> + wrmsrl(MSR_AMD64_SMCA_MCx_CONFIG(bank), mca_config);
>> +}
>> +
>> +static void smca_configure_old(unsigned int bank, unsigned int cpu)
>
> Yah, at the end of the patchset there should be patches which remove all
> the _old things. Not in a different patchset. You can split things
> accordingly.
>
Okay. I'll include the follow up patches in the next revision of this set.
Thanks,
Yazen
next prev parent reply other threads:[~2024-04-23 19:32 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-04 15:13 [PATCH v2 00/16] MCA Updates Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 01/16] x86/mce: Define mce_setup() helpers for common and per-CPU fields Yazen Ghannam
2024-04-16 10:02 ` Borislav Petkov
2024-04-17 13:50 ` Yazen Ghannam
2024-04-22 8:13 ` Borislav Petkov
2024-04-04 15:13 ` [PATCH v2 02/16] x86/mce: Use mce_setup() helpers for apei_smca_report_x86_error() Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 03/16] x86/mce/amd: Use fixed bank number for quirks Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 04/16] x86/mce/amd: Look up bank type by IPID Yazen Ghannam
2024-04-23 17:06 ` Borislav Petkov
2024-04-23 19:16 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 05/16] x86/mce/amd: Clean up SMCA configuration Yazen Ghannam
2024-04-23 19:06 ` Borislav Petkov
2024-04-23 19:32 ` Yazen Ghannam [this message]
2024-04-24 2:29 ` Borislav Petkov
2024-04-24 13:44 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 06/16] x86/mce/amd: Prep DFR handler before enabling banks Yazen Ghannam
2024-04-24 18:34 ` Borislav Petkov
2024-04-25 13:31 ` Yazen Ghannam
2024-04-29 12:38 ` Borislav Petkov
2024-04-29 13:22 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 07/16] x86/mce/amd: Simplify DFR handler setup Yazen Ghannam
2024-04-24 19:06 ` Borislav Petkov
2024-04-25 14:12 ` Yazen Ghannam
2024-04-29 12:59 ` Borislav Petkov
2024-04-29 13:56 ` Yazen Ghannam
2024-04-29 14:12 ` Borislav Petkov
2024-04-29 14:25 ` Yazen Ghannam
2024-04-30 13:47 ` Borislav Petkov
2024-04-29 18:34 ` Robert Richter
2024-04-30 18:06 ` Borislav Petkov
2024-05-02 16:02 ` Yazen Ghannam
2024-05-02 18:48 ` Robert Richter
2024-05-04 14:37 ` Borislav Petkov
2024-04-04 15:13 ` [PATCH v2 08/16] x86/mce/amd: Clean up enable_deferred_error_interrupt() Yazen Ghannam
2024-04-29 13:12 ` Borislav Petkov
2024-04-29 14:18 ` Yazen Ghannam
2024-05-04 14:41 ` Borislav Petkov
2024-04-04 15:13 ` [PATCH v2 09/16] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2024-04-29 13:40 ` Borislav Petkov
2024-04-29 14:36 ` Yazen Ghannam
2024-05-04 14:52 ` Borislav Petkov
2024-05-07 16:25 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 10/16] x86/mce: Unify AMD DFR " Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 11/16] x86/mce: Skip AMD threshold init if no threshold banks found Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 12/16] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 13/16] x86/mce: Add wrapper for struct mce to export vendor specific info Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 14/16] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 15/16] x86/mce/apei: Handle variable register array size Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 16/16] EDAC/mce_amd: Add support for FRU Text in MCA Yazen Ghannam
2024-04-05 16:06 ` Luck, Tony
2024-04-07 13:19 ` Yazen Ghannam
2024-04-08 19:47 ` Naik, Avadhut
2024-04-08 19:57 ` Luck, Tony
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