From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: yazen.ghannam@amd.com, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org, tony.luck@intel.com,
x86@kernel.org, Avadhut.Naik@amd.com, John.Allen@amd.com
Subject: Re: [PATCH v2 09/16] x86/mce: Unify AMD THR handler with MCA Polling
Date: Tue, 7 May 2024 12:25:07 -0400 [thread overview]
Message-ID: <8b396843-4505-415e-b989-14bb37245877@amd.com> (raw)
In-Reply-To: <20240504145253.GFZjZLxf3lzAHGaHhh@fat_crate.local>
On 5/4/24 10:52 AM, Borislav Petkov wrote:
> On Mon, Apr 29, 2024 at 10:36:57AM -0400, Yazen Ghannam wrote:
>> Related to this, I've been thinking that banks with thresholding enabled
>> should be removed from the list of polling banks. This is done on Intel but
>> not on AMD.
>>
>> I wanted to give it more thought, because I think folks have come to expect
>> polling and thresholding to be independent on AMD.
>
> Yes, this whole thing sounds weird.
>
> On the one hand, you have a special interrupt for errors which have
> reached a threshold *just* *so* you don't have to poll. Because polling
> is ok but getting a a special interrupt is better and such notification
> systems always want to have a special interrupt and not have to poll.
>
> On the other hand, you're marrying the two which sounds weird. Why?
>
> What is wrong with getting thresholding interrupts?
>
Nothing. This patch is not disabling the interrupt. The goal is to get
rid of duplicate code and have a single function that checks the MCA
banks.
This would be similar to intel_threshold_interrupt().
> Why can't we simply stop the polling and do THR only if available? That
> would save a lot of energy.
>
> So why can't we program the THR to raise an interrupt on a single error
> and disable polling completely?
>
> Because that would be a lot better as the hardware would be doing the
> work for us.
>
> In any case, I'm missing the strategy here so no cleanups without
> a clear goal first please.
>
We could do that. In fact, there's a request to use the threshold that
is pre-programmed in the hardware. And we could use some of the current
kernel parameters for overrides, if needed.
Thanks,
Yazen
next prev parent reply other threads:[~2024-05-07 18:05 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-04 15:13 [PATCH v2 00/16] MCA Updates Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 01/16] x86/mce: Define mce_setup() helpers for common and per-CPU fields Yazen Ghannam
2024-04-16 10:02 ` Borislav Petkov
2024-04-17 13:50 ` Yazen Ghannam
2024-04-22 8:13 ` Borislav Petkov
2024-04-04 15:13 ` [PATCH v2 02/16] x86/mce: Use mce_setup() helpers for apei_smca_report_x86_error() Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 03/16] x86/mce/amd: Use fixed bank number for quirks Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 04/16] x86/mce/amd: Look up bank type by IPID Yazen Ghannam
2024-04-23 17:06 ` Borislav Petkov
2024-04-23 19:16 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 05/16] x86/mce/amd: Clean up SMCA configuration Yazen Ghannam
2024-04-23 19:06 ` Borislav Petkov
2024-04-23 19:32 ` Yazen Ghannam
2024-04-24 2:29 ` Borislav Petkov
2024-04-24 13:44 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 06/16] x86/mce/amd: Prep DFR handler before enabling banks Yazen Ghannam
2024-04-24 18:34 ` Borislav Petkov
2024-04-25 13:31 ` Yazen Ghannam
2024-04-29 12:38 ` Borislav Petkov
2024-04-29 13:22 ` Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 07/16] x86/mce/amd: Simplify DFR handler setup Yazen Ghannam
2024-04-24 19:06 ` Borislav Petkov
2024-04-25 14:12 ` Yazen Ghannam
2024-04-29 12:59 ` Borislav Petkov
2024-04-29 13:56 ` Yazen Ghannam
2024-04-29 14:12 ` Borislav Petkov
2024-04-29 14:25 ` Yazen Ghannam
2024-04-30 13:47 ` Borislav Petkov
2024-04-29 18:34 ` Robert Richter
2024-04-30 18:06 ` Borislav Petkov
2024-05-02 16:02 ` Yazen Ghannam
2024-05-02 18:48 ` Robert Richter
2024-05-04 14:37 ` Borislav Petkov
2024-04-04 15:13 ` [PATCH v2 08/16] x86/mce/amd: Clean up enable_deferred_error_interrupt() Yazen Ghannam
2024-04-29 13:12 ` Borislav Petkov
2024-04-29 14:18 ` Yazen Ghannam
2024-05-04 14:41 ` Borislav Petkov
2024-04-04 15:13 ` [PATCH v2 09/16] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2024-04-29 13:40 ` Borislav Petkov
2024-04-29 14:36 ` Yazen Ghannam
2024-05-04 14:52 ` Borislav Petkov
2024-05-07 16:25 ` Yazen Ghannam [this message]
2024-04-04 15:13 ` [PATCH v2 10/16] x86/mce: Unify AMD DFR " Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 11/16] x86/mce: Skip AMD threshold init if no threshold banks found Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 12/16] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 13/16] x86/mce: Add wrapper for struct mce to export vendor specific info Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 14/16] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 15/16] x86/mce/apei: Handle variable register array size Yazen Ghannam
2024-04-04 15:13 ` [PATCH v2 16/16] EDAC/mce_amd: Add support for FRU Text in MCA Yazen Ghannam
2024-04-05 16:06 ` Luck, Tony
2024-04-07 13:19 ` Yazen Ghannam
2024-04-08 19:47 ` Naik, Avadhut
2024-04-08 19:57 ` Luck, Tony
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