[PATCH v2 0/7] Add Huashan Pi board support

[PATCH v2 0/7] Add Huashan Pi board support

[Inochi Amaoto]

Huashan Pi board is an embedded development platform based on the
CV1812H chip. Add minimal device tree files for this board.
Currently, it can boot to a basic shell.

NOTE: this series is based on the Jisheng's Milk-V Duo patch.

Link: https://en.sophgo.com/product/introduce/huashan.html
Link: https://en.sophgo.com/product/introduce/cv181xH.html

Changed from v1:
1. split the patch into several patch and refactor them.

Inochi Amaoto (7):
  dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
  dt-bindings: timer: Add SOPHGO CV1812H clint
  dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
  riscv: dts: sophgo: Separate common devices from cv1800b soc
  riscv: dts: sophgo: cv180x: Add gpio devices
  riscv: dts: sophgo: add initial CV1812H SoC device tree
  riscv: dts: sophgo: add Huashan Pi board device tree

 .../sifive,plic-1.0.0.yaml                    |  1 +
 .../devicetree/bindings/riscv/sophgo.yaml     |  4 +
 .../bindings/timer/sifive,clint.yaml          |  1 +
 arch/riscv/boot/dts/sophgo/Makefile           |  1 +
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 95 +------------------
 .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi}  | 91 ++++++++++++++----
 .../boot/dts/sophgo/cv1812h-huashan-pi.dts    | 48 ++++++++++
 arch/riscv/boot/dts/sophgo/cv1812h.dtsi       | 36 +++++++
 8 files changed, 165 insertions(+), 112 deletions(-)
 copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (58%)
 create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
 create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi

--
2.42.0


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[PATCH v2 1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic

[Inochi Amaoto]

Add compatible string for SOPHGO CV1812H plic.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 0c07e8dda445..709b2211276b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,7 @@ properties:
           - enum:
               - allwinner,sun20i-d1-plic
               - sophgo,cv1800b-plic
+              - sophgo,cv1812h-plic
               - sophgo,sg2042-plic
               - thead,th1520-plic
           - const: thead,c900-plic
--
2.42.0


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[PATCH v2 2/7] dt-bindings: timer: Add SOPHGO CV1812H clint

[Inochi Amaoto]

Add compatible string for the SOPHGO CV1812H clint.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index e8be6c470364..4b6c20fc8194 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -38,6 +38,7 @@ properties:
           - enum:
               - allwinner,sun20i-d1-clint
               - sophgo,cv1800b-clint
+              - sophgo,cv1812h-clint
               - thead,th1520-clint
           - const: thead,c900-clint
       - items:
--
2.42.0


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[PATCH v2 3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles

[Inochi Amaoto]

Document the compatible strings for the SOPHGO Huashan Pi board which
uses the SOPHGO CV1812H SoC.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Link: https://en.sophgo.com/product/introduce/huashan.html
Link: https://en.sophgo.com/product/introduce/cv181xH.html
Acked-by: Chen Wang <unicorn_wang@outlook.com>
---
 Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
index 86748c5390be..9bc813dad098 100644
--- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
+++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
@@ -22,6 +22,10 @@ properties:
           - enum:
               - milkv,duo
           - const: sophgo,cv1800b
+      - items:
+          - enum:
+              - sophgo,huashan-pi
+          - const: sophgo,cv1812h
       - items:
           - enum:
               - milkv,pioneer
--
2.42.0


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[PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc

[Inochi Amaoto]

Move the cpu and the common peripherals of CV181x and CV180x to new file.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 95 +------------------
 .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi}  | 19 +---
 2 files changed, 2 insertions(+), 112 deletions(-)
 copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%)

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index df40e87ee063..0904154f9829 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -3,106 +3,13 @@
  * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
  */

-#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv180x.dtsi"

 / {
 	compatible = "sophgo,cv1800b";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	cpus: cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		timebase-frequency = <25000000>;
-
-		cpu0: cpu@0 {
-			compatible = "thead,c906", "riscv";
-			device_type = "cpu";
-			reg = <0>;
-			d-cache-block-size = <64>;
-			d-cache-sets = <512>;
-			d-cache-size = <65536>;
-			i-cache-block-size = <64>;
-			i-cache-sets = <128>;
-			i-cache-size = <32768>;
-			mmu-type = "riscv,sv39";
-			riscv,isa = "rv64imafdc";
-			riscv,isa-base = "rv64i";
-			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
-
-			cpu0_intc: interrupt-controller {
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-			};
-		};
-	};
-
-	osc: oscillator {
-		compatible = "fixed-clock";
-		clock-output-names = "osc_25m";
-		#clock-cells = <0>;
-	};

 	soc {
-		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		dma-noncoherent;
-		ranges;
-
-		uart0: serial@4140000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x04140000 0x100>;
-			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		uart1: serial@4150000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x04150000 0x100>;
-			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		uart2: serial@4160000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x04160000 0x100>;
-			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		uart3: serial@4170000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x04170000 0x100>;
-			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		uart4: serial@41c0000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x041c0000 0x100>;
-			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};

 		plic: interrupt-controller@70000000 {
 			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
similarity index 80%
copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi
copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi
index df40e87ee063..ffaf51724c98 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
@@ -1,12 +1,12 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
  */

 #include <dt-bindings/interrupt-controller/irq.h>

 / {
-	compatible = "sophgo,cv1800b";
 	#address-cells = <1>;
 	#size-cells = <1>;

@@ -48,7 +48,6 @@ osc: oscillator {

 	soc {
 		compatible = "simple-bus";
-		interrupt-parent = <&plic>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		dma-noncoherent;
@@ -103,21 +102,5 @@ uart4: serial@41c0000 {
 			reg-io-width = <4>;
 			status = "disabled";
 		};
-
-		plic: interrupt-controller@70000000 {
-			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
-			reg = <0x70000000 0x4000000>;
-			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <2>;
-			riscv,ndev = <101>;
-		};
-
-		clint: timer@74000000 {
-			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
-			reg = <0x74000000 0x10000>;
-			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
-		};
 	};
 };
--
2.42.0


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[PATCH v2 5/7] riscv: dts: sophgo: cv180x: Add gpio devices

[Inochi Amaoto]

Add common GPIO devices for the CV180x and CV181x soc.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 arch/riscv/boot/dts/sophgo/cv180x.dtsi | 72 ++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
index ffaf51724c98..64ffb23d3626 100644
--- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
@@ -53,6 +53,78 @@ soc {
 		dma-noncoherent;
 		ranges;

+		gpio0: gpio@3020000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x3020000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio1: gpio@3021000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x3021000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portb: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio2: gpio@3022000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x3022000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portc: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio3: gpio@3023000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x3023000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portd: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		uart0: serial@4140000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x04140000 0x100>;
--
2.42.0


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[PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree

[Inochi Amaoto]

Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi

diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
new file mode 100644
index 000000000000..3864d34b0100
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv180x.dtsi"
+
+/ {
+	compatible = "sophgo,cv1812h";
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+
+	soc {
+		interrupt-parent = <&plic>;
+
+		plic: interrupt-controller@70000000 {
+			compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
+			reg = <0x70000000 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			riscv,ndev = <101>;
+		};
+
+		clint: timer@74000000 {
+			compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
+			reg = <0x74000000 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+		};
+	};
+};
--
2.42.0


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[PATCH v2 7/7] riscv: dts: sophgo: add Huashan Pi board device tree

[Inochi Amaoto]

Add initial device tree files for the Huashan Pi board.

Note: The boot of CV1812H chip needs a rtos firmware for coprocessor to
function properly. To make the soc happy, reserved the last 2M memory
for the rtos firmware.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Link: https://en.sophgo.com/product/introduce/huashan.html
Link: https://en.sophgo.com/product/introduce/cv181xH.html
Link: https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv181x/cv1812h_wevb_0007a_emmc_huashan/memmap.py#L15
---
 arch/riscv/boot/dts/sophgo/Makefile           |  1 +
 .../boot/dts/sophgo/cv1812h-huashan-pi.dts    | 48 +++++++++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts

diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
index 3fb65512c631..57ad82a61ea6 100644
--- a/arch/riscv/boot/dts/sophgo/Makefile
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
+dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
 dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
new file mode 100644
index 000000000000..aa361f3a86bb
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+/dts-v1/;
+
+#include "cv1812h.dtsi"
+
+/ {
+	model = "Huashan Pi";
+	compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		coprocessor_rtos: region@8fe00000 {
+			reg = <0x8fe00000 0x200000>;
+			no-map;
+		};
+	};
+};
+
+&osc {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
--
2.42.0


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Re: [PATCH v2 1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic

[Krzysztof Kozlowski]

On 09/10/2023 13:26, Inochi Amaoto wrote:
> Add compatible string for SOPHGO CV1812H plic.
> 
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

---

This is an automated instruction, just in case, because many review tags
are being ignored. If you know the process, you can skip it (please do
not feel offended by me posting it here - no bad intentions intended).
If you do not know the process, here is a short explanation:

Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions, under or above your Signed-off-by tag. Tag is "received", when
provided in a message replied to you on the mailing list. Tools like b4
can help here. However, there's no need to repost patches *only* to add
the tags. The upstream maintainer will do that for tags received on the
version they apply.

https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577

Best regards,
Krzysztof


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Re: [PATCH v2 2/7] dt-bindings: timer: Add SOPHGO CV1812H clint

[Krzysztof Kozlowski]

On 09/10/2023 13:26, Inochi Amaoto wrote:
> Add compatible string for the SOPHGO CV1812H clint.
> 
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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Re: [PATCH v2 3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles

[Krzysztof Kozlowski]

On 09/10/2023 13:26, Inochi Amaoto wrote:
> Document the compatible strings for the SOPHGO Huashan Pi board which
> uses the SOPHGO CV1812H SoC.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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Re: [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree

[Chen Wang]

On 2023/10/9 19:26, Inochi Amaoto wrote:
> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>   arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
>   1 file changed, 36 insertions(+)
>   create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> new file mode 100644
> index 000000000000..3864d34b0100
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
This include is not required.
> +#include "cv180x.dtsi"
> +
> +/ {
> +	compatible = "sophgo,cv1812h";
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x80000000 0x10000000>;
> +	};
What's this defined for , I see this is different against cv1800b.
> +
> +	soc {
> +		interrupt-parent = <&plic>;
> +
> +		plic: interrupt-controller@70000000 {
> +			compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> +			reg = <0x70000000 0x4000000>;
> +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			riscv,ndev = <101>;
> +		};
> +
> +		clint: timer@74000000 {
> +			compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> +			reg = <0x74000000 0x10000>;
> +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> +		};
> +	};
> +};
> --
> 2.42.0
>

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Re: [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree

[Inochi Amaoto]

>On 2023/10/9 19:26, Inochi Amaoto wrote:
>> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
>>
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>> ---
>>   arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
>>   1 file changed, 36 insertions(+)
>>   create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>> new file mode 100644
>> index 000000000000..3864d34b0100
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>> @@ -0,0 +1,36 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/*
>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>This include is not required.

Thx.

>> +#include "cv180x.dtsi"
>> +
>> +/ {
>> +    compatible = "sophgo,cv1812h";
>> +
>> +    memory@80000000 {
>> +        device_type = "memory";
>> +        reg = <0x80000000 0x10000000>;
>> +    };
>What's this defined for , I see this is different against cv1800b.

CV1812h have a embedded 256MB RAM. The cv1800b is 64MB, This is why the
size is different. I write this node here because the RAM is embedded
and fixed size, and leave it in the board DT is unnecessary.

>> +
>> +    soc {
>> +        interrupt-parent = <&plic>;
>> +
>> +        plic: interrupt-controller@70000000 {
>> +            compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
>> +            reg = <0x70000000 0x4000000>;
>> +            interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
>> +            interrupt-controller;
>> +            #address-cells = <0>;
>> +            #interrupt-cells = <2>;
>> +            riscv,ndev = <101>;
>> +        };
>> +
>> +        clint: timer@74000000 {
>> +            compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
>> +            reg = <0x74000000 0x10000>;
>> +            interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
>> +        };
>> +    };
>> +};
>> --
>> 2.42.0
>>
>

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Re: [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 2422 bytes --]

On Tue, Oct 10, 2023 at 03:53:54PM +0800, Inochi Amaoto wrote:
> >On 2023/10/9 19:26, Inochi Amaoto wrote:
> >> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> >> ---
> >>   arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
> >>   1 file changed, 36 insertions(+)
> >>   create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >>
> >> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >> new file mode 100644
> >> index 000000000000..3864d34b0100
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >> @@ -0,0 +1,36 @@
> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> +/*
> >> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> >> + */
> >> +
> >> +#include <dt-bindings/interrupt-controller/irq.h>
> >This include is not required.
> 
> Thx.

I can drop this include on application. Is the rest of the series okay
with you Chen Wang?

Thanks,
Conor.

> 
> >> +#include "cv180x.dtsi"
> >> +
> >> +/ {
> >> +    compatible = "sophgo,cv1812h";
> >> +
> >> +    memory@80000000 {
> >> +        device_type = "memory";
> >> +        reg = <0x80000000 0x10000000>;
> >> +    };
> >What's this defined for , I see this is different against cv1800b.
> 
> CV1812h have a embedded 256MB RAM. The cv1800b is 64MB, This is why the
> size is different. I write this node here because the RAM is embedded
> and fixed size, and leave it in the board DT is unnecessary.
> 
> >> +
> >> +    soc {
> >> +        interrupt-parent = <&plic>;
> >> +
> >> +        plic: interrupt-controller@70000000 {
> >> +            compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> >> +            reg = <0x70000000 0x4000000>;
> >> +            interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> >> +            interrupt-controller;
> >> +            #address-cells = <0>;
> >> +            #interrupt-cells = <2>;
> >> +            riscv,ndev = <101>;
> >> +        };
> >> +
> >> +        clint: timer@74000000 {
> >> +            compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> >> +            reg = <0x74000000 0x10000>;
> >> +            interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> >> +        };
> >> +    };
> >> +};
> >> --
> >> 2.42.0
> >>
> >

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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

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Re: [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc

[Chen Wang]

On 2023/10/9 19:26, Inochi Amaoto wrote:
> Move the cpu and the common peripherals of CV181x and CV180x to new file.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>   arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 95 +------------------
>   .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi}  | 19 +---
>   2 files changed, 2 insertions(+), 112 deletions(-)
>   copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index df40e87ee063..0904154f9829 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi

Hi，Jisheng

Do you have any more comment on this change related to cv1800b?

> @@ -3,106 +3,13 @@
>    * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>    */
>
> -#include <dt-bindings/interrupt-controller/irq.h>
> +#include "cv180x.dtsi"
>
>   / {
>   	compatible = "sophgo,cv1800b";
> -	#address-cells = <1>;
> -	#size-cells = <1>;
> -
> -	cpus: cpus {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		timebase-frequency = <25000000>;
> -
> -		cpu0: cpu@0 {
> -			compatible = "thead,c906", "riscv";
> -			device_type = "cpu";
> -			reg = <0>;
> -			d-cache-block-size = <64>;
> -			d-cache-sets = <512>;
> -			d-cache-size = <65536>;
> -			i-cache-block-size = <64>;
> -			i-cache-sets = <128>;
> -			i-cache-size = <32768>;
> -			mmu-type = "riscv,sv39";
> -			riscv,isa = "rv64imafdc";
> -			riscv,isa-base = "rv64i";
> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> -					       "zifencei", "zihpm";
> -
> -			cpu0_intc: interrupt-controller {
> -				compatible = "riscv,cpu-intc";
> -				interrupt-controller;
> -				#address-cells = <0>;
> -				#interrupt-cells = <1>;
> -			};
> -		};
> -	};
> -
> -	osc: oscillator {
> -		compatible = "fixed-clock";
> -		clock-output-names = "osc_25m";
> -		#clock-cells = <0>;
> -	};
>
>   	soc {
> -		compatible = "simple-bus";
>   		interrupt-parent = <&plic>;
> -		#address-cells = <1>;
> -		#size-cells = <1>;
> -		dma-noncoherent;
> -		ranges;
> -
> -		uart0: serial@4140000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04140000 0x100>;
> -			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart1: serial@4150000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04150000 0x100>;
> -			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart2: serial@4160000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04160000 0x100>;
> -			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart3: serial@4170000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04170000 0x100>;
> -			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart4: serial@41c0000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x041c0000 0x100>;
> -			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
>
>   		plic: interrupt-controller@70000000 {
>   			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> similarity index 80%
> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index df40e87ee063..ffaf51724c98 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -1,12 +1,12 @@
>   // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>   /*
>    * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>    */
>
>   #include <dt-bindings/interrupt-controller/irq.h>
>
>   / {
> -	compatible = "sophgo,cv1800b";
>   	#address-cells = <1>;
>   	#size-cells = <1>;
>
> @@ -48,7 +48,6 @@ osc: oscillator {
>
>   	soc {
>   		compatible = "simple-bus";
> -		interrupt-parent = <&plic>;
>   		#address-cells = <1>;
>   		#size-cells = <1>;
>   		dma-noncoherent;
> @@ -103,21 +102,5 @@ uart4: serial@41c0000 {
>   			reg-io-width = <4>;
>   			status = "disabled";
>   		};
> -
> -		plic: interrupt-controller@70000000 {
> -			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> -			reg = <0x70000000 0x4000000>;
> -			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> -			interrupt-controller;
> -			#address-cells = <0>;
> -			#interrupt-cells = <2>;
> -			riscv,ndev = <101>;
> -		};
> -
> -		clint: timer@74000000 {
> -			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> -			reg = <0x74000000 0x10000>;
> -			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> -		};
>   	};
>   };
> --
> 2.42.0
>

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Re: [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc

[Chen Wang]

On 2023/10/9 19:26, Inochi Amaoto wrote:
> Move the cpu and the common peripherals of CV181x and CV180x to new file.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>   arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 95 +------------------
>   .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi}  | 19 +---
>   2 files changed, 2 insertions(+), 112 deletions(-)
>   copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%)

LGTM

Acked-by: Chen Wang <unicorn_wang@outlook.com>

> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index df40e87ee063..0904154f9829 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -3,106 +3,13 @@
>    * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>    */
>
> -#include <dt-bindings/interrupt-controller/irq.h>
> +#include "cv180x.dtsi"
>
>   / {
>   	compatible = "sophgo,cv1800b";
> -	#address-cells = <1>;
> -	#size-cells = <1>;
> -
> -	cpus: cpus {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		timebase-frequency = <25000000>;
> -
> -		cpu0: cpu@0 {
> -			compatible = "thead,c906", "riscv";
> -			device_type = "cpu";
> -			reg = <0>;
> -			d-cache-block-size = <64>;
> -			d-cache-sets = <512>;
> -			d-cache-size = <65536>;
> -			i-cache-block-size = <64>;
> -			i-cache-sets = <128>;
> -			i-cache-size = <32768>;
> -			mmu-type = "riscv,sv39";
> -			riscv,isa = "rv64imafdc";
> -			riscv,isa-base = "rv64i";
> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> -					       "zifencei", "zihpm";
> -
> -			cpu0_intc: interrupt-controller {
> -				compatible = "riscv,cpu-intc";
> -				interrupt-controller;
> -				#address-cells = <0>;
> -				#interrupt-cells = <1>;
> -			};
> -		};
> -	};
> -
> -	osc: oscillator {
> -		compatible = "fixed-clock";
> -		clock-output-names = "osc_25m";
> -		#clock-cells = <0>;
> -	};
>
>   	soc {
> -		compatible = "simple-bus";
>   		interrupt-parent = <&plic>;
> -		#address-cells = <1>;
> -		#size-cells = <1>;
> -		dma-noncoherent;
> -		ranges;
> -
> -		uart0: serial@4140000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04140000 0x100>;
> -			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart1: serial@4150000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04150000 0x100>;
> -			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart2: serial@4160000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04160000 0x100>;
> -			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart3: serial@4170000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04170000 0x100>;
> -			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart4: serial@41c0000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x041c0000 0x100>;
> -			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
>
>   		plic: interrupt-controller@70000000 {
>   			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> similarity index 80%
> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index df40e87ee063..ffaf51724c98 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -1,12 +1,12 @@
>   // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>   /*
>    * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>    */
>
>   #include <dt-bindings/interrupt-controller/irq.h>
>
>   / {
> -	compatible = "sophgo,cv1800b";
>   	#address-cells = <1>;
>   	#size-cells = <1>;
>
> @@ -48,7 +48,6 @@ osc: oscillator {
>
>   	soc {
>   		compatible = "simple-bus";
> -		interrupt-parent = <&plic>;
>   		#address-cells = <1>;
>   		#size-cells = <1>;
>   		dma-noncoherent;
> @@ -103,21 +102,5 @@ uart4: serial@41c0000 {
>   			reg-io-width = <4>;
>   			status = "disabled";
>   		};
> -
> -		plic: interrupt-controller@70000000 {
> -			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> -			reg = <0x70000000 0x4000000>;
> -			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> -			interrupt-controller;
> -			#address-cells = <0>;
> -			#interrupt-cells = <2>;
> -			riscv,ndev = <101>;
> -		};
> -
> -		clint: timer@74000000 {
> -			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> -			reg = <0x74000000 0x10000>;
> -			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> -		};
>   	};
>   };
> --
> 2.42.0
>

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Re: [PATCH v2 5/7] riscv: dts: sophgo: cv180x: Add gpio devices

[Chen Wang]

On 2023/10/9 19:26, Inochi Amaoto wrote:
> Add common GPIO devices for the CV180x and CV181x soc.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>   arch/riscv/boot/dts/sophgo/cv180x.dtsi | 72 ++++++++++++++++++++++++++
>   1 file changed, 72 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index ffaf51724c98..64ffb23d3626 100644
> --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -53,6 +53,78 @@ soc {
>   		dma-noncoherent;
>   		ranges;
>
> +		gpio0: gpio@3020000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x3020000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			porta: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				ngpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		gpio1: gpio@3021000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x3021000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			portb: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				ngpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		gpio2: gpio@3022000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x3022000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			portc: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				ngpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		gpio3: gpio@3023000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x3023000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			portd: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				ngpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>   		uart0: serial@4140000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x04140000 0x100>;
LGTM

Acked-by: Chen Wang <unicorn_wang@outlook.com>

Thanks,

Chen


> --
> 2.42.0
>

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Re: [PATCH v2 7/7] riscv: dts: sophgo: add Huashan Pi board device tree

[Chen Wang]

On 2023/10/9 19:26, Inochi Amaoto wrote:
> Add initial device tree files for the Huashan Pi board.
>
> Note: The boot of CV1812H chip needs a rtos firmware for coprocessor to
> function properly. To make the soc happy, reserved the last 2M memory
> for the rtos firmware.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Link: https://en.sophgo.com/product/introduce/huashan.html
> Link: https://en.sophgo.com/product/introduce/cv181xH.html
> Link: https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv181x/cv1812h_wevb_0007a_emmc_huashan/memmap.py#L15
> ---
>   arch/riscv/boot/dts/sophgo/Makefile           |  1 +
>   .../boot/dts/sophgo/cv1812h-huashan-pi.dts    | 48 +++++++++++++++++++
>   2 files changed, 49 insertions(+)
>   create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
>
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 3fb65512c631..57ad82a61ea6 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -1,3 +1,4 @@
>   # SPDX-License-Identifier: GPL-2.0
>   dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
>   dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> new file mode 100644
> index 000000000000..aa361f3a86bb
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "cv1812h.dtsi"
> +
> +/ {
> +	model = "Huashan Pi";
> +	compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
> +
> +	aliases {
> +		gpio0 = &gpio0;
> +		gpio1 = &gpio1;
> +		gpio2 = &gpio2;
> +		gpio3 = &gpio3;
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		coprocessor_rtos: region@8fe00000 {
> +			reg = <0x8fe00000 0x200000>;
> +			no-map;
> +		};
> +	};
> +};
> +
> +&osc {
> +	clock-frequency = <25000000>;
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> --
LGTM

Acked-by: Chen Wang <unicorn_wang@outlook.com>
> 2.42.0
>

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Re: [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree

[Chen Wang]

On 2023/10/12 17:41, Conor Dooley wrote:
> On Tue, Oct 10, 2023 at 03:53:54PM +0800, Inochi Amaoto wrote:
>>> On 2023/10/9 19:26, Inochi Amaoto wrote:
>>>> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
>>>>
>>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>>>> ---
>>>>    arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
>>>>    1 file changed, 36 insertions(+)
>>>>    create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>>>>
>>>> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>>>> new file mode 100644
>>>> index 000000000000..3864d34b0100
>>>> --- /dev/null
>>>> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>>>> @@ -0,0 +1,36 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>> +/*
>>>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>>>> + */
>>>> +
>>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> This include is not required.
>> Thx.
> I can drop this include on application. Is the rest of the series okay
> with you Chen Wang?
>
> Thanks,
> Conor.

Yes, just remove this include and the others are all

Acked-by: Chen Wang <unicorn_wang@outlook.com>

I also ran dtbs check with W=1 and no warning found.

BTW, due to this patchset changes some code submitted by Jisheng, I have 
sent email to him and hope he to have a look too.



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Re: [PATCH v2 0/7] Add Huashan Pi board support

[Jisheng Zhang]

On Mon, Oct 09, 2023 at 07:25:14PM +0800, Inochi Amaoto wrote:
> Huashan Pi board is an embedded development platform based on the
> CV1812H chip. Add minimal device tree files for this board.
> Currently, it can boot to a basic shell.
> 
> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
> 
> Link: https://en.sophgo.com/product/introduce/huashan.html
> Link: https://en.sophgo.com/product/introduce/cv181xH.html
> 
> Changed from v1:
> 1. split the patch into several patch and refactor them.
> 
> Inochi Amaoto (7):
>   dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
>   dt-bindings: timer: Add SOPHGO CV1812H clint
>   dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
>   riscv: dts: sophgo: Separate common devices from cv1800b soc
>   riscv: dts: sophgo: cv180x: Add gpio devices
>   riscv: dts: sophgo: add initial CV1812H SoC device tree
>   riscv: dts: sophgo: add Huashan Pi board device tree

For the patch series:
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> 
>  .../sifive,plic-1.0.0.yaml                    |  1 +
>  .../devicetree/bindings/riscv/sophgo.yaml     |  4 +
>  .../bindings/timer/sifive,clint.yaml          |  1 +
>  arch/riscv/boot/dts/sophgo/Makefile           |  1 +
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 95 +------------------
>  .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi}  | 91 ++++++++++++++----
>  .../boot/dts/sophgo/cv1812h-huashan-pi.dts    | 48 ++++++++++
>  arch/riscv/boot/dts/sophgo/cv1812h.dtsi       | 36 +++++++
>  8 files changed, 165 insertions(+), 112 deletions(-)
>  copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (58%)
>  create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
>  create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> 
> --
> 2.42.0
> 

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Re: [PATCH v2 0/7] Add Huashan Pi board support

[Krzysztof Kozlowski]

On 09/10/2023 13:25, Inochi Amaoto wrote:
> Huashan Pi board is an embedded development platform based on the
> CV1812H chip. Add minimal device tree files for this board.
> Currently, it can boot to a basic shell.
> 
> NOTE: this series is based on the Jisheng's Milk-V Duo patch.

Which is? This must be clear dependency - lore link.

Best regards,
Krzysztof


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Re: [PATCH v2 0/7] Add Huashan Pi board support

[Inochi Amaoto]

On Fri, Oct 13, 2023 at 10:48:23AM +0200, Krzysztof Kozlowski wrote:
> On 09/10/2023 13:25, Inochi Amaoto wrote:
> > Huashan Pi board is an embedded development platform based on the
> > CV1812H chip. Add minimal device tree files for this board.
> > Currently, it can boot to a basic shell.
> > 
> > NOTE: this series is based on the Jisheng's Milk-V Duo patch.
> 
> Which is? This must be clear dependency - lore link.
> 

https://lore.kernel.org/linux-riscv/20231006121449.721-1-jszhang@kernel.org/
AFAIK, This is merged in the for-next.

> Best regards,
> Krzysztof
> 

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Re: [PATCH v2 0/7] Add Huashan Pi board support

[Inochi Amaoto]

>On 09/10/2023 13:25, Inochi Amaoto wrote:
>> Huashan Pi board is an embedded development platform based on the
>> CV1812H chip. Add minimal device tree files for this board.
>> Currently, it can boot to a basic shell.
>>
>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>
>Which is? This must be clear dependency - lore link.
>
>Best regards,
>Krzysztof

https://lore.kernel.org/linux-riscv/c3920f4e-9e93-4a33-b3af-cc30cf6c1fe3@linaro.org/
AFAIK, this is already merged.

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Re: [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 9405 bytes --]

Yo,

On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote:
> Move the cpu and the common peripherals of CV181x and CV180x to new file.
> 
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 95 +------------------
>  .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi}  | 19 +---
>  2 files changed, 2 insertions(+), 112 deletions(-)
>  copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index df40e87ee063..0904154f9829 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -3,106 +3,13 @@
>   * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>   */
> 
> -#include <dt-bindings/interrupt-controller/irq.h>
> +#include "cv180x.dtsi"
> 
>  / {
>  	compatible = "sophgo,cv1800b";
> -	#address-cells = <1>;
> -	#size-cells = <1>;
> -
> -	cpus: cpus {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		timebase-frequency = <25000000>;
> -
> -		cpu0: cpu@0 {
> -			compatible = "thead,c906", "riscv";
> -			device_type = "cpu";
> -			reg = <0>;
> -			d-cache-block-size = <64>;
> -			d-cache-sets = <512>;
> -			d-cache-size = <65536>;
> -			i-cache-block-size = <64>;
> -			i-cache-sets = <128>;
> -			i-cache-size = <32768>;
> -			mmu-type = "riscv,sv39";
> -			riscv,isa = "rv64imafdc";
> -			riscv,isa-base = "rv64i";
> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> -					       "zifencei", "zihpm";
> -
> -			cpu0_intc: interrupt-controller {
> -				compatible = "riscv,cpu-intc";
> -				interrupt-controller;
> -				#address-cells = <0>;
> -				#interrupt-cells = <1>;
> -			};
> -		};
> -	};
> -
> -	osc: oscillator {
> -		compatible = "fixed-clock";
> -		clock-output-names = "osc_25m";
> -		#clock-cells = <0>;
> -	};
> 
>  	soc {
> -		compatible = "simple-bus";
>  		interrupt-parent = <&plic>;
> -		#address-cells = <1>;
> -		#size-cells = <1>;
> -		dma-noncoherent;
> -		ranges;
> -
> -		uart0: serial@4140000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04140000 0x100>;
> -			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart1: serial@4150000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04150000 0x100>;
> -			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart2: serial@4160000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04160000 0x100>;
> -			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart3: serial@4170000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04170000 0x100>;
> -			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart4: serial@41c0000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x041c0000 0x100>;
> -			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> 
>  		plic: interrupt-controller@70000000 {
>  			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> similarity index 80%
> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index df40e87ee063..ffaf51724c98 100644

Firstly, this form of diff really threw me, I was quite confused for a
few minutes. A copy plus a pair of diffs doesn't really make much sense,
when the operation being carried is an extraction of some nodes to a
different file.

> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -1,12 +1,12 @@
>  // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>  /*
>   * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>

Also, is moving around some bits of hw description really a
copyrightable change?

>   */
> 
>  #include <dt-bindings/interrupt-controller/irq.h>
> 
>  / {
> -	compatible = "sophgo,cv1800b";
>  	#address-cells = <1>;
>  	#size-cells = <1>;
> 
> @@ -48,7 +48,6 @@ osc: oscillator {
> 
>  	soc {
>  		compatible = "simple-bus";
> -		interrupt-parent = <&plic>;
>  		#address-cells = <1>;
>  		#size-cells = <1>;
>  		dma-noncoherent;
> @@ -103,21 +102,5 @@ uart4: serial@41c0000 {
>  			reg-io-width = <4>;
>  			status = "disabled";
>  		};
> -
> -		plic: interrupt-controller@70000000 {
> -			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> -			reg = <0x70000000 0x4000000>;
> -			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> -			interrupt-controller;
> -			#address-cells = <0>;
> -			#interrupt-cells = <2>;
> -			riscv,ndev = <101>;
> -		};
> -
> -		clint: timer@74000000 {
> -			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> -			reg = <0x74000000 0x10000>;
> -			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> -		};
>  	};
>  };

What I wanted to comment on was this though - it seems that both the
cv1800b and the cv1812h have identical plic and clint nodes, other than
their compatibles? If that is the case, why create a cv1800b and a
cv1812h specific file containing entirely new nodes, when overriding the
compatible would be sufficient? Doubly so if the other SoCs in the
cv18xx series are going to have identical layouts.

I gave it a quick test locally with the below diff applied on top of
this series - although I didn't make sure that I didn't re-order the
plic & clint nodes, I just wanted to demonstrate what I had done.

Cheers,
Conor.

-- 8< --

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
index 3af9e34b3bc7..a9d809a49e7a 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
+++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "cv1800b.dtsi"
+#include "cv180x.dtsi"
 
 / {
 	model = "Milk-V Duo";
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index 0904154f9829..e69de29bb2d1 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
- */
-
-#include "cv180x.dtsi"
-
-/ {
-	compatible = "sophgo,cv1800b";
-
-	soc {
-		interrupt-parent = <&plic>;
-
-		plic: interrupt-controller@70000000 {
-			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
-			reg = <0x70000000 0x4000000>;
-			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <2>;
-			riscv,ndev = <101>;
-		};
-
-		clint: timer@74000000 {
-			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
-			reg = <0x74000000 0x10000>;
-			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
-		};
-	};
-};
diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
index 64ffb23d3626..1a2c44ba4de9 100644
--- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
@@ -48,6 +48,7 @@ osc: oscillator {
 
 	soc {
 		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		dma-noncoherent;
@@ -174,5 +175,21 @@ uart4: serial@41c0000 {
 			reg-io-width = <4>;
 			status = "disabled";
 		};
+
+		plic: interrupt-controller@70000000 {
+			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
+			reg = <0x70000000 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			riscv,ndev = <101>;
+		};
+
+		clint: timer@74000000 {
+			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
+			reg = <0x74000000 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+		};
 	};
 };
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
index 3864d34b0100..c0a8d3290cc8 100644
--- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -15,22 +15,13 @@ memory@80000000 {
 	};
 
 	soc {
-		interrupt-parent = <&plic>;
 
 		plic: interrupt-controller@70000000 {
 			compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
-			reg = <0x70000000 0x4000000>;
-			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <2>;
-			riscv,ndev = <101>;
 		};
 
 		clint: timer@74000000 {
 			compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
-			reg = <0x74000000 0x10000>;
-			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
 		};
 	};
 };


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Re: [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree

[Inochi Amaoto]

>Yo,
>
>On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote:
>> Move the cpu and the common peripherals of CV181x and CV180x to new file.
>>
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>> ---
>>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 95 +------------------
>>  .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi}  | 19 +---
>>  2 files changed, 2 insertions(+), 112 deletions(-)
>>  copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%)
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> index df40e87ee063..0904154f9829 100644
>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> @@ -3,106 +3,13 @@
>>   * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>>   */
>>
>> -#include <dt-bindings/interrupt-controller/irq.h>
>> +#include "cv180x.dtsi"
>>
>>  / {
>>  	compatible = "sophgo,cv1800b";
>> -	#address-cells = <1>;
>> -	#size-cells = <1>;
>> -
>> -	cpus: cpus {
>> -		#address-cells = <1>;
>> -		#size-cells = <0>;
>> -		timebase-frequency = <25000000>;
>> -
>> -		cpu0: cpu@0 {
>> -			compatible = "thead,c906", "riscv";
>> -			device_type = "cpu";
>> -			reg = <0>;
>> -			d-cache-block-size = <64>;
>> -			d-cache-sets = <512>;
>> -			d-cache-size = <65536>;
>> -			i-cache-block-size = <64>;
>> -			i-cache-sets = <128>;
>> -			i-cache-size = <32768>;
>> -			mmu-type = "riscv,sv39";
>> -			riscv,isa = "rv64imafdc";
>> -			riscv,isa-base = "rv64i";
>> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
>> -					       "zifencei", "zihpm";
>> -
>> -			cpu0_intc: interrupt-controller {
>> -				compatible = "riscv,cpu-intc";
>> -				interrupt-controller;
>> -				#address-cells = <0>;
>> -				#interrupt-cells = <1>;
>> -			};
>> -		};
>> -	};
>> -
>> -	osc: oscillator {
>> -		compatible = "fixed-clock";
>> -		clock-output-names = "osc_25m";
>> -		#clock-cells = <0>;
>> -	};
>>
>>  	soc {
>> -		compatible = "simple-bus";
>>  		interrupt-parent = <&plic>;
>> -		#address-cells = <1>;
>> -		#size-cells = <1>;
>> -		dma-noncoherent;
>> -		ranges;
>> -
>> -		uart0: serial@4140000 {
>> -			compatible = "snps,dw-apb-uart";
>> -			reg = <0x04140000 0x100>;
>> -			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> -			reg-shift = <2>;
>> -			reg-io-width = <4>;
>> -			status = "disabled";
>> -		};
>> -
>> -		uart1: serial@4150000 {
>> -			compatible = "snps,dw-apb-uart";
>> -			reg = <0x04150000 0x100>;
>> -			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> -			reg-shift = <2>;
>> -			reg-io-width = <4>;
>> -			status = "disabled";
>> -		};
>> -
>> -		uart2: serial@4160000 {
>> -			compatible = "snps,dw-apb-uart";
>> -			reg = <0x04160000 0x100>;
>> -			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> -			reg-shift = <2>;
>> -			reg-io-width = <4>;
>> -			status = "disabled";
>> -		};
>> -
>> -		uart3: serial@4170000 {
>> -			compatible = "snps,dw-apb-uart";
>> -			reg = <0x04170000 0x100>;
>> -			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> -			reg-shift = <2>;
>> -			reg-io-width = <4>;
>> -			status = "disabled";
>> -		};
>> -
>> -		uart4: serial@41c0000 {
>> -			compatible = "snps,dw-apb-uart";
>> -			reg = <0x041c0000 0x100>;
>> -			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> -			reg-shift = <2>;
>> -			reg-io-width = <4>;
>> -			status = "disabled";
>> -		};
>>
>>  		plic: interrupt-controller@70000000 {
>>  			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
>> similarity index 80%
>> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi
>> index df40e87ee063..ffaf51724c98 100644
>
>Firstly, this form of diff really threw me, I was quite confused for a
>few minutes. A copy plus a pair of diffs doesn't really make much sense,
>when the operation being carried is an extraction of some nodes to a
>different file.
>

I was told to use -C/-M/-B to generate patch, and the git format-patch
give me this wired output if I use -C, using -M seems no change from v1.
The -B output is also disappointing. Maybe I need to generate agaion?

The v1 version:
https://lore.kernel.org/linux-riscv/IA1PR20MB495360B632D106BBB833D82ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com/

>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
>> @@ -1,12 +1,12 @@
>>  // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>  /*
>>   * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>
>Also, is moving around some bits of hw description really a
>copyrightable change?
>

It seems to be a mistake when I splitting the patch from v1.
This copyright should in the next patch.

>>   */
>>
>>  #include <dt-bindings/interrupt-controller/irq.h>
>>
>>  / {
>> -	compatible = "sophgo,cv1800b";
>>  	#address-cells = <1>;
>>  	#size-cells = <1>;
>>
>> @@ -48,7 +48,6 @@ osc: oscillator {
>>
>>  	soc {
>>  		compatible = "simple-bus";
>> -		interrupt-parent = <&plic>;
>>  		#address-cells = <1>;
>>  		#size-cells = <1>;
>>  		dma-noncoherent;
>> @@ -103,21 +102,5 @@ uart4: serial@41c0000 {
>>  			reg-io-width = <4>;
>>  			status = "disabled";
>>  		};
>> -
>> -		plic: interrupt-controller@70000000 {
>> -			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
>> -			reg = <0x70000000 0x4000000>;
>> -			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
>> -			interrupt-controller;
>> -			#address-cells = <0>;
>> -			#interrupt-cells = <2>;
>> -			riscv,ndev = <101>;
>> -		};
>> -
>> -		clint: timer@74000000 {
>> -			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
>> -			reg = <0x74000000 0x10000>;
>> -			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
>> -		};
>>  	};
>>  };
>
>What I wanted to comment on was this though - it seems that both the
>cv1800b and the cv1812h have identical plic and clint nodes, other than
>their compatibles? If that is the case, why create a cv1800b and a
>cv1812h specific file containing entirely new nodes, when overriding the
>compatible would be sufficient? Doubly so if the other SoCs in the
>cv18xx series are going to have identical layouts.
>
>I gave it a quick test locally with the below diff applied on top of
>this series - although I didn't make sure that I didn't re-order the
>plic & clint nodes, I just wanted to demonstrate what I had done.
>

Thanks for demonstration. AFAIK, what you said is true. the most devices
of CV180x and CV181x are the same, including plic and clint. The reason I
used a new one is to identify these two devices without making the
compatible string confusing.
Should I change the binding name of plic and clint to "sophgo,cv1800-xxx"
to mark there are the same series? I think this can avoid this confusing
dt nodes.

>Cheers,
>Conor.
>

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Re: [PATCH v2 6/7] riscv: dts: sophgo: Separate common devices from cv1800b soc

[Inochi Amaoto]

Sorry for the wrong title.

>Yo,
>
>On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote:
>> Move the cpu and the common peripherals of CV181x and CV180x to new file.
>>
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>> ---
>>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 95 +------------------
>>  .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi}  | 19 +---
>>  2 files changed, 2 insertions(+), 112 deletions(-)
>>  copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%)
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> index df40e87ee063..0904154f9829 100644
>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> @@ -3,106 +3,13 @@
>>   * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>>   */
>>
>> -#include <dt-bindings/interrupt-controller/irq.h>
>> +#include "cv180x.dtsi"
>>
>>  / {
>>  	compatible = "sophgo,cv1800b";
>> -	#address-cells = <1>;
>> -	#size-cells = <1>;
>> -
>> -	cpus: cpus {
>> -		#address-cells = <1>;
>> -		#size-cells = <0>;
>> -		timebase-frequency = <25000000>;
>> -
>> -		cpu0: cpu@0 {
>> -			compatible = "thead,c906", "riscv";
>> -			device_type = "cpu";
>> -			reg = <0>;
>> -			d-cache-block-size = <64>;
>> -			d-cache-sets = <512>;
>> -			d-cache-size = <65536>;
>> -			i-cache-block-size = <64>;
>> -			i-cache-sets = <128>;
>> -			i-cache-size = <32768>;
>> -			mmu-type = "riscv,sv39";
>> -			riscv,isa = "rv64imafdc";
>> -			riscv,isa-base = "rv64i";
>> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
>> -					       "zifencei", "zihpm";
>> -
>> -			cpu0_intc: interrupt-controller {
>> -				compatible = "riscv,cpu-intc";
>> -				interrupt-controller;
>> -				#address-cells = <0>;
>> -				#interrupt-cells = <1>;
>> -			};
>> -		};
>> -	};
>> -
>> -	osc: oscillator {
>> -		compatible = "fixed-clock";
>> -		clock-output-names = "osc_25m";
>> -		#clock-cells = <0>;
>> -	};
>>
>>  	soc {
>> -		compatible = "simple-bus";
>>  		interrupt-parent = <&plic>;
>> -		#address-cells = <1>;
>> -		#size-cells = <1>;
>> -		dma-noncoherent;
>> -		ranges;
>> -
>> -		uart0: serial@4140000 {
>> -			compatible = "snps,dw-apb-uart";
>> -			reg = <0x04140000 0x100>;
>> -			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> -			reg-shift = <2>;
>> -			reg-io-width = <4>;
>> -			status = "disabled";
>> -		};
>> -
>> -		uart1: serial@4150000 {
>> -			compatible = "snps,dw-apb-uart";
>> -			reg = <0x04150000 0x100>;
>> -			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> -			reg-shift = <2>;
>> -			reg-io-width = <4>;
>> -			status = "disabled";
>> -		};
>> -
>> -		uart2: serial@4160000 {
>> -			compatible = "snps,dw-apb-uart";
>> -			reg = <0x04160000 0x100>;
>> -			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> -			reg-shift = <2>;
>> -			reg-io-width = <4>;
>> -			status = "disabled";
>> -		};
>> -
>> -		uart3: serial@4170000 {
>> -			compatible = "snps,dw-apb-uart";
>> -			reg = <0x04170000 0x100>;
>> -			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> -			reg-shift = <2>;
>> -			reg-io-width = <4>;
>> -			status = "disabled";
>> -		};
>> -
>> -		uart4: serial@41c0000 {
>> -			compatible = "snps,dw-apb-uart";
>> -			reg = <0x041c0000 0x100>;
>> -			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> -			reg-shift = <2>;
>> -			reg-io-width = <4>;
>> -			status = "disabled";
>> -		};
>>
>>  		plic: interrupt-controller@70000000 {
>>  			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
>> similarity index 80%
>> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi
>> index df40e87ee063..ffaf51724c98 100644
>
>Firstly, this form of diff really threw me, I was quite confused for a
>few minutes. A copy plus a pair of diffs doesn't really make much sense,
>when the operation being carried is an extraction of some nodes to a
>different file.
>

I was told to use -C/-M/-B to generate patch, and the git format-patch
give me this wired output if I use -C, using -M seems no change from v1.
The -B output is also disappointing. Maybe I need to generate agaion?

The v1 version:
https://lore.kernel.org/linux-riscv/IA1PR20MB495360B632D106BBB833D82ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com/

>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
>> @@ -1,12 +1,12 @@
>>  // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>  /*
>>   * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>
>Also, is moving around some bits of hw description really a
>copyrightable change?
>

It seems to be a mistake when I splitting the patch from v1.
This copyright should in the next patch.

>>   */
>>
>>  #include <dt-bindings/interrupt-controller/irq.h>
>>
>>  / {
>> -	compatible = "sophgo,cv1800b";
>>  	#address-cells = <1>;
>>  	#size-cells = <1>;
>>
>> @@ -48,7 +48,6 @@ osc: oscillator {
>>
>>  	soc {
>>  		compatible = "simple-bus";
>> -		interrupt-parent = <&plic>;
>>  		#address-cells = <1>;
>>  		#size-cells = <1>;
>>  		dma-noncoherent;
>> @@ -103,21 +102,5 @@ uart4: serial@41c0000 {
>>  			reg-io-width = <4>;
>>  			status = "disabled";
>>  		};
>> -
>> -		plic: interrupt-controller@70000000 {
>> -			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
>> -			reg = <0x70000000 0x4000000>;
>> -			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
>> -			interrupt-controller;
>> -			#address-cells = <0>;
>> -			#interrupt-cells = <2>;
>> -			riscv,ndev = <101>;
>> -		};
>> -
>> -		clint: timer@74000000 {
>> -			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
>> -			reg = <0x74000000 0x10000>;
>> -			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
>> -		};
>>  	};
>>  };
>
>What I wanted to comment on was this though - it seems that both the
>cv1800b and the cv1812h have identical plic and clint nodes, other than
>their compatibles? If that is the case, why create a cv1800b and a
>cv1812h specific file containing entirely new nodes, when overriding the
>compatible would be sufficient? Doubly so if the other SoCs in the
>cv18xx series are going to have identical layouts.
>
>I gave it a quick test locally with the below diff applied on top of
>this series - although I didn't make sure that I didn't re-order the
>plic & clint nodes, I just wanted to demonstrate what I had done.
>

Thanks for demonstration. AFAIK, what you said is true. the most devices
of CV180x and CV181x are the same, including plic and clint. The reason I
used a new one is to identify these two devices without making the
compatible string confusing.
Should I change the binding name of plic and clint to "sophgo,cv1800-xxx"
to mark there are the same series? I think this can avoid this confusing
dt nodes.

>Cheers,
>Conor.
>

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Re: [PATCH v2 6/7] riscv: dts: sophgo: Separate common devices from cv1800b soc

[Conor Dooley]

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On Fri, Oct 13, 2023 at 05:52:03PM +0800, Inochi Amaoto wrote:
> Sorry for the wrong title.
> 
> >Yo,
> >
> >On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote:
> >> Move the cpu and the common peripherals of CV181x and CV180x to new file.
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> >> ---
> >>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 95 +------------------
> >>  .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi}  | 19 +---
> >>  2 files changed, 2 insertions(+), 112 deletions(-)
> >>  copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%)
> >>
> >> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >> index df40e87ee063..0904154f9829 100644
> >> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >> @@ -3,106 +3,13 @@
> >>   * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> >>   */
> >>
> >> -#include <dt-bindings/interrupt-controller/irq.h>
> >> +#include "cv180x.dtsi"
> >>
> >>  / {
> >>  	compatible = "sophgo,cv1800b";
> >> -	#address-cells = <1>;
> >> -	#size-cells = <1>;
> >> -
> >> -	cpus: cpus {
> >> -		#address-cells = <1>;
> >> -		#size-cells = <0>;
> >> -		timebase-frequency = <25000000>;
> >> -
> >> -		cpu0: cpu@0 {
> >> -			compatible = "thead,c906", "riscv";
> >> -			device_type = "cpu";
> >> -			reg = <0>;
> >> -			d-cache-block-size = <64>;
> >> -			d-cache-sets = <512>;
> >> -			d-cache-size = <65536>;
> >> -			i-cache-block-size = <64>;
> >> -			i-cache-sets = <128>;
> >> -			i-cache-size = <32768>;
> >> -			mmu-type = "riscv,sv39";
> >> -			riscv,isa = "rv64imafdc";
> >> -			riscv,isa-base = "rv64i";
> >> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> >> -					       "zifencei", "zihpm";
> >> -
> >> -			cpu0_intc: interrupt-controller {
> >> -				compatible = "riscv,cpu-intc";
> >> -				interrupt-controller;
> >> -				#address-cells = <0>;
> >> -				#interrupt-cells = <1>;
> >> -			};
> >> -		};
> >> -	};
> >> -
> >> -	osc: oscillator {
> >> -		compatible = "fixed-clock";
> >> -		clock-output-names = "osc_25m";
> >> -		#clock-cells = <0>;
> >> -	};
> >>
> >>  	soc {
> >> -		compatible = "simple-bus";
> >>  		interrupt-parent = <&plic>;
> >> -		#address-cells = <1>;
> >> -		#size-cells = <1>;
> >> -		dma-noncoherent;
> >> -		ranges;
> >> -
> >> -		uart0: serial@4140000 {
> >> -			compatible = "snps,dw-apb-uart";
> >> -			reg = <0x04140000 0x100>;
> >> -			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> >> -			clocks = <&osc>;
> >> -			reg-shift = <2>;
> >> -			reg-io-width = <4>;
> >> -			status = "disabled";
> >> -		};
> >> -
> >> -		uart1: serial@4150000 {
> >> -			compatible = "snps,dw-apb-uart";
> >> -			reg = <0x04150000 0x100>;
> >> -			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> >> -			clocks = <&osc>;
> >> -			reg-shift = <2>;
> >> -			reg-io-width = <4>;
> >> -			status = "disabled";
> >> -		};
> >> -
> >> -		uart2: serial@4160000 {
> >> -			compatible = "snps,dw-apb-uart";
> >> -			reg = <0x04160000 0x100>;
> >> -			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> >> -			clocks = <&osc>;
> >> -			reg-shift = <2>;
> >> -			reg-io-width = <4>;
> >> -			status = "disabled";
> >> -		};
> >> -
> >> -		uart3: serial@4170000 {
> >> -			compatible = "snps,dw-apb-uart";
> >> -			reg = <0x04170000 0x100>;
> >> -			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> >> -			clocks = <&osc>;
> >> -			reg-shift = <2>;
> >> -			reg-io-width = <4>;
> >> -			status = "disabled";
> >> -		};
> >> -
> >> -		uart4: serial@41c0000 {
> >> -			compatible = "snps,dw-apb-uart";
> >> -			reg = <0x041c0000 0x100>;
> >> -			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> >> -			clocks = <&osc>;
> >> -			reg-shift = <2>;
> >> -			reg-io-width = <4>;
> >> -			status = "disabled";
> >> -		};
> >>
> >>  		plic: interrupt-controller@70000000 {
> >>  			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> >> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> >> similarity index 80%
> >> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi
> >> index df40e87ee063..ffaf51724c98 100644
> >
> >Firstly, this form of diff really threw me, I was quite confused for a
> >few minutes. A copy plus a pair of diffs doesn't really make much sense,
> >when the operation being carried is an extraction of some nodes to a
> >different file.
> >
> 
> I was told to use -C/-M/-B to generate patch, and the git format-patch
> give me this wired output if I use -C, using -M seems no change from v1.
> The -B output is also disappointing. Maybe I need to generate agaion?

I don't think generating it again is going to change the outcome & I
don't really think the -C version of this patch makes much sense, it is
hard to tell what has actually been moved.

> The v1 version:
> https://lore.kernel.org/linux-riscv/IA1PR20MB495360B632D106BBB833D82ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com/
> 
> >> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> >> @@ -1,12 +1,12 @@
> >>  // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >>  /*
> >>   * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> >> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> >
> >Also, is moving around some bits of hw description really a
> >copyrightable change?
> >
> 
> It seems to be a mistake when I splitting the patch from v1.
> This copyright should in the next patch.
> 
> >>   */
> >>
> >>  #include <dt-bindings/interrupt-controller/irq.h>
> >>
> >>  / {
> >> -	compatible = "sophgo,cv1800b";
> >>  	#address-cells = <1>;
> >>  	#size-cells = <1>;
> >>
> >> @@ -48,7 +48,6 @@ osc: oscillator {
> >>
> >>  	soc {
> >>  		compatible = "simple-bus";
> >> -		interrupt-parent = <&plic>;
> >>  		#address-cells = <1>;
> >>  		#size-cells = <1>;
> >>  		dma-noncoherent;
> >> @@ -103,21 +102,5 @@ uart4: serial@41c0000 {
> >>  			reg-io-width = <4>;
> >>  			status = "disabled";
> >>  		};
> >> -
> >> -		plic: interrupt-controller@70000000 {
> >> -			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> >> -			reg = <0x70000000 0x4000000>;
> >> -			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> >> -			interrupt-controller;
> >> -			#address-cells = <0>;
> >> -			#interrupt-cells = <2>;
> >> -			riscv,ndev = <101>;
> >> -		};
> >> -
> >> -		clint: timer@74000000 {
> >> -			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> >> -			reg = <0x74000000 0x10000>;
> >> -			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> >> -		};
> >>  	};
> >>  };
> >
> >What I wanted to comment on was this though - it seems that both the
> >cv1800b and the cv1812h have identical plic and clint nodes, other than
> >their compatibles? If that is the case, why create a cv1800b and a
> >cv1812h specific file containing entirely new nodes, when overriding the
> >compatible would be sufficient? Doubly so if the other SoCs in the
> >cv18xx series are going to have identical layouts.
> >
> >I gave it a quick test locally with the below diff applied on top of
> >this series - although I didn't make sure that I didn't re-order the
> >plic & clint nodes, I just wanted to demonstrate what I had done.
> >
> 
> Thanks for demonstration. AFAIK, what you said is true. the most devices
> of CV180x and CV181x are the same, including plic and clint. The reason I
> used a new one is to identify these two devices without making the
> compatible string confusing.
> Should I change the binding name of plic and clint to "sophgo,cv1800-xxx"
> to mark there are the same series? I think this can avoid this confusing
> dt nodes.

I personally don't find the compatibles (or the dt nodes) confusing, so
I dunno. Having reusing the compatible is not something that I am a fan of
either, since this seems to be a different soc (given the sram &
coprocessor etc) even if the addresses of the peripherals are identical.

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Re: [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc

[Inochi Amaoto]

>
>On Fri, Oct 13, 2023 at 05:52:03PM +0800, Inochi Amaoto wrote:
>> Sorry for the wrong title.
>>
>>> Yo,
>>>
>>> On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote:
>>>> Move the cpu and the common peripherals of CV181x and CV180x to new file.
>>>>
>>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>>>> ---
>>>>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 95 +------------------
>>>>  .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi}  | 19 +---
>>>>  2 files changed, 2 insertions(+), 112 deletions(-)
>>>>  copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%)
>>>>
>>>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>>> index df40e87ee063..0904154f9829 100644
>>>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>>> @@ -3,106 +3,13 @@
>>>>   * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>>>>   */
>>>>
>>>> -#include <dt-bindings/interrupt-controller/irq.h>
>>>> +#include "cv180x.dtsi"
>>>>
>>>>  / {
>>>>  	compatible = "sophgo,cv1800b";
>>>> -	#address-cells = <1>;
>>>> -	#size-cells = <1>;
>>>> -
>>>> -	cpus: cpus {
>>>> -		#address-cells = <1>;
>>>> -		#size-cells = <0>;
>>>> -		timebase-frequency = <25000000>;
>>>> -
>>>> -		cpu0: cpu@0 {
>>>> -			compatible = "thead,c906", "riscv";
>>>> -			device_type = "cpu";
>>>> -			reg = <0>;
>>>> -			d-cache-block-size = <64>;
>>>> -			d-cache-sets = <512>;
>>>> -			d-cache-size = <65536>;
>>>> -			i-cache-block-size = <64>;
>>>> -			i-cache-sets = <128>;
>>>> -			i-cache-size = <32768>;
>>>> -			mmu-type = "riscv,sv39";
>>>> -			riscv,isa = "rv64imafdc";
>>>> -			riscv,isa-base = "rv64i";
>>>> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
>>>> -					       "zifencei", "zihpm";
>>>> -
>>>> -			cpu0_intc: interrupt-controller {
>>>> -				compatible = "riscv,cpu-intc";
>>>> -				interrupt-controller;
>>>> -				#address-cells = <0>;
>>>> -				#interrupt-cells = <1>;
>>>> -			};
>>>> -		};
>>>> -	};
>>>> -
>>>> -	osc: oscillator {
>>>> -		compatible = "fixed-clock";
>>>> -		clock-output-names = "osc_25m";
>>>> -		#clock-cells = <0>;
>>>> -	};
>>>>
>>>>  	soc {
>>>> -		compatible = "simple-bus";
>>>>  		interrupt-parent = <&plic>;
>>>> -		#address-cells = <1>;
>>>> -		#size-cells = <1>;
>>>> -		dma-noncoherent;
>>>> -		ranges;
>>>> -
>>>> -		uart0: serial@4140000 {
>>>> -			compatible = "snps,dw-apb-uart";
>>>> -			reg = <0x04140000 0x100>;
>>>> -			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
>>>> -			clocks = <&osc>;
>>>> -			reg-shift = <2>;
>>>> -			reg-io-width = <4>;
>>>> -			status = "disabled";
>>>> -		};
>>>> -
>>>> -		uart1: serial@4150000 {
>>>> -			compatible = "snps,dw-apb-uart";
>>>> -			reg = <0x04150000 0x100>;
>>>> -			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
>>>> -			clocks = <&osc>;
>>>> -			reg-shift = <2>;
>>>> -			reg-io-width = <4>;
>>>> -			status = "disabled";
>>>> -		};
>>>> -
>>>> -		uart2: serial@4160000 {
>>>> -			compatible = "snps,dw-apb-uart";
>>>> -			reg = <0x04160000 0x100>;
>>>> -			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
>>>> -			clocks = <&osc>;
>>>> -			reg-shift = <2>;
>>>> -			reg-io-width = <4>;
>>>> -			status = "disabled";
>>>> -		};
>>>> -
>>>> -		uart3: serial@4170000 {
>>>> -			compatible = "snps,dw-apb-uart";
>>>> -			reg = <0x04170000 0x100>;
>>>> -			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
>>>> -			clocks = <&osc>;
>>>> -			reg-shift = <2>;
>>>> -			reg-io-width = <4>;
>>>> -			status = "disabled";
>>>> -		};
>>>> -
>>>> -		uart4: serial@41c0000 {
>>>> -			compatible = "snps,dw-apb-uart";
>>>> -			reg = <0x041c0000 0x100>;
>>>> -			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
>>>> -			clocks = <&osc>;
>>>> -			reg-shift = <2>;
>>>> -			reg-io-width = <4>;
>>>> -			status = "disabled";
>>>> -		};
>>>>
>>>>  		plic: interrupt-controller@70000000 {
>>>>  			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
>>>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
>>>> similarity index 80%
>>>> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>>> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi
>>>> index df40e87ee063..ffaf51724c98 100644
>>>
>>> Firstly, this form of diff really threw me, I was quite confused for a
>>> few minutes. A copy plus a pair of diffs doesn't really make much sense,
>>> when the operation being carried is an extraction of some nodes to a
>>> different file.
>>>
>>
>> I was told to use -C/-M/-B to generate patch, and the git format-patch
>> give me this wired output if I use -C, using -M seems no change from v1.
>> The -B output is also disappointing. Maybe I need to generate agaion?
>
>I don't think generating it again is going to change the outcome & I
>don't really think the -C version of this patch makes much sense, it is
>hard to tell what has actually been moved.
>

I mean regenerating without -C, This shows the the code move, but it gives
a huge output, since the git can not detect this move and output all the
moved line in the diff as changed.

>> The v1 version:
>> https://lore.kernel.org/linux-riscv/IA1PR20MB495360B632D106BBB833D82ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com/
>>
>>>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>>> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
>>>> @@ -1,12 +1,12 @@
>>>>  // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>>  /*
>>>>   * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>>>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>>>
>>> Also, is moving around some bits of hw description really a
>>> copyrightable change?
>>>
>>
>> It seems to be a mistake when I splitting the patch from v1.
>> This copyright should in the next patch.
>>
>>>>   */
>>>>
>>>>  #include <dt-bindings/interrupt-controller/irq.h>
>>>>
>>>>  / {
>>>> -	compatible = "sophgo,cv1800b";
>>>>  	#address-cells = <1>;
>>>>  	#size-cells = <1>;
>>>>
>>>> @@ -48,7 +48,6 @@ osc: oscillator {
>>>>
>>>>  	soc {
>>>>  		compatible = "simple-bus";
>>>> -		interrupt-parent = <&plic>;
>>>>  		#address-cells = <1>;
>>>>  		#size-cells = <1>;
>>>>  		dma-noncoherent;
>>>> @@ -103,21 +102,5 @@ uart4: serial@41c0000 {
>>>>  			reg-io-width = <4>;
>>>>  			status = "disabled";
>>>>  		};
>>>> -
>>>> -		plic: interrupt-controller@70000000 {
>>>> -			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
>>>> -			reg = <0x70000000 0x4000000>;
>>>> -			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
>>>> -			interrupt-controller;
>>>> -			#address-cells = <0>;
>>>> -			#interrupt-cells = <2>;
>>>> -			riscv,ndev = <101>;
>>>> -		};
>>>> -
>>>> -		clint: timer@74000000 {
>>>> -			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
>>>> -			reg = <0x74000000 0x10000>;
>>>> -			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
>>>> -		};
>>>>  	};
>>>>  };
>>>
>>> What I wanted to comment on was this though - it seems that both the
>>> cv1800b and the cv1812h have identical plic and clint nodes, other than
>>> their compatibles? If that is the case, why create a cv1800b and a
>>> cv1812h specific file containing entirely new nodes, when overriding the
>>> compatible would be sufficient? Doubly so if the other SoCs in the
>>> cv18xx series are going to have identical layouts.
>>>
>>> I gave it a quick test locally with the below diff applied on top of
>>> this series - although I didn't make sure that I didn't re-order the
>>> plic & clint nodes, I just wanted to demonstrate what I had done.
>>>
>>
>> Thanks for demonstration. AFAIK, what you said is true. the most devices
>> of CV180x and CV181x are the same, including plic and clint. The reason I
>> used a new one is to identify these two devices without making the
>> compatible string confusing.
>> Should I change the binding name of plic and clint to "sophgo,cv1800-xxx"
>> to mark there are the same series? I think this can avoid this confusing
>> dt nodes.
>
>I personally don't find the compatibles (or the dt nodes) confusing, so
>I dunno. Having reusing the compatible is not something that I am a fan of
>either, since this seems to be a different soc (given the sram &
>coprocessor etc) even if the addresses of the peripherals are identical.

Thanks. It is more like I have misunderstood something.

>
>

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Re: [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc

[Jisheng Zhang]

On Fri, Oct 13, 2023 at 10:08:24AM +0100, Conor Dooley wrote:
> Yo,
> 
> On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote:
> > Move the cpu and the common peripherals of CV181x and CV180x to new file.
> > 
...

> >  	};
> >  };
> 
> What I wanted to comment on was this though - it seems that both the
> cv1800b and the cv1812h have identical plic and clint nodes, other than
> their compatibles? If that is the case, why create a cv1800b and a
> cv1812h specific file containing entirely new nodes, when overriding the
> compatible would be sufficient? Doubly so if the other SoCs in the
> cv18xx series are going to have identical layouts.
> 
> I gave it a quick test locally with the below diff applied on top of
> this series - although I didn't make sure that I didn't re-order the
> plic & clint nodes, I just wanted to demonstrate what I had done.
> 
> Cheers,
> Conor.
> 
> -- 8< --
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
> index 3af9e34b3bc7..a9d809a49e7a 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
> @@ -5,7 +5,7 @@
>  
>  /dts-v1/;
>  
> -#include "cv1800b.dtsi"
> +#include "cv180x.dtsi"
>  
>  / {
>  	model = "Milk-V Duo";
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index 0904154f9829..e69de29bb2d1 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -1,30 +0,0 @@
> -// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> -/*
> - * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> - */
> -
> -#include "cv180x.dtsi"
> -
> -/ {
> -	compatible = "sophgo,cv1800b";
> -
> -	soc {
> -		interrupt-parent = <&plic>;
> -
> -		plic: interrupt-controller@70000000 {
> -			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> -			reg = <0x70000000 0x4000000>;
> -			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> -			interrupt-controller;
> -			#address-cells = <0>;
> -			#interrupt-cells = <2>;
> -			riscv,ndev = <101>;
> -		};
> -
> -		clint: timer@74000000 {
> -			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> -			reg = <0x74000000 0x10000>;
> -			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> -		};
> -	};
> -};
> diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index 64ffb23d3626..1a2c44ba4de9 100644
> --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -48,6 +48,7 @@ osc: oscillator {
>  
>  	soc {
>  		compatible = "simple-bus";
> +		interrupt-parent = <&plic>;
>  		#address-cells = <1>;
>  		#size-cells = <1>;
>  		dma-noncoherent;
> @@ -174,5 +175,21 @@ uart4: serial@41c0000 {
>  			reg-io-width = <4>;
>  			status = "disabled";
>  		};
> +
> +		plic: interrupt-controller@70000000 {
> +			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> +			reg = <0x70000000 0x4000000>;
> +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			riscv,ndev = <101>;
> +		};
> +
> +		clint: timer@74000000 {
> +			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> +			reg = <0x74000000 0x10000>;
> +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> +		};
>  	};
>  };
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> index 3864d34b0100..c0a8d3290cc8 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> @@ -15,22 +15,13 @@ memory@80000000 {
>  	};
>  
>  	soc {
> -		interrupt-parent = <&plic>;
>  
>  		plic: interrupt-controller@70000000 {
>  			compatible = "sophgo,cv1812h-plic", "thead,c900-plic";

Hi Conor,

Maybe this has been discussed before but I didn't find it. I'm wondering
the reason of adding each plic and clint binding for each SoC, can we
just use the thead,c900-plic for plic?
FWICT, arm gic dt usage follows this way, there's no binding for each SoC's
gic but directly use "arm,gic-v3" and so on.


Thanks in advance

> -			reg = <0x70000000 0x4000000>;
> -			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> -			interrupt-controller;
> -			#address-cells = <0>;
> -			#interrupt-cells = <2>;
> -			riscv,ndev = <101>;
>  		};
>  
>  		clint: timer@74000000 {
>  			compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> -			reg = <0x74000000 0x10000>;
> -			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;


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Re: [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc

[Conor Dooley]

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> Maybe this has been discussed before but I didn't find it. I'm wondering
> the reason of adding each plic and clint binding for each SoC, can we
> just use the thead,c900-plic for plic?
> FWICT, arm gic dt usage follows this way, there's no binding for each SoC's
> gic but directly use "arm,gic-v3" and so on.

I'm not aware of why the gic-v3 is done like this, but having different
compatibles allows differentiation between implementations/integrations
of this interrupt controller. I think having that ability is especially
helpful given T-Head have open-sourced a bunch of their IP.

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