From: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com,
bob.j.paauwe@intel.com, edmund.j.dea@intel.com
Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org,
rodrigo.vivi@intel.com
Subject: [PATCH 14/59] drm/kmb: Correct address offsets for mipi registers
Date: Tue, 30 Jun 2020 14:27:26 -0700 [thread overview]
Message-ID: <1593552491-23698-15-git-send-email-anitha.chrisanthus@intel.com> (raw)
In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com>
Mipi HS registers start at an additional offset of 0x400 which needs to be
added at the register macro definition and not at the read/write function
level.
v2: replaced calculations with macro to make code simpler
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
drivers/gpu/drm/kmb/kmb_dsi.c | 16 +++---
drivers/gpu/drm/kmb/kmb_regs.h | 116 ++++++++++++++++++++++++-----------------
2 files changed, 75 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 886a8ac..adcfe81 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -443,20 +443,20 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv,
*REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1
*REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3
*/
- offset = (frame_gen % 2) * 16;
- reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen);
+ offset = (frame_gen % 2)*16;
+ reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen/2);
kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->vsync_width);
- /*v backporch - same register config like vsync width */
- reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen);
+ /*v backporch - same register config like vsync width*/
+ reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen/2);
kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_backporch);
- /*v frontporch - same register config like vsync width */
- reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen);
+ /*v frontporch - same register config like vsync width*/
+ reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen/2);
kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_frontporch);
- /*v active - same register config like vsync width */
- reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen);
+ /*v active - same register config like vsync width*/
+ reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen/2);
kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_active);
/*hsyc width */
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index 9a5f371..4d6cf3d 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -395,10 +395,10 @@
* MIPI controller control register defines
***********************************************i****************************/
#define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400)
-#define MIPI_CTRL_HS_BASE_ADDR (0x400)
+#define HS_OFFSET(M) ((M + 1) * 0x400)
#define MIPI_TX_HS_CTRL (0x0)
-#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + (0x400*M))
+#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M))
#define HS_CTRL_EN (1 << 0)
#define HS_CTRL_CSIDSIN (1 << 2) /*1:CSI 0:DSI*/
#define TX_SOURCE (1 << 3) /*1:LCD, 0:DMA*/
@@ -411,7 +411,7 @@
#define HSCLKIDLE_CNT (1 << 24)
#define MIPI_TX_HS_SYNC_CFG (0x8)
#define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \
- + (0x400*M))
+ + HS_OFFSET(M))
#define LINE_SYNC_PKT_ENABLE (1 << 0)
#define FRAME_COUNTER_ACTIVE (1 << 1)
#define LINE_COUNTER_ACTIVE (1 << 2)
@@ -428,75 +428,93 @@
#define FRAME_GEN_EN(f) ((f) << 23)
#define HACT_WAIT_STOP(f) ((f) << 28)
#define MIPI_TX0_HS_FG0_SECT0_PH (0x40)
-#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \
- (0x400*M) + (0x2C*N) + (8*O))
-#define MIPI_TX_SECT_WC_MASK (0xffff)
-#define MIPI_TX_SECT_VC_MASK (3)
-#define MIPI_TX_SECT_VC_SHIFT (22)
-#define MIPI_TX_SECT_DT_MASK (0x3f)
-#define MIPI_TX_SECT_DT_SHIFT (16)
-#define MIPI_TX_SECT_DM_MASK (3)
-#define MIPI_TX_SECT_DM_SHIFT (24)
-#define MIPI_TX_SECT_DMA_PACKED (1<<26)
+#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \
+ HS_OFFSET(M) + (0x2C*N) + (8*O))
+#define MIPI_TX_SECT_WC_MASK (0xffff)
+#define MIPI_TX_SECT_VC_MASK (3)
+#define MIPI_TX_SECT_VC_SHIFT (22)
+#define MIPI_TX_SECT_DT_MASK (0x3f)
+#define MIPI_TX_SECT_DT_SHIFT (16)
+#define MIPI_TX_SECT_DM_MASK (3)
+#define MIPI_TX_SECT_DM_SHIFT (24)
+#define MIPI_TX_SECT_DMA_PACKED (1<<26)
#define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60)
#define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64)
-#define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \
- (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 + (0x400*M) + (0x2C*N))
+#define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \
+ (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 \
+ + HS_OFFSET(M) + (0x2C*N))
#define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44)
-#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \
- (MIPI_TX_HS_FG0_SECT0_LINE_CFG + (0x400*M) + (0x2C*N) + (8*O))
+#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \
+ (MIPI_TX_HS_FG0_SECT0_LINE_CFG + HS_OFFSET(M) \
+ + (0x2C*N) + (8*O))
#define MIPI_TX_HS_FG0_NUM_LINES (0x68)
-#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) (MIPI_TX_HS_FG0_NUM_LINES + \
- (0x400*M) + (0x2C*N))
+#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) \
+ (MIPI_TX_HS_FG0_NUM_LINES + HS_OFFSET(M) \
+ + (0x2C*N))
#define MIPI_TX_HS_VSYNC_WIDTHS0 (0x104)
-#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) (MIPI_TX_HS_VSYNC_WIDTHS0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) \
+ (MIPI_TX_HS_VSYNC_WIDTHS0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_V_BACKPORCHES0 (0x16c)
-#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) (MIPI_TX_HS_V_BACKPORCHES0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) \
+ (MIPI_TX_HS_V_BACKPORCHES0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_V_FRONTPORCHES0 (0x174)
-#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) (MIPI_TX_HS_V_FRONTPORCHES0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) \
+ (MIPI_TX_HS_V_FRONTPORCHES0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_V_ACTIVE0 (0x17c)
-#define MIPI_TXm_HS_V_ACTIVEn(M, N) (MIPI_TX_HS_V_ACTIVE0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_V_ACTIVEn(M, N) \
+ (MIPI_TX_HS_V_ACTIVE0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_HSYNC_WIDTH0 (0x10c)
-#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_HSYNC_WIDTH0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) \
+ (MIPI_TX_HS_HSYNC_WIDTH0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_H_BACKPORCH0 (0x11c)
-#define MIPI_TXm_HS_H_BACKPORCHn(M, N) (MIPI_TX_HS_H_BACKPORCH0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_H_BACKPORCHn(M, N) \
+ (MIPI_TX_HS_H_BACKPORCH0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_H_FRONTPORCH0 (0x12c)
-#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) (MIPI_TX_HS_H_FRONTPORCH0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) \
+ (MIPI_TX_HS_H_FRONTPORCH0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_H_ACTIVE0 (0x184)
-#define MIPI_TXm_HS_H_ACTIVEn(M, N) (MIPI_TX_HS_H_ACTIVE0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_H_ACTIVEn(M, N) \
+ (MIPI_TX_HS_H_ACTIVE0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_LLP_HSYNC_WIDTH0 (0x13c)
-#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) \
+ (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_LLP_H_BACKPORCH0 (0x14c)
-#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) (MIPI_TX_HS_LLP_H_BACKPORCH0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) \
+ (MIPI_TX_HS_LLP_H_BACKPORCH0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c)
-#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \
- + (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) \
+ (MIPI_TX_HS_LLP_H_FRONTPORCH0 + HS_OFFSET(M) \
+ + (0x4*N))
+
#define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194)
-#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) (MIPI_TX_HS_MC_FIFO_CTRL_EN \
- + (0x400*M))
+#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) \
+ (MIPI_TX_HS_MC_FIFO_CTRL_EN + HS_OFFSET(M))
+
#define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198)
#define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c)
#define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \
- (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + (0x400*M) + (0x4*N))
+ (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \
+ + (0x4*N))
#define SET_MC_FIFO_CHAN_ALLOC(ctrl, vc, sz) \
- kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, vc/2), \
- (vc % 2)*16, 16, sz)
+ kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, \
+ vc/2), (vc % 2)*16, 16, sz)
#define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0)
#define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4)
-#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \
- (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + (0x400*M) + (0x4*N))
-#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \
+#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \
+ (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + HS_OFFSET(M) \
+ + (0x4*N))
+#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \
kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \
(vc % 2)*16, 16, th)
--
2.7.4
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WARNING: multiple messages have this Message-ID (diff)
From: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com,
bob.j.paauwe@intel.com, edmund.j.dea@intel.com
Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 14/59] drm/kmb: Correct address offsets for mipi registers
Date: Tue, 30 Jun 2020 14:27:26 -0700 [thread overview]
Message-ID: <1593552491-23698-15-git-send-email-anitha.chrisanthus@intel.com> (raw)
In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com>
Mipi HS registers start at an additional offset of 0x400 which needs to be
added at the register macro definition and not at the read/write function
level.
v2: replaced calculations with macro to make code simpler
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
drivers/gpu/drm/kmb/kmb_dsi.c | 16 +++---
drivers/gpu/drm/kmb/kmb_regs.h | 116 ++++++++++++++++++++++++-----------------
2 files changed, 75 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 886a8ac..adcfe81 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -443,20 +443,20 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv,
*REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1
*REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3
*/
- offset = (frame_gen % 2) * 16;
- reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen);
+ offset = (frame_gen % 2)*16;
+ reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen/2);
kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->vsync_width);
- /*v backporch - same register config like vsync width */
- reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen);
+ /*v backporch - same register config like vsync width*/
+ reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen/2);
kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_backporch);
- /*v frontporch - same register config like vsync width */
- reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen);
+ /*v frontporch - same register config like vsync width*/
+ reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen/2);
kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_frontporch);
- /*v active - same register config like vsync width */
- reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen);
+ /*v active - same register config like vsync width*/
+ reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen/2);
kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_active);
/*hsyc width */
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index 9a5f371..4d6cf3d 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -395,10 +395,10 @@
* MIPI controller control register defines
***********************************************i****************************/
#define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400)
-#define MIPI_CTRL_HS_BASE_ADDR (0x400)
+#define HS_OFFSET(M) ((M + 1) * 0x400)
#define MIPI_TX_HS_CTRL (0x0)
-#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + (0x400*M))
+#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M))
#define HS_CTRL_EN (1 << 0)
#define HS_CTRL_CSIDSIN (1 << 2) /*1:CSI 0:DSI*/
#define TX_SOURCE (1 << 3) /*1:LCD, 0:DMA*/
@@ -411,7 +411,7 @@
#define HSCLKIDLE_CNT (1 << 24)
#define MIPI_TX_HS_SYNC_CFG (0x8)
#define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \
- + (0x400*M))
+ + HS_OFFSET(M))
#define LINE_SYNC_PKT_ENABLE (1 << 0)
#define FRAME_COUNTER_ACTIVE (1 << 1)
#define LINE_COUNTER_ACTIVE (1 << 2)
@@ -428,75 +428,93 @@
#define FRAME_GEN_EN(f) ((f) << 23)
#define HACT_WAIT_STOP(f) ((f) << 28)
#define MIPI_TX0_HS_FG0_SECT0_PH (0x40)
-#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \
- (0x400*M) + (0x2C*N) + (8*O))
-#define MIPI_TX_SECT_WC_MASK (0xffff)
-#define MIPI_TX_SECT_VC_MASK (3)
-#define MIPI_TX_SECT_VC_SHIFT (22)
-#define MIPI_TX_SECT_DT_MASK (0x3f)
-#define MIPI_TX_SECT_DT_SHIFT (16)
-#define MIPI_TX_SECT_DM_MASK (3)
-#define MIPI_TX_SECT_DM_SHIFT (24)
-#define MIPI_TX_SECT_DMA_PACKED (1<<26)
+#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \
+ HS_OFFSET(M) + (0x2C*N) + (8*O))
+#define MIPI_TX_SECT_WC_MASK (0xffff)
+#define MIPI_TX_SECT_VC_MASK (3)
+#define MIPI_TX_SECT_VC_SHIFT (22)
+#define MIPI_TX_SECT_DT_MASK (0x3f)
+#define MIPI_TX_SECT_DT_SHIFT (16)
+#define MIPI_TX_SECT_DM_MASK (3)
+#define MIPI_TX_SECT_DM_SHIFT (24)
+#define MIPI_TX_SECT_DMA_PACKED (1<<26)
#define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60)
#define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64)
-#define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \
- (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 + (0x400*M) + (0x2C*N))
+#define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \
+ (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 \
+ + HS_OFFSET(M) + (0x2C*N))
#define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44)
-#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \
- (MIPI_TX_HS_FG0_SECT0_LINE_CFG + (0x400*M) + (0x2C*N) + (8*O))
+#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \
+ (MIPI_TX_HS_FG0_SECT0_LINE_CFG + HS_OFFSET(M) \
+ + (0x2C*N) + (8*O))
#define MIPI_TX_HS_FG0_NUM_LINES (0x68)
-#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) (MIPI_TX_HS_FG0_NUM_LINES + \
- (0x400*M) + (0x2C*N))
+#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) \
+ (MIPI_TX_HS_FG0_NUM_LINES + HS_OFFSET(M) \
+ + (0x2C*N))
#define MIPI_TX_HS_VSYNC_WIDTHS0 (0x104)
-#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) (MIPI_TX_HS_VSYNC_WIDTHS0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) \
+ (MIPI_TX_HS_VSYNC_WIDTHS0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_V_BACKPORCHES0 (0x16c)
-#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) (MIPI_TX_HS_V_BACKPORCHES0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) \
+ (MIPI_TX_HS_V_BACKPORCHES0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_V_FRONTPORCHES0 (0x174)
-#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) (MIPI_TX_HS_V_FRONTPORCHES0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) \
+ (MIPI_TX_HS_V_FRONTPORCHES0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_V_ACTIVE0 (0x17c)
-#define MIPI_TXm_HS_V_ACTIVEn(M, N) (MIPI_TX_HS_V_ACTIVE0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_V_ACTIVEn(M, N) \
+ (MIPI_TX_HS_V_ACTIVE0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_HSYNC_WIDTH0 (0x10c)
-#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_HSYNC_WIDTH0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) \
+ (MIPI_TX_HS_HSYNC_WIDTH0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_H_BACKPORCH0 (0x11c)
-#define MIPI_TXm_HS_H_BACKPORCHn(M, N) (MIPI_TX_HS_H_BACKPORCH0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_H_BACKPORCHn(M, N) \
+ (MIPI_TX_HS_H_BACKPORCH0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_H_FRONTPORCH0 (0x12c)
-#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) (MIPI_TX_HS_H_FRONTPORCH0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) \
+ (MIPI_TX_HS_H_FRONTPORCH0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_H_ACTIVE0 (0x184)
-#define MIPI_TXm_HS_H_ACTIVEn(M, N) (MIPI_TX_HS_H_ACTIVE0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_H_ACTIVEn(M, N) \
+ (MIPI_TX_HS_H_ACTIVE0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_LLP_HSYNC_WIDTH0 (0x13c)
-#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) \
+ (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_LLP_H_BACKPORCH0 (0x14c)
-#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) (MIPI_TX_HS_LLP_H_BACKPORCH0 + \
- (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) \
+ (MIPI_TX_HS_LLP_H_BACKPORCH0 + HS_OFFSET(M) \
+ + (0x4*N))
#define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c)
-#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \
- + (0x400*M) + (0x4*N))
+#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) \
+ (MIPI_TX_HS_LLP_H_FRONTPORCH0 + HS_OFFSET(M) \
+ + (0x4*N))
+
#define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194)
-#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) (MIPI_TX_HS_MC_FIFO_CTRL_EN \
- + (0x400*M))
+#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) \
+ (MIPI_TX_HS_MC_FIFO_CTRL_EN + HS_OFFSET(M))
+
#define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198)
#define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c)
#define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \
- (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + (0x400*M) + (0x4*N))
+ (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \
+ + (0x4*N))
#define SET_MC_FIFO_CHAN_ALLOC(ctrl, vc, sz) \
- kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, vc/2), \
- (vc % 2)*16, 16, sz)
+ kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, \
+ vc/2), (vc % 2)*16, 16, sz)
#define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0)
#define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4)
-#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \
- (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + (0x400*M) + (0x4*N))
-#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \
+#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \
+ (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + HS_OFFSET(M) \
+ + (0x4*N))
+#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \
kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \
(vc % 2)*16, 16, th)
--
2.7.4
_______________________________________________
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next prev parent reply other threads:[~2020-06-30 21:29 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-30 21:27 [PATCH 00/59] Add support for Keem Bay DRM driver Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 01/59] drm/kmb: Add support for KeemBay Display Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 02/59] drm/kmb: Added id to kmb_plane Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 03/59] drm/kmb: Set correct values in the LAYERn_CFG register Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 04/59] drm/kmb: Use biwise operators for register definitions Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 05/59] drm/kmb: Updated kmb_plane_atomic_check Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 06/59] drm/kmb: Initial check-in for Mipi DSI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 07/59] drm/kmb: Set OUT_FORMAT_CFG register Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 08/59] drm/kmb: Added mipi_dsi_host initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 09/59] drm/kmb: Part 1 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 10/59] drm/kmb: Part 2 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 11/59] drm/kmb: Use correct mmio offset from data book Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 12/59] drm/kmb: Part3 of Mipi Tx initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 13/59] drm/kmb: Part4 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` Anitha Chrisanthus [this message]
2020-06-30 21:27 ` [Intel-gfx] [PATCH 14/59] drm/kmb: Correct address offsets for mipi registers Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 15/59] drm/kmb: Part5 of Mipi Tx Intitialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 16/59] drm/kmb: Part6 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 17/59] drm/kmb: Part7 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 18/59] drm/kmb: Part8 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 19/59] drm/kmb: Added ioremap/iounmap for register access Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 20/59] drm/kmb: Register IRQ for LCD Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 21/59] drm/kmb: IRQ handlers for LCD and mipi dsi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 23/59] drm/kmb: Additional register programming to update_plane Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 24/59] drm/kmb: Add ADV7535 bridge Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 25/59] drm/kmb: Display clock enable/disable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 26/59] drm/kmb: rebase to newer kernel version Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 27/59] drm/kmb: minor name change to match device tree Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 28/59] drm/kmb: Changed MMIO size Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 29/59] drm/kmb: Defer Probe Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 30/59] drm/kmb: call bridge init in the very beginning Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 31/59] drm/kmb: Cleanup probe functions Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 32/59] drm/kmb: Revert dsi_host back to a static variable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 33/59] drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 35/59] drm/kmb: Remove declaration of irq_lcd/irq_mipi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 36/59] drm/kmb: Enable MIPI TX HS Test Pattern Generation Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 37/59] drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 38/59] drm/kmb: Mipi DPHY initialization changes Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 39/59] drm/kmb: Fixed driver unload Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 40/59] drm/kmb: Added LCD_TEST config Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 41/59] drm/kmb: Changes for LCD to Mipi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 42/59] drm/kmb: Update LCD programming to match MIPI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 43/59] drm/kmb: Changed name of driver to kmb-drm Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 44/59] drm/kmb: Mipi settings from input timings Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 45/59] drm/kmb: Enable LCD interrupts Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 46/59] drm/kmb: Enable LCD interrupts during modeset Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 47/59] drm/kmb: Don’t inadvertantly disable LCD controller Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 48/59] drm/kmb: SWAP R and B LCD Layer order Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 49/59] drm/kmb: Disable ping pong mode Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 50/59] drm/kmb: Do the layer initializations only once Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 51/59] drm/kmb: Write to LCD_LAYERn_CFG " Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 52/59] drm/kmb: Cleaned up code Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 53/59] drm/kmb: disable the LCD layer in EOF irq handler Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 54/59] drm/kmb: Initialize uninitialized variables Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 55/59] drm/kmb: Added useful messages in LCD ISR Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 56/59] kmb/drm: Prune unsupported modes Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 57/59] drm/kmb: workaround for dma undeflow issue Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 58/59] drm/kmb: Get System Clock from SCMI Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 59/59] drm/kmb: work around for planar formats Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 22:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for Keem Bay DRM driver Patchwork
2020-07-01 3:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-01 6:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-07-01 7:01 ` [PATCH 00/59] " Sam Ravnborg
2020-07-01 7:01 ` [Intel-gfx] " Sam Ravnborg
2020-07-01 21:53 ` Chrisanthus, Anitha
2020-07-01 21:53 ` [Intel-gfx] " Chrisanthus, Anitha
2020-07-02 10:19 ` Neil Armstrong
2020-07-02 10:19 ` [Intel-gfx] " Neil Armstrong
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