From: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com,
bob.j.paauwe@intel.com, edmund.j.dea@intel.com
Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org,
rodrigo.vivi@intel.com
Subject: [PATCH 03/59] drm/kmb: Set correct values in the LAYERn_CFG register
Date: Tue, 30 Jun 2020 14:27:15 -0700 [thread overview]
Message-ID: <1593552491-23698-4-git-send-email-anitha.chrisanthus@intel.com> (raw)
In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com>
During update plane, set the layer format, bpp, fifo level,
RGB order, Cb/Cr order etc. in the LAYER_CFG register.
v2: Return val in set_pixel and set_bpp instead of passing in pointer,
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
drivers/gpu/drm/kmb/kmb_plane.c | 145 ++++++++++++++++++++++++++++++----
drivers/gpu/drm/kmb/kmb_regs.h | 167 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 298 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index b9d8d38..9f1e44f 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -53,6 +53,119 @@ static int kmb_plane_atomic_check(struct drm_plane *plane,
return 0;
}
+unsigned int set_pixel_format(u32 format)
+{
+ unsigned int val = 0;
+
+ switch (format) {
+ /*planar formats */
+ case DRM_FORMAT_YUV444:
+ val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_YVU444:
+ val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ case DRM_FORMAT_YUV422:
+ val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_YVU422:
+ val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ case DRM_FORMAT_YUV420:
+ val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_YVU420:
+ val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ case DRM_FORMAT_NV12:
+ val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_NV21:
+ val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ /* packed formats */
+ case DRM_FORMAT_RGB332:
+ val = LCD_LAYER_FORMAT_RGB332;
+ break;
+ case DRM_FORMAT_XBGR4444:
+ val = LCD_LAYER_FORMAT_RGBX4444 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_ARGB4444:
+ val = LCD_LAYER_FORMAT_RGBA4444;
+ break;
+ case DRM_FORMAT_ABGR4444:
+ val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_XRGB1555:
+ val = LCD_LAYER_FORMAT_XRGB1555;
+ break;
+ case DRM_FORMAT_XBGR1555:
+ val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_ARGB1555:
+ val = LCD_LAYER_FORMAT_RGBA1555;
+ break;
+ case DRM_FORMAT_ABGR1555:
+ val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_RGB565:
+ val = LCD_LAYER_FORMAT_RGB565;
+ break;
+ case DRM_FORMAT_BGR565:
+ val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_RGB888:
+ val = LCD_LAYER_FORMAT_RGB888;
+ break;
+ case DRM_FORMAT_BGR888:
+ val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_XRGB8888:
+ val = LCD_LAYER_FORMAT_RGBX8888;
+ break;
+ case DRM_FORMAT_XBGR8888:
+ val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_ARGB8888:
+ val = LCD_LAYER_FORMAT_RGBA8888;
+ break;
+ case DRM_FORMAT_ABGR8888:
+ val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER;
+ break;
+ }
+ return val;
+}
+
+unsigned int set_bits_per_pixel(const struct drm_format_info *format)
+{
+ int i;
+ u32 bpp = 0;
+ unsigned int val = 0;
+
+ for (i = 0; i < format->num_planes; i++)
+ bpp += 8*format->cpp[i];
+
+ switch (bpp) {
+ case 8:
+ val = LCD_LAYER_8BPP;
+ break;
+ case 16:
+ val = LCD_LAYER_16BPP;
+ break;
+ case 24:
+ val = LCD_LAYER_24BPP;
+ break;
+ case 32:
+ val = LCD_LAYER_32BPP;
+ break;
+ }
+ return val;
+}
+
static void kmb_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *state)
{
@@ -64,7 +177,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
unsigned int dma_len;
struct kmb_plane *kmb_plane = to_kmb_plane(plane);
unsigned int dma_cfg;
- unsigned int ctrl = 0;
+ unsigned int ctrl = 0, val = 0;
+ unsigned int src_w, src_h, crtc_x, crtc_y;
unsigned char plane_id = kmb_plane->id;
if (!fb)
@@ -72,6 +186,22 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
lcd = plane->dev->dev_private;
+ src_w = plane->state->src_w >> 16;
+ src_h = plane->state->src_h >> 16;
+ crtc_x = plane->state->crtc_x;
+ crtc_y = plane->state->crtc_y;
+
+ kmb_write(lcd, LCD_LAYERn_WIDTH(plane_id), src_w-1);
+ kmb_write(lcd, LCD_LAYERn_HEIGHT(plane_id), src_h-1);
+ kmb_write(lcd, LCD_LAYERn_COL_START(plane_id), crtc_x);
+ kmb_write(lcd, LCD_LAYERn_ROW_START(plane_id), crtc_y);
+
+ val = set_pixel_format(fb->format->format);
+ val |= set_bits_per_pixel(fb->format);
+ /*CHECKME Leon drvr sets it to 50 try this for now */
+ val |= LCD_LAYER_FIFO_50;
+ kmb_write(lcd, LCD_LAYERn_CFG(plane_id), val);
+
switch (plane_id) {
case LAYER_0:
ctrl = LCD_CTRL_VL1_ENABLE;
@@ -92,12 +222,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
| LCD_CTRL_OUTPUT_ENABLED;
kmb_write(lcd, LCD_CONTROL, ctrl);
- /* TBD */
- /*set LCD_LAYERn_WIDTH, LCD_LAYERn_HEIGHT, LCD_LAYERn_COL_START,
- * LCD_LAYERn_ROW_START, LCD_LAYERn_CFG
- * CFG should set the pixel format, FIFO level and BPP
- */
-
/*TBD check visible? */
/* we may have to set LCD_DMA_VSTRIDE_ENABLE in the future */
@@ -202,9 +326,6 @@ static const u32 kmb_formats_g[] = {
DRM_FORMAT_RGB888, DRM_FORMAT_BGR888,
DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888,
- DRM_FORMAT_XRGB2101010, DRM_FORMAT_XBGR2101010,
- DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
- DRM_FORMAT_UYVY, DRM_FORMAT_VYUY,
};
/* video layer (0 & 1) formats, packed and planar formats are supported */
@@ -219,11 +340,7 @@ static const u32 kmb_formats_v[] = {
DRM_FORMAT_RGB888, DRM_FORMAT_BGR888,
DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888,
- DRM_FORMAT_XRGB2101010, DRM_FORMAT_XBGR2101010,
- DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
- DRM_FORMAT_UYVY, DRM_FORMAT_VYUY,
/*planar formats */
- DRM_FORMAT_YUV411, DRM_FORMAT_YVU411,
DRM_FORMAT_YUV420, DRM_FORMAT_YVU420,
DRM_FORMAT_YUV422, DRM_FORMAT_YVU422,
DRM_FORMAT_YUV444, DRM_FORMAT_YVU444,
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index 95cf932..9bf2b9f 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -381,6 +381,173 @@
/* bit 10 */
#define LCD_DMA_LAYER_V_STRIDE_EN (0x400)
+/******************************************************************************
+ * LCD controller Layer config register
+ ******************************************************************************/
+/* ---bit 1:2 */
+/* enable horizontal scaling,default is
+ * no scaling
+ */
+#define LCD_LAYER_SCALE_H (0x0002)
+/* enable vertical scaling*/
+#define LCD_LAYER_SCALE_V (0x0004)
+/* enable vertical and horizontal
+ * scaling
+ */
+#define LCD_LAYER_SCALE_H_V (0x0006)
+/* --- bit 3*/
+/* enable CSC, default is bypassed*/
+#define LCD_LAYER_CSC_EN (0x0008)
+/* --- bit 4:5*/
+/* use static alpha value for layer,
+ * default is disabled
+ */
+#define LCD_LAYER_ALPHA_STATIC (0x10)
+/* use embedded value for alpha blending*/
+#define LCD_LAYER_ALPHA_EMBED (0x20)
+/* use static alpha and embedded value,
+ * by multiplication
+ */
+#define LCD_LAYER_ALPHA_COMBI (0x30)
+/* --- bit 6*/
+/* indicates that the RGB values have
+ * been multiplied with alpha
+ */
+#define LCD_LAYER_ALPHA_PREMULT (0x40)
+/* --- bit 7*/
+#define LCD_LAYER_INVERT_COL (0x80)
+/* enable color inversion,
+ * default is not inverted
+ */
+/* --- bit 8*/
+/* enable transparency */
+#define LCD_LAYER_TRANSPARENT_EN (0x100)
+/* --- bit 9:13*/
+/* default Layer config */
+#define LCD_LAYER_FORMAT_YCBCR444PLAN (0x0000)
+#define LCD_LAYER_FORMAT_YCBCR422PLAN (0x0200)
+#define LCD_LAYER_FORMAT_YCBCR420PLAN (0x0400)
+#define LCD_LAYER_FORMAT_RGB888PLAN (0x0600)
+#define LCD_LAYER_FORMAT_YCBCR444LIN (0x0800)
+#define LCD_LAYER_FORMAT_YCBCR422LIN (0x0A00)
+#define LCD_LAYER_FORMAT_RGB888 (0x0C00)
+#define LCD_LAYER_FORMAT_RGBA8888 (0x0E00)
+#define LCD_LAYER_FORMAT_RGBX8888 (0x1000)
+#define LCD_LAYER_FORMAT_RGB565 (0x1200)
+#define LCD_LAYER_FORMAT_RGBA1555 (0x1400)
+#define LCD_LAYER_FORMAT_XRGB1555 (0x1600)
+#define LCD_LAYER_FORMAT_RGB444 (0x1800)
+#define LCD_LAYER_FORMAT_RGBA4444 (0x1A00)
+#define LCD_LAYER_FORMAT_RGBX4444 (0x1C00)
+#define LCD_LAYER_FORMAT_RGB332 (0x1E00)
+#define LCD_LAYER_FORMAT_RGBA3328 (0x2000)
+#define LCD_LAYER_FORMAT_RGBX3328 (0x2200)
+#define LCD_LAYER_FORMAT_CLUT (0x2400)
+#define LCD_LAYER_FORMAT_NV12 (0x3800)
+/* --- bit 14*/
+/* planar storege format */
+#define LCD_LAYER_PLANAR_STORAGE (0x4000)
+/* --- bit 15:16*/
+#define LCD_LAYER_8BPP (0x00000)
+#define LCD_LAYER_16BPP (0x08000)
+#define LCD_LAYER_24BPP (0x10000)
+#define LCD_LAYER_32BPP (0x18000)
+/* --- bit 17*/
+/* Y after CRCb,
+ * default is Y before crcb
+ */
+#define LCD_LAYER_Y_ORDER (0x020000)
+/* --- bit 18*/
+/* CR before Cb,
+ * default is CB before Cr
+ */
+#define LCD_LAYER_CRCB_ORDER (0x040000)
+/*--- but 19*/
+/* BGR order, default is RGB */
+#define LCD_LAYER_BGR_ORDER (0x080000)
+/* ---bit 20:21*/
+/* 2 entry clut, 1bpp */
+#define LCD_LAYER_LUT_2ENT (0x000000)
+/* 4 entry clut, 2bpp */
+#define LCD_LAYER_LUT_4ENT (0x100000)
+/* 18 entry clut, 4bpp */
+#define LCD_LAYER_LUT_16ENT (0x200000)
+/*--- bit 22:24*/
+/* no flip or rotaton */
+#define LCD_LAYER_NO_FLIP (0x000000)
+/* flip vertical */
+#define LCD_LAYER_FLIP_V (0x400000)
+/* flip horizontal */
+#define LCD_LAYER_FLIP_H (0x800000)
+/* rotate right 90 */
+#define LCD_LAYER_ROT_R90 (0xC00000)
+/* rotate left 90 */
+#define LCD_LAYER_ROT_L90 (0x1000000)
+/* rotate 180 (flip H & V ) */
+#define LCD_LAYER_ROT_180 (0x1400000)
+/* --- bit 25:26*/
+/* fifo empty */
+#define LCD_LAYER_FIFO_00 (0x0000000)
+/* fifo 25% */
+#define LCD_LAYER_FIFO_25 (0x2000000)
+/* fifo 50% */
+#define LCD_LAYER_FIFO_50 (0x4000000)
+/* fifo 100% , full */
+#define LCD_LAYER_FIFO_100 (0x6000000)
+
+/* --- bit 27:29*/
+#define LCD_LAYER_INTERLEAVE_DIS (0x00000000)
+#define LCD_LAYER_INTERLEAVE_V (0x08000000)
+#define LCD_LAYER_INTERLEAVE_H (0x10000000)
+#define LCD_LAYER_INTERLEAVE_CH (0x18000000)
+#define LCD_LAYER_INTERLEAVE_V_SUB (0x20000000)
+#define LCD_LAYER_INTERLEAVE_H_SUB (0x28000000)
+#define LCD_LAYER_INTERLEAVE_CH_SUB (0x30000000)
+/*bit 30*/
+#define LCD_LAYER_INTER_POS_EVEN (0x00000000)
+#define LCD_LAYER_INTER_POS_ODD (0x40000000)
+
+/****************************************************************************
+ * LCD controller output format register defines
+ ****************************************************************************/
+/* --- bits 0:4*/
+#define D_LCD_OUTF_FORMAT_RGB121212 (0x00 << 0)
+#define D_LCD_OUTF_FORMAT_RGB101010 (0x01 << 0)
+#define D_LCD_OUTF_FORMAT_RGB888 (0x02 << 0)
+#define D_LCD_OUTF_FORMAT_RGB666 (0x03 << 0)
+#define D_LCD_OUTF_FORMAT_RGB565 (0x04 << 0)
+#define D_LCD_OUTF_FORMAT_RGB444 (0x05 << 0)
+#define D_LCD_OUTF_FORMAT_MRGB121212 (0x10 << 0)
+#define D_LCD_OUTF_FORMAT_MRGB101010 (0x11 << 0)
+#define D_LCD_OUTF_FORMAT_MRGB888 (0x12 << 0)
+#define D_LCD_OUTF_FORMAT_MRGB666 (0x13 << 0)
+#define D_LCD_OUTF_FORMAT_MRGB565 (0x14 << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08 << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09 << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR420_8B (0x0A << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR420_10B (0x0B << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR420_12B (0x0C << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR422_8B (0x0D << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR422_10B (0x0E << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR444 (0x0F << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18 << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19 << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR444 (0x1F << 0)
+/* --- bit 5*/
+/* default is 0, RGB order */
+#define D_LCD_OUTF_BGR_ORDER (1 << 5)
+/* --- bit 6*/
+/* Y after CB/Cr, default is Y before CB/CR */
+#define D_LCD_OUTF_Y_ORDER (1 << 6)
+/* --- bit 7*/
+/* Cr before Cb, default is Cb before Cr */
+#define D_LCD_OUTF_CRCB_ORDER (1 << 7)
+
/* **************************************************************************
* LCD controller control register defines
****************************************************************************
--
2.7.4
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WARNING: multiple messages have this Message-ID (diff)
From: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com,
bob.j.paauwe@intel.com, edmund.j.dea@intel.com
Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 03/59] drm/kmb: Set correct values in the LAYERn_CFG register
Date: Tue, 30 Jun 2020 14:27:15 -0700 [thread overview]
Message-ID: <1593552491-23698-4-git-send-email-anitha.chrisanthus@intel.com> (raw)
In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com>
During update plane, set the layer format, bpp, fifo level,
RGB order, Cb/Cr order etc. in the LAYER_CFG register.
v2: Return val in set_pixel and set_bpp instead of passing in pointer,
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
drivers/gpu/drm/kmb/kmb_plane.c | 145 ++++++++++++++++++++++++++++++----
drivers/gpu/drm/kmb/kmb_regs.h | 167 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 298 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index b9d8d38..9f1e44f 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -53,6 +53,119 @@ static int kmb_plane_atomic_check(struct drm_plane *plane,
return 0;
}
+unsigned int set_pixel_format(u32 format)
+{
+ unsigned int val = 0;
+
+ switch (format) {
+ /*planar formats */
+ case DRM_FORMAT_YUV444:
+ val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_YVU444:
+ val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ case DRM_FORMAT_YUV422:
+ val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_YVU422:
+ val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ case DRM_FORMAT_YUV420:
+ val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_YVU420:
+ val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ case DRM_FORMAT_NV12:
+ val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_NV21:
+ val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ /* packed formats */
+ case DRM_FORMAT_RGB332:
+ val = LCD_LAYER_FORMAT_RGB332;
+ break;
+ case DRM_FORMAT_XBGR4444:
+ val = LCD_LAYER_FORMAT_RGBX4444 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_ARGB4444:
+ val = LCD_LAYER_FORMAT_RGBA4444;
+ break;
+ case DRM_FORMAT_ABGR4444:
+ val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_XRGB1555:
+ val = LCD_LAYER_FORMAT_XRGB1555;
+ break;
+ case DRM_FORMAT_XBGR1555:
+ val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_ARGB1555:
+ val = LCD_LAYER_FORMAT_RGBA1555;
+ break;
+ case DRM_FORMAT_ABGR1555:
+ val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_RGB565:
+ val = LCD_LAYER_FORMAT_RGB565;
+ break;
+ case DRM_FORMAT_BGR565:
+ val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_RGB888:
+ val = LCD_LAYER_FORMAT_RGB888;
+ break;
+ case DRM_FORMAT_BGR888:
+ val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_XRGB8888:
+ val = LCD_LAYER_FORMAT_RGBX8888;
+ break;
+ case DRM_FORMAT_XBGR8888:
+ val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_ARGB8888:
+ val = LCD_LAYER_FORMAT_RGBA8888;
+ break;
+ case DRM_FORMAT_ABGR8888:
+ val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER;
+ break;
+ }
+ return val;
+}
+
+unsigned int set_bits_per_pixel(const struct drm_format_info *format)
+{
+ int i;
+ u32 bpp = 0;
+ unsigned int val = 0;
+
+ for (i = 0; i < format->num_planes; i++)
+ bpp += 8*format->cpp[i];
+
+ switch (bpp) {
+ case 8:
+ val = LCD_LAYER_8BPP;
+ break;
+ case 16:
+ val = LCD_LAYER_16BPP;
+ break;
+ case 24:
+ val = LCD_LAYER_24BPP;
+ break;
+ case 32:
+ val = LCD_LAYER_32BPP;
+ break;
+ }
+ return val;
+}
+
static void kmb_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *state)
{
@@ -64,7 +177,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
unsigned int dma_len;
struct kmb_plane *kmb_plane = to_kmb_plane(plane);
unsigned int dma_cfg;
- unsigned int ctrl = 0;
+ unsigned int ctrl = 0, val = 0;
+ unsigned int src_w, src_h, crtc_x, crtc_y;
unsigned char plane_id = kmb_plane->id;
if (!fb)
@@ -72,6 +186,22 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
lcd = plane->dev->dev_private;
+ src_w = plane->state->src_w >> 16;
+ src_h = plane->state->src_h >> 16;
+ crtc_x = plane->state->crtc_x;
+ crtc_y = plane->state->crtc_y;
+
+ kmb_write(lcd, LCD_LAYERn_WIDTH(plane_id), src_w-1);
+ kmb_write(lcd, LCD_LAYERn_HEIGHT(plane_id), src_h-1);
+ kmb_write(lcd, LCD_LAYERn_COL_START(plane_id), crtc_x);
+ kmb_write(lcd, LCD_LAYERn_ROW_START(plane_id), crtc_y);
+
+ val = set_pixel_format(fb->format->format);
+ val |= set_bits_per_pixel(fb->format);
+ /*CHECKME Leon drvr sets it to 50 try this for now */
+ val |= LCD_LAYER_FIFO_50;
+ kmb_write(lcd, LCD_LAYERn_CFG(plane_id), val);
+
switch (plane_id) {
case LAYER_0:
ctrl = LCD_CTRL_VL1_ENABLE;
@@ -92,12 +222,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
| LCD_CTRL_OUTPUT_ENABLED;
kmb_write(lcd, LCD_CONTROL, ctrl);
- /* TBD */
- /*set LCD_LAYERn_WIDTH, LCD_LAYERn_HEIGHT, LCD_LAYERn_COL_START,
- * LCD_LAYERn_ROW_START, LCD_LAYERn_CFG
- * CFG should set the pixel format, FIFO level and BPP
- */
-
/*TBD check visible? */
/* we may have to set LCD_DMA_VSTRIDE_ENABLE in the future */
@@ -202,9 +326,6 @@ static const u32 kmb_formats_g[] = {
DRM_FORMAT_RGB888, DRM_FORMAT_BGR888,
DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888,
- DRM_FORMAT_XRGB2101010, DRM_FORMAT_XBGR2101010,
- DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
- DRM_FORMAT_UYVY, DRM_FORMAT_VYUY,
};
/* video layer (0 & 1) formats, packed and planar formats are supported */
@@ -219,11 +340,7 @@ static const u32 kmb_formats_v[] = {
DRM_FORMAT_RGB888, DRM_FORMAT_BGR888,
DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888,
- DRM_FORMAT_XRGB2101010, DRM_FORMAT_XBGR2101010,
- DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
- DRM_FORMAT_UYVY, DRM_FORMAT_VYUY,
/*planar formats */
- DRM_FORMAT_YUV411, DRM_FORMAT_YVU411,
DRM_FORMAT_YUV420, DRM_FORMAT_YVU420,
DRM_FORMAT_YUV422, DRM_FORMAT_YVU422,
DRM_FORMAT_YUV444, DRM_FORMAT_YVU444,
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index 95cf932..9bf2b9f 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -381,6 +381,173 @@
/* bit 10 */
#define LCD_DMA_LAYER_V_STRIDE_EN (0x400)
+/******************************************************************************
+ * LCD controller Layer config register
+ ******************************************************************************/
+/* ---bit 1:2 */
+/* enable horizontal scaling,default is
+ * no scaling
+ */
+#define LCD_LAYER_SCALE_H (0x0002)
+/* enable vertical scaling*/
+#define LCD_LAYER_SCALE_V (0x0004)
+/* enable vertical and horizontal
+ * scaling
+ */
+#define LCD_LAYER_SCALE_H_V (0x0006)
+/* --- bit 3*/
+/* enable CSC, default is bypassed*/
+#define LCD_LAYER_CSC_EN (0x0008)
+/* --- bit 4:5*/
+/* use static alpha value for layer,
+ * default is disabled
+ */
+#define LCD_LAYER_ALPHA_STATIC (0x10)
+/* use embedded value for alpha blending*/
+#define LCD_LAYER_ALPHA_EMBED (0x20)
+/* use static alpha and embedded value,
+ * by multiplication
+ */
+#define LCD_LAYER_ALPHA_COMBI (0x30)
+/* --- bit 6*/
+/* indicates that the RGB values have
+ * been multiplied with alpha
+ */
+#define LCD_LAYER_ALPHA_PREMULT (0x40)
+/* --- bit 7*/
+#define LCD_LAYER_INVERT_COL (0x80)
+/* enable color inversion,
+ * default is not inverted
+ */
+/* --- bit 8*/
+/* enable transparency */
+#define LCD_LAYER_TRANSPARENT_EN (0x100)
+/* --- bit 9:13*/
+/* default Layer config */
+#define LCD_LAYER_FORMAT_YCBCR444PLAN (0x0000)
+#define LCD_LAYER_FORMAT_YCBCR422PLAN (0x0200)
+#define LCD_LAYER_FORMAT_YCBCR420PLAN (0x0400)
+#define LCD_LAYER_FORMAT_RGB888PLAN (0x0600)
+#define LCD_LAYER_FORMAT_YCBCR444LIN (0x0800)
+#define LCD_LAYER_FORMAT_YCBCR422LIN (0x0A00)
+#define LCD_LAYER_FORMAT_RGB888 (0x0C00)
+#define LCD_LAYER_FORMAT_RGBA8888 (0x0E00)
+#define LCD_LAYER_FORMAT_RGBX8888 (0x1000)
+#define LCD_LAYER_FORMAT_RGB565 (0x1200)
+#define LCD_LAYER_FORMAT_RGBA1555 (0x1400)
+#define LCD_LAYER_FORMAT_XRGB1555 (0x1600)
+#define LCD_LAYER_FORMAT_RGB444 (0x1800)
+#define LCD_LAYER_FORMAT_RGBA4444 (0x1A00)
+#define LCD_LAYER_FORMAT_RGBX4444 (0x1C00)
+#define LCD_LAYER_FORMAT_RGB332 (0x1E00)
+#define LCD_LAYER_FORMAT_RGBA3328 (0x2000)
+#define LCD_LAYER_FORMAT_RGBX3328 (0x2200)
+#define LCD_LAYER_FORMAT_CLUT (0x2400)
+#define LCD_LAYER_FORMAT_NV12 (0x3800)
+/* --- bit 14*/
+/* planar storege format */
+#define LCD_LAYER_PLANAR_STORAGE (0x4000)
+/* --- bit 15:16*/
+#define LCD_LAYER_8BPP (0x00000)
+#define LCD_LAYER_16BPP (0x08000)
+#define LCD_LAYER_24BPP (0x10000)
+#define LCD_LAYER_32BPP (0x18000)
+/* --- bit 17*/
+/* Y after CRCb,
+ * default is Y before crcb
+ */
+#define LCD_LAYER_Y_ORDER (0x020000)
+/* --- bit 18*/
+/* CR before Cb,
+ * default is CB before Cr
+ */
+#define LCD_LAYER_CRCB_ORDER (0x040000)
+/*--- but 19*/
+/* BGR order, default is RGB */
+#define LCD_LAYER_BGR_ORDER (0x080000)
+/* ---bit 20:21*/
+/* 2 entry clut, 1bpp */
+#define LCD_LAYER_LUT_2ENT (0x000000)
+/* 4 entry clut, 2bpp */
+#define LCD_LAYER_LUT_4ENT (0x100000)
+/* 18 entry clut, 4bpp */
+#define LCD_LAYER_LUT_16ENT (0x200000)
+/*--- bit 22:24*/
+/* no flip or rotaton */
+#define LCD_LAYER_NO_FLIP (0x000000)
+/* flip vertical */
+#define LCD_LAYER_FLIP_V (0x400000)
+/* flip horizontal */
+#define LCD_LAYER_FLIP_H (0x800000)
+/* rotate right 90 */
+#define LCD_LAYER_ROT_R90 (0xC00000)
+/* rotate left 90 */
+#define LCD_LAYER_ROT_L90 (0x1000000)
+/* rotate 180 (flip H & V ) */
+#define LCD_LAYER_ROT_180 (0x1400000)
+/* --- bit 25:26*/
+/* fifo empty */
+#define LCD_LAYER_FIFO_00 (0x0000000)
+/* fifo 25% */
+#define LCD_LAYER_FIFO_25 (0x2000000)
+/* fifo 50% */
+#define LCD_LAYER_FIFO_50 (0x4000000)
+/* fifo 100% , full */
+#define LCD_LAYER_FIFO_100 (0x6000000)
+
+/* --- bit 27:29*/
+#define LCD_LAYER_INTERLEAVE_DIS (0x00000000)
+#define LCD_LAYER_INTERLEAVE_V (0x08000000)
+#define LCD_LAYER_INTERLEAVE_H (0x10000000)
+#define LCD_LAYER_INTERLEAVE_CH (0x18000000)
+#define LCD_LAYER_INTERLEAVE_V_SUB (0x20000000)
+#define LCD_LAYER_INTERLEAVE_H_SUB (0x28000000)
+#define LCD_LAYER_INTERLEAVE_CH_SUB (0x30000000)
+/*bit 30*/
+#define LCD_LAYER_INTER_POS_EVEN (0x00000000)
+#define LCD_LAYER_INTER_POS_ODD (0x40000000)
+
+/****************************************************************************
+ * LCD controller output format register defines
+ ****************************************************************************/
+/* --- bits 0:4*/
+#define D_LCD_OUTF_FORMAT_RGB121212 (0x00 << 0)
+#define D_LCD_OUTF_FORMAT_RGB101010 (0x01 << 0)
+#define D_LCD_OUTF_FORMAT_RGB888 (0x02 << 0)
+#define D_LCD_OUTF_FORMAT_RGB666 (0x03 << 0)
+#define D_LCD_OUTF_FORMAT_RGB565 (0x04 << 0)
+#define D_LCD_OUTF_FORMAT_RGB444 (0x05 << 0)
+#define D_LCD_OUTF_FORMAT_MRGB121212 (0x10 << 0)
+#define D_LCD_OUTF_FORMAT_MRGB101010 (0x11 << 0)
+#define D_LCD_OUTF_FORMAT_MRGB888 (0x12 << 0)
+#define D_LCD_OUTF_FORMAT_MRGB666 (0x13 << 0)
+#define D_LCD_OUTF_FORMAT_MRGB565 (0x14 << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08 << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09 << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR420_8B (0x0A << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR420_10B (0x0B << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR420_12B (0x0C << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR422_8B (0x0D << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR422_10B (0x0E << 0)
+#define D_LCD_OUTF_FORMAT_YCBCR444 (0x0F << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18 << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19 << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E << 0)
+#define D_LCD_OUTF_FORMAT_MYCBCR444 (0x1F << 0)
+/* --- bit 5*/
+/* default is 0, RGB order */
+#define D_LCD_OUTF_BGR_ORDER (1 << 5)
+/* --- bit 6*/
+/* Y after CB/Cr, default is Y before CB/CR */
+#define D_LCD_OUTF_Y_ORDER (1 << 6)
+/* --- bit 7*/
+/* Cr before Cb, default is Cb before Cr */
+#define D_LCD_OUTF_CRCB_ORDER (1 << 7)
+
/* **************************************************************************
* LCD controller control register defines
****************************************************************************
--
2.7.4
_______________________________________________
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next prev parent reply other threads:[~2020-06-30 21:29 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-30 21:27 [PATCH 00/59] Add support for Keem Bay DRM driver Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 01/59] drm/kmb: Add support for KeemBay Display Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 02/59] drm/kmb: Added id to kmb_plane Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` Anitha Chrisanthus [this message]
2020-06-30 21:27 ` [Intel-gfx] [PATCH 03/59] drm/kmb: Set correct values in the LAYERn_CFG register Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 04/59] drm/kmb: Use biwise operators for register definitions Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 05/59] drm/kmb: Updated kmb_plane_atomic_check Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 06/59] drm/kmb: Initial check-in for Mipi DSI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 07/59] drm/kmb: Set OUT_FORMAT_CFG register Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 08/59] drm/kmb: Added mipi_dsi_host initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 09/59] drm/kmb: Part 1 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 10/59] drm/kmb: Part 2 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 11/59] drm/kmb: Use correct mmio offset from data book Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 12/59] drm/kmb: Part3 of Mipi Tx initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 13/59] drm/kmb: Part4 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 14/59] drm/kmb: Correct address offsets for mipi registers Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 15/59] drm/kmb: Part5 of Mipi Tx Intitialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 16/59] drm/kmb: Part6 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 17/59] drm/kmb: Part7 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 18/59] drm/kmb: Part8 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 19/59] drm/kmb: Added ioremap/iounmap for register access Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 20/59] drm/kmb: Register IRQ for LCD Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 21/59] drm/kmb: IRQ handlers for LCD and mipi dsi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 23/59] drm/kmb: Additional register programming to update_plane Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 24/59] drm/kmb: Add ADV7535 bridge Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 25/59] drm/kmb: Display clock enable/disable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 26/59] drm/kmb: rebase to newer kernel version Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 27/59] drm/kmb: minor name change to match device tree Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 28/59] drm/kmb: Changed MMIO size Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 29/59] drm/kmb: Defer Probe Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 30/59] drm/kmb: call bridge init in the very beginning Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 31/59] drm/kmb: Cleanup probe functions Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 32/59] drm/kmb: Revert dsi_host back to a static variable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 33/59] drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 35/59] drm/kmb: Remove declaration of irq_lcd/irq_mipi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 36/59] drm/kmb: Enable MIPI TX HS Test Pattern Generation Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 37/59] drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 38/59] drm/kmb: Mipi DPHY initialization changes Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 39/59] drm/kmb: Fixed driver unload Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 40/59] drm/kmb: Added LCD_TEST config Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 41/59] drm/kmb: Changes for LCD to Mipi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 42/59] drm/kmb: Update LCD programming to match MIPI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 43/59] drm/kmb: Changed name of driver to kmb-drm Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 44/59] drm/kmb: Mipi settings from input timings Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 45/59] drm/kmb: Enable LCD interrupts Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 46/59] drm/kmb: Enable LCD interrupts during modeset Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 47/59] drm/kmb: Don’t inadvertantly disable LCD controller Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 48/59] drm/kmb: SWAP R and B LCD Layer order Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 49/59] drm/kmb: Disable ping pong mode Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 50/59] drm/kmb: Do the layer initializations only once Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 51/59] drm/kmb: Write to LCD_LAYERn_CFG " Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 52/59] drm/kmb: Cleaned up code Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 53/59] drm/kmb: disable the LCD layer in EOF irq handler Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 54/59] drm/kmb: Initialize uninitialized variables Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 55/59] drm/kmb: Added useful messages in LCD ISR Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 56/59] kmb/drm: Prune unsupported modes Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 57/59] drm/kmb: workaround for dma undeflow issue Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 58/59] drm/kmb: Get System Clock from SCMI Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 59/59] drm/kmb: work around for planar formats Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 22:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for Keem Bay DRM driver Patchwork
2020-07-01 3:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-01 6:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-07-01 7:01 ` [PATCH 00/59] " Sam Ravnborg
2020-07-01 7:01 ` [Intel-gfx] " Sam Ravnborg
2020-07-01 21:53 ` Chrisanthus, Anitha
2020-07-01 21:53 ` [Intel-gfx] " Chrisanthus, Anitha
2020-07-02 10:19 ` Neil Armstrong
2020-07-02 10:19 ` [Intel-gfx] " Neil Armstrong
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all data and code used by this external index.