From: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com,
bob.j.paauwe@intel.com, edmund.j.dea@intel.com
Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org,
rodrigo.vivi@intel.com
Subject: [PATCH 40/59] drm/kmb: Added LCD_TEST config
Date: Tue, 30 Jun 2020 14:27:52 -0700 [thread overview]
Message-ID: <1593552491-23698-41-git-send-email-anitha.chrisanthus@intel.com> (raw)
In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com>
To run modetest without ADV driver, enable LCD_TEST and FCC_TEST.
Also made front porches 0, and some changes in the plane init.
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
---
drivers/gpu/drm/kmb/kmb_crtc.c | 13 +++----
drivers/gpu/drm/kmb/kmb_drv.c | 6 +--
drivers/gpu/drm/kmb/kmb_drv.h | 3 +-
drivers/gpu/drm/kmb/kmb_dsi.c | 85 +++++++++++++++++++++++++++--------------
drivers/gpu/drm/kmb/kmb_plane.c | 15 ++++++--
5 files changed, 78 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index 01ad82e..9275f77 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -100,13 +100,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
struct videomode vm;
int vsync_start_offset;
int vsync_end_offset;
- unsigned int ctrl = 0;
#endif
/* initialize mipi */
kmb_dsi_hw_init(dev);
#ifdef LCD_TEST
- vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
- vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
+// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
+ vm.vfront_porch = 0;
+// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
+ vm.vback_porch = 0;
vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
//vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
vm.hfront_porch = 0;
@@ -149,12 +150,8 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, 10);
}
/* enable VL1 layer as default */
- ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE;
- ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
- | LCD_CTRL_OUTPUT_ENABLED;
- kmb_write_lcd(dev->dev_private, LCD_CONTROL, ctrl);
-
kmb_write_lcd(dev->dev_private, LCD_TIMING_GEN_TRIG, ENABLE);
+ kmb_set_bitmask_lcd(dev->dev_private, LCD_CONTROL, LCD_CTRL_ENABLE);
#endif
/* TBD */
/* set clocks here */
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index e9dd879..e2d57ca 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -236,6 +236,8 @@ static int kmb_load(struct drm_device *drm, unsigned long flags)
#endif
/* Set MIPI clock to 24 Mhz*/
DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi));
+//#define MIPI_CLK
+#ifdef MIPI_CLK
ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK);
DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi));
if (clk_get_rate(clk_mipi) != KMB_MIPI_DEFAULT_CLK) {
@@ -243,6 +245,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags)
KMB_MIPI_DEFAULT_CLK);
goto setup_fail;
}
+#endif
DRM_INFO("Setting MIPI clock to %d Mhz ret = %d\n",
KMB_MIPI_DEFAULT_CLK/1000000, ret);
DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi));
@@ -339,8 +342,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags)
DRM_ERROR("failed to initialize DSI\n");
goto setup_fail;
}
-
- DRM_INFO("%s : %d\n", __func__, __LINE__);
#ifdef WIP
ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
if (ret < 0) {
@@ -355,7 +356,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags)
drm_crtc_cleanup(&dev_p->crtc);
#endif
setup_fail:
- DRM_INFO("%s : %d\n", __func__, __LINE__);
of_reserved_mem_device_release(drm->dev);
return ret;
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index da1df5c..67ddf7a 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -28,7 +28,8 @@
#include "kmb_regs.h"
-/*#define FCCTEST*/
+#define FCCTEST
+#define LCD_TEST
#define KMB_MAX_WIDTH 1920 /*max width in pixels */
#define KMB_MAX_HEIGHT 1080 /*max height in pixels */
#define KMB_LCD_DEFAULT_CLK 250000000
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 5f7683e..91c6898 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -44,18 +44,19 @@
static int hw_initialized;
#define IMAGE_PATH "/home/root/1280x720.pnm"
-#define MIPI_TX_TEST_PATTERN_GENERATION
+//#define MIPI_TX_TEST_PATTERN_GENERATION
+//#define RTL_TEST
+//#define IMG_WIDTH_PX 640
+//#define IMG_HEIGHT_LINES 10
-#define IMG_HEIGHT_LINES 720
-#define IMG_WIDTH_PX 1280
#define LCD_BYTESPP 1
/*MIPI TX CFG*/
-#define MIPI_TX_ACTIVE_LANES 2
//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782
#define MIPI_TX_LANE_DATA_RATE_MBPS 891
//#define MIPI_TX_LANE_DATA_RATE_MBPS 80
#define MIPI_TX_REF_CLK_KHZ 24000
+//#define MIPI_TX_REF_CLK_KHZ 23809
#define MIPI_TX_CFG_CLK_KHZ 24000
/*DPHY Tx test codes*/
@@ -99,6 +100,18 @@ static struct mipi_dsi_device *dsi_device;
* these will eventually go to the device tree sections,
* and can be used as a refernce later for device tree additions
*/
+#ifdef RES_1920x1080
+#define IMG_HEIGHT_LINES 1080
+#define IMG_WIDTH_PX 1920
+#define MIPI_TX_ACTIVE_LANES 4
+#endif
+
+#define RES_1280x720
+#ifdef RES_1280x720
+#define IMG_HEIGHT_LINES 720
+#define IMG_WIDTH_PX 1280
+#define MIPI_TX_ACTIVE_LANES 2
+#endif
struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.width_pixels = IMG_WIDTH_PX,
.height_lines = IMG_HEIGHT_LINES,
@@ -108,6 +121,22 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.dma_packed = 1
};
+#ifdef RES_1920x1080
+struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
+ .sections[0] = &mipi_tx_frame0_sect_cfg,
+ .sections[1] = NULL,
+ .sections[2] = NULL,
+ .sections[3] = NULL,
+ .vsync_width = 5,
+ .v_backporch = 36,
+ .v_frontporch = 4,
+ .hsync_width = 44,
+ .h_backporch = 148,
+ .h_frontporch = 88
+};
+#endif
+
+#ifdef RES_1280x720
struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
.sections[0] = &mipi_tx_frame0_sect_cfg,
.sections[1] = NULL,
@@ -120,6 +149,7 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
.h_backporch = 220,
.h_frontporch = 110,
};
+#endif
struct mipi_tx_dsi_cfg mipitx_dsi_cfg = {
.hfp_blank_en = 0,
@@ -141,8 +171,7 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = {
.lane_rate_mbps = MIPI_TX_LANE_DATA_RATE_MBPS,
.ref_clk_khz = MIPI_TX_REF_CLK_KHZ,
.cfg_clk_khz = MIPI_TX_CFG_CLK_KHZ,
-// .data_if = MIPI_IF_PARALLEL,
- .data_if = MIPI_IF_DMA,
+ .data_if = MIPI_IF_PARALLEL,
.tx_ctrl_cfg = {
.frames[0] = &mipitx_frame0_cfg,
.frames[1] = NULL,
@@ -334,7 +363,6 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm,
struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev)
{
- struct device_node *encoder_node;
struct drm_bridge *bridge;
/* Create and register MIPI DSI host */
@@ -613,7 +641,13 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p,
ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) /
((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes);
- /*frame generator number of lines */
+ DRM_INFO("%s : %d bpp=%d sysclk=%d lane-rate=%d activ-lanes=%d\n",
+ __func__, __LINE__, fg_cfg->bpp, sysclk,
+ fg_cfg->lane_rate_mbps, fg_cfg->active_lanes);
+
+ DRM_INFO("%s : %d ppl_llp_ratio=%d\n", __func__, __LINE__,
+ ppl_llp_ratio);
+ /*frame generator number of lines*/
reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen);
kmb_write_mipi(dev_p, reg_adr, fg_cfg->v_active);
@@ -774,8 +808,8 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id,
if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop)
sync_cfg |= HACT_WAIT_STOP(fg_en);
- /* MIPI_TX_HS_CTRL */
- ctrl = HS_CTRL_EN; /* type:DSI,source:LCD */
+ /* MIPI_TX_HS_CTRL*/
+ ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */
if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en)
ctrl |= DSI_EOTP_EN;
if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en)
@@ -862,6 +896,7 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p,
active_vchannels++;
/*connect lcd to mipi */
+ kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1);
/*stop iterating as only one virtual channel shall be used for
* LCD connection
@@ -1528,7 +1563,7 @@ static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no,
kmb_read_mipi(dev_p, MIPI_DPHY_ERR_STAT6_7));
break;
}
- udelay(1);
+// udelay(1);
} while (stopstatedata != data_lanes);
DRM_INFO("********** DPHY %d INIT - %s **********\n",
@@ -1543,10 +1578,9 @@ static u32 wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no)
int status = 1;
do {
- ;
/*TODO-need to add a time out and return failure */
i++;
- udelay(1);
+ // udelay(1);
if (i > TIMEOUT) {
status = 0;
DRM_INFO("%s: timing out", __func__);
@@ -1603,7 +1637,7 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p,
cfg->active_lanes - MIPI_DPHY_D_LANES);
wait_pll_lock(dev_p, dphy_no);
wait_pll_lock(dev_p, dphy_no + 1);
- udelay(1000);
+// udelay(1000);
dphy_wait_fsm(dev_p, dphy_no, DPHY_TX_IDLE);
} else { /* Single DPHY */
dphy_init_sequence(dev_p, cfg, dphy_no, cfg->active_lanes,
@@ -1727,11 +1761,9 @@ int kmb_kernel_read(struct file *file, loff_t offset,
int kmb_dsi_hw_init(struct drm_device *dev)
{
struct kmb_drm_private *dev_p = dev->dev_private;
- int i;
if (hw_initialized)
return 0;
- udelay(1000);
kmb_write_mipi(dev_p, DPHY_ENABLE, 0);
kmb_write_mipi(dev_p, DPHY_INIT_CTRL0, 0);
kmb_write_mipi(dev_p, DPHY_INIT_CTRL1, 0);
@@ -1739,19 +1771,15 @@ int kmb_dsi_hw_init(struct drm_device *dev)
/* initialize mipi controller */
mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg);
- /* irq initialization */
- //mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg);
/*d-phy initialization */
mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg);
#ifdef MIPI_TX_TEST_PATTERN_GENERATION
- for (i = MIPI_CTRL6; i < MIPI_CTRL6 + 1; i++) {
- mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES,
- 0x05, 0xffffff, 0xff00, i);
- }
- DRM_INFO("%s : %d MIPI_TXm_HS_CTRL = 0x%x\n", __func__,
- __LINE__, kmb_read_mipi(dev_p, MIPI_TXm_HS_CTRL(6)));
-#else
- dma_data_length = image_height * image_width * unpacked_bytes;
+ mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, 0x15, 0xff,
+ 0xff00, MIPI_CTRL6);
+ DRM_INFO("%s : %d IRQ_STATUS = 0x%x\n", __func__, __LINE__,
+ GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6));
+#elseif MIPI_DMA
+ dma_data_length = image_height * image_width * unpacked_bytes;
file = filp_open(IMAGE_PATH, O_RDWR, 0);
if (IS_ERR(file)) {
DRM_ERROR("filp_open failed\n");
@@ -1785,7 +1813,6 @@ int kmb_dsi_hw_init(struct drm_device *dev)
DRM_INFO("count = %d\n", count);
kfree(file_buf);
filp_close(file, NULL);
-
#endif //MIPI_TX_TEST_PATTERN_GENERATION
hw_initialized = true;
@@ -1854,13 +1881,15 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge)
return ret;
}
#endif
+
#ifndef FCCTEST
DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__);
#endif
#ifdef FCCTEST
+#ifndef LCD_TEST
kmb_dsi_hw_init(dev);
#endif
-
+#endif
return 0;
}
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 2815ab3..008fd48 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -367,10 +367,14 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, layer_irqs[plane_id]);
/*TBD check visible? */
-
+/*
dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_AUTO_UPDATE
| LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1
| LCD_DMA_LAYER_VSTRIDE_EN;
+*/
+ dma_cfg = LCD_DMA_LAYER_ENABLE
+ | LCD_DMA_LAYER_AXI_BURST_1
+ | LCD_DMA_LAYER_VSTRIDE_EN;
/* disable DMA first */
kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id),
@@ -447,10 +451,12 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
break;
}
- ctrl |= LCD_CTRL_ENABLE;
- ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
- | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED;
+// ctrl |= LCD_CTRL_ENABLE;
+// ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
+// | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED;
+ ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
+ | LCD_CTRL_ONE_SHOT | LCD_CTRL_OUTPUT_ENABLED;
/*LCD is connected to MIPI on kmb
* Therefore this bit is required for DSI Tx
*/
@@ -474,6 +480,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
/* do not interleave RGB channels for mipi Tx compatibility */
out_format |= LCD_OUTF_MIPI_RGB_MODE;
kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format);
+// kmb_write_lcd(dev_p, LCD_CONTROL, LCD_CTRL_ENABLE);
#endif
}
--
2.7.4
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WARNING: multiple messages have this Message-ID (diff)
From: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com,
bob.j.paauwe@intel.com, edmund.j.dea@intel.com
Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 40/59] drm/kmb: Added LCD_TEST config
Date: Tue, 30 Jun 2020 14:27:52 -0700 [thread overview]
Message-ID: <1593552491-23698-41-git-send-email-anitha.chrisanthus@intel.com> (raw)
In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com>
To run modetest without ADV driver, enable LCD_TEST and FCC_TEST.
Also made front porches 0, and some changes in the plane init.
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
---
drivers/gpu/drm/kmb/kmb_crtc.c | 13 +++----
drivers/gpu/drm/kmb/kmb_drv.c | 6 +--
drivers/gpu/drm/kmb/kmb_drv.h | 3 +-
drivers/gpu/drm/kmb/kmb_dsi.c | 85 +++++++++++++++++++++++++++--------------
drivers/gpu/drm/kmb/kmb_plane.c | 15 ++++++--
5 files changed, 78 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index 01ad82e..9275f77 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -100,13 +100,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
struct videomode vm;
int vsync_start_offset;
int vsync_end_offset;
- unsigned int ctrl = 0;
#endif
/* initialize mipi */
kmb_dsi_hw_init(dev);
#ifdef LCD_TEST
- vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
- vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
+// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
+ vm.vfront_porch = 0;
+// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
+ vm.vback_porch = 0;
vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
//vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
vm.hfront_porch = 0;
@@ -149,12 +150,8 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, 10);
}
/* enable VL1 layer as default */
- ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE;
- ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
- | LCD_CTRL_OUTPUT_ENABLED;
- kmb_write_lcd(dev->dev_private, LCD_CONTROL, ctrl);
-
kmb_write_lcd(dev->dev_private, LCD_TIMING_GEN_TRIG, ENABLE);
+ kmb_set_bitmask_lcd(dev->dev_private, LCD_CONTROL, LCD_CTRL_ENABLE);
#endif
/* TBD */
/* set clocks here */
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index e9dd879..e2d57ca 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -236,6 +236,8 @@ static int kmb_load(struct drm_device *drm, unsigned long flags)
#endif
/* Set MIPI clock to 24 Mhz*/
DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi));
+//#define MIPI_CLK
+#ifdef MIPI_CLK
ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK);
DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi));
if (clk_get_rate(clk_mipi) != KMB_MIPI_DEFAULT_CLK) {
@@ -243,6 +245,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags)
KMB_MIPI_DEFAULT_CLK);
goto setup_fail;
}
+#endif
DRM_INFO("Setting MIPI clock to %d Mhz ret = %d\n",
KMB_MIPI_DEFAULT_CLK/1000000, ret);
DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi));
@@ -339,8 +342,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags)
DRM_ERROR("failed to initialize DSI\n");
goto setup_fail;
}
-
- DRM_INFO("%s : %d\n", __func__, __LINE__);
#ifdef WIP
ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
if (ret < 0) {
@@ -355,7 +356,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags)
drm_crtc_cleanup(&dev_p->crtc);
#endif
setup_fail:
- DRM_INFO("%s : %d\n", __func__, __LINE__);
of_reserved_mem_device_release(drm->dev);
return ret;
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index da1df5c..67ddf7a 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -28,7 +28,8 @@
#include "kmb_regs.h"
-/*#define FCCTEST*/
+#define FCCTEST
+#define LCD_TEST
#define KMB_MAX_WIDTH 1920 /*max width in pixels */
#define KMB_MAX_HEIGHT 1080 /*max height in pixels */
#define KMB_LCD_DEFAULT_CLK 250000000
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 5f7683e..91c6898 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -44,18 +44,19 @@
static int hw_initialized;
#define IMAGE_PATH "/home/root/1280x720.pnm"
-#define MIPI_TX_TEST_PATTERN_GENERATION
+//#define MIPI_TX_TEST_PATTERN_GENERATION
+//#define RTL_TEST
+//#define IMG_WIDTH_PX 640
+//#define IMG_HEIGHT_LINES 10
-#define IMG_HEIGHT_LINES 720
-#define IMG_WIDTH_PX 1280
#define LCD_BYTESPP 1
/*MIPI TX CFG*/
-#define MIPI_TX_ACTIVE_LANES 2
//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782
#define MIPI_TX_LANE_DATA_RATE_MBPS 891
//#define MIPI_TX_LANE_DATA_RATE_MBPS 80
#define MIPI_TX_REF_CLK_KHZ 24000
+//#define MIPI_TX_REF_CLK_KHZ 23809
#define MIPI_TX_CFG_CLK_KHZ 24000
/*DPHY Tx test codes*/
@@ -99,6 +100,18 @@ static struct mipi_dsi_device *dsi_device;
* these will eventually go to the device tree sections,
* and can be used as a refernce later for device tree additions
*/
+#ifdef RES_1920x1080
+#define IMG_HEIGHT_LINES 1080
+#define IMG_WIDTH_PX 1920
+#define MIPI_TX_ACTIVE_LANES 4
+#endif
+
+#define RES_1280x720
+#ifdef RES_1280x720
+#define IMG_HEIGHT_LINES 720
+#define IMG_WIDTH_PX 1280
+#define MIPI_TX_ACTIVE_LANES 2
+#endif
struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.width_pixels = IMG_WIDTH_PX,
.height_lines = IMG_HEIGHT_LINES,
@@ -108,6 +121,22 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.dma_packed = 1
};
+#ifdef RES_1920x1080
+struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
+ .sections[0] = &mipi_tx_frame0_sect_cfg,
+ .sections[1] = NULL,
+ .sections[2] = NULL,
+ .sections[3] = NULL,
+ .vsync_width = 5,
+ .v_backporch = 36,
+ .v_frontporch = 4,
+ .hsync_width = 44,
+ .h_backporch = 148,
+ .h_frontporch = 88
+};
+#endif
+
+#ifdef RES_1280x720
struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
.sections[0] = &mipi_tx_frame0_sect_cfg,
.sections[1] = NULL,
@@ -120,6 +149,7 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
.h_backporch = 220,
.h_frontporch = 110,
};
+#endif
struct mipi_tx_dsi_cfg mipitx_dsi_cfg = {
.hfp_blank_en = 0,
@@ -141,8 +171,7 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = {
.lane_rate_mbps = MIPI_TX_LANE_DATA_RATE_MBPS,
.ref_clk_khz = MIPI_TX_REF_CLK_KHZ,
.cfg_clk_khz = MIPI_TX_CFG_CLK_KHZ,
-// .data_if = MIPI_IF_PARALLEL,
- .data_if = MIPI_IF_DMA,
+ .data_if = MIPI_IF_PARALLEL,
.tx_ctrl_cfg = {
.frames[0] = &mipitx_frame0_cfg,
.frames[1] = NULL,
@@ -334,7 +363,6 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm,
struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev)
{
- struct device_node *encoder_node;
struct drm_bridge *bridge;
/* Create and register MIPI DSI host */
@@ -613,7 +641,13 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p,
ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) /
((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes);
- /*frame generator number of lines */
+ DRM_INFO("%s : %d bpp=%d sysclk=%d lane-rate=%d activ-lanes=%d\n",
+ __func__, __LINE__, fg_cfg->bpp, sysclk,
+ fg_cfg->lane_rate_mbps, fg_cfg->active_lanes);
+
+ DRM_INFO("%s : %d ppl_llp_ratio=%d\n", __func__, __LINE__,
+ ppl_llp_ratio);
+ /*frame generator number of lines*/
reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen);
kmb_write_mipi(dev_p, reg_adr, fg_cfg->v_active);
@@ -774,8 +808,8 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id,
if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop)
sync_cfg |= HACT_WAIT_STOP(fg_en);
- /* MIPI_TX_HS_CTRL */
- ctrl = HS_CTRL_EN; /* type:DSI,source:LCD */
+ /* MIPI_TX_HS_CTRL*/
+ ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */
if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en)
ctrl |= DSI_EOTP_EN;
if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en)
@@ -862,6 +896,7 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p,
active_vchannels++;
/*connect lcd to mipi */
+ kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1);
/*stop iterating as only one virtual channel shall be used for
* LCD connection
@@ -1528,7 +1563,7 @@ static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no,
kmb_read_mipi(dev_p, MIPI_DPHY_ERR_STAT6_7));
break;
}
- udelay(1);
+// udelay(1);
} while (stopstatedata != data_lanes);
DRM_INFO("********** DPHY %d INIT - %s **********\n",
@@ -1543,10 +1578,9 @@ static u32 wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no)
int status = 1;
do {
- ;
/*TODO-need to add a time out and return failure */
i++;
- udelay(1);
+ // udelay(1);
if (i > TIMEOUT) {
status = 0;
DRM_INFO("%s: timing out", __func__);
@@ -1603,7 +1637,7 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p,
cfg->active_lanes - MIPI_DPHY_D_LANES);
wait_pll_lock(dev_p, dphy_no);
wait_pll_lock(dev_p, dphy_no + 1);
- udelay(1000);
+// udelay(1000);
dphy_wait_fsm(dev_p, dphy_no, DPHY_TX_IDLE);
} else { /* Single DPHY */
dphy_init_sequence(dev_p, cfg, dphy_no, cfg->active_lanes,
@@ -1727,11 +1761,9 @@ int kmb_kernel_read(struct file *file, loff_t offset,
int kmb_dsi_hw_init(struct drm_device *dev)
{
struct kmb_drm_private *dev_p = dev->dev_private;
- int i;
if (hw_initialized)
return 0;
- udelay(1000);
kmb_write_mipi(dev_p, DPHY_ENABLE, 0);
kmb_write_mipi(dev_p, DPHY_INIT_CTRL0, 0);
kmb_write_mipi(dev_p, DPHY_INIT_CTRL1, 0);
@@ -1739,19 +1771,15 @@ int kmb_dsi_hw_init(struct drm_device *dev)
/* initialize mipi controller */
mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg);
- /* irq initialization */
- //mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg);
/*d-phy initialization */
mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg);
#ifdef MIPI_TX_TEST_PATTERN_GENERATION
- for (i = MIPI_CTRL6; i < MIPI_CTRL6 + 1; i++) {
- mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES,
- 0x05, 0xffffff, 0xff00, i);
- }
- DRM_INFO("%s : %d MIPI_TXm_HS_CTRL = 0x%x\n", __func__,
- __LINE__, kmb_read_mipi(dev_p, MIPI_TXm_HS_CTRL(6)));
-#else
- dma_data_length = image_height * image_width * unpacked_bytes;
+ mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, 0x15, 0xff,
+ 0xff00, MIPI_CTRL6);
+ DRM_INFO("%s : %d IRQ_STATUS = 0x%x\n", __func__, __LINE__,
+ GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6));
+#elseif MIPI_DMA
+ dma_data_length = image_height * image_width * unpacked_bytes;
file = filp_open(IMAGE_PATH, O_RDWR, 0);
if (IS_ERR(file)) {
DRM_ERROR("filp_open failed\n");
@@ -1785,7 +1813,6 @@ int kmb_dsi_hw_init(struct drm_device *dev)
DRM_INFO("count = %d\n", count);
kfree(file_buf);
filp_close(file, NULL);
-
#endif //MIPI_TX_TEST_PATTERN_GENERATION
hw_initialized = true;
@@ -1854,13 +1881,15 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge)
return ret;
}
#endif
+
#ifndef FCCTEST
DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__);
#endif
#ifdef FCCTEST
+#ifndef LCD_TEST
kmb_dsi_hw_init(dev);
#endif
-
+#endif
return 0;
}
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 2815ab3..008fd48 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -367,10 +367,14 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, layer_irqs[plane_id]);
/*TBD check visible? */
-
+/*
dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_AUTO_UPDATE
| LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1
| LCD_DMA_LAYER_VSTRIDE_EN;
+*/
+ dma_cfg = LCD_DMA_LAYER_ENABLE
+ | LCD_DMA_LAYER_AXI_BURST_1
+ | LCD_DMA_LAYER_VSTRIDE_EN;
/* disable DMA first */
kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id),
@@ -447,10 +451,12 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
break;
}
- ctrl |= LCD_CTRL_ENABLE;
- ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
- | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED;
+// ctrl |= LCD_CTRL_ENABLE;
+// ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
+// | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED;
+ ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
+ | LCD_CTRL_ONE_SHOT | LCD_CTRL_OUTPUT_ENABLED;
/*LCD is connected to MIPI on kmb
* Therefore this bit is required for DSI Tx
*/
@@ -474,6 +480,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
/* do not interleave RGB channels for mipi Tx compatibility */
out_format |= LCD_OUTF_MIPI_RGB_MODE;
kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format);
+// kmb_write_lcd(dev_p, LCD_CONTROL, LCD_CTRL_ENABLE);
#endif
}
--
2.7.4
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next prev parent reply other threads:[~2020-06-30 21:30 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-30 21:27 [PATCH 00/59] Add support for Keem Bay DRM driver Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 01/59] drm/kmb: Add support for KeemBay Display Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 02/59] drm/kmb: Added id to kmb_plane Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 03/59] drm/kmb: Set correct values in the LAYERn_CFG register Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 04/59] drm/kmb: Use biwise operators for register definitions Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 05/59] drm/kmb: Updated kmb_plane_atomic_check Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 06/59] drm/kmb: Initial check-in for Mipi DSI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 07/59] drm/kmb: Set OUT_FORMAT_CFG register Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 08/59] drm/kmb: Added mipi_dsi_host initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 09/59] drm/kmb: Part 1 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 10/59] drm/kmb: Part 2 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 11/59] drm/kmb: Use correct mmio offset from data book Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 12/59] drm/kmb: Part3 of Mipi Tx initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 13/59] drm/kmb: Part4 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 14/59] drm/kmb: Correct address offsets for mipi registers Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 15/59] drm/kmb: Part5 of Mipi Tx Intitialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 16/59] drm/kmb: Part6 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 17/59] drm/kmb: Part7 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 18/59] drm/kmb: Part8 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 19/59] drm/kmb: Added ioremap/iounmap for register access Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 20/59] drm/kmb: Register IRQ for LCD Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 21/59] drm/kmb: IRQ handlers for LCD and mipi dsi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 23/59] drm/kmb: Additional register programming to update_plane Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 24/59] drm/kmb: Add ADV7535 bridge Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 25/59] drm/kmb: Display clock enable/disable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 26/59] drm/kmb: rebase to newer kernel version Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 27/59] drm/kmb: minor name change to match device tree Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 28/59] drm/kmb: Changed MMIO size Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 29/59] drm/kmb: Defer Probe Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 30/59] drm/kmb: call bridge init in the very beginning Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 31/59] drm/kmb: Cleanup probe functions Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 32/59] drm/kmb: Revert dsi_host back to a static variable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 33/59] drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 35/59] drm/kmb: Remove declaration of irq_lcd/irq_mipi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 36/59] drm/kmb: Enable MIPI TX HS Test Pattern Generation Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 37/59] drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 38/59] drm/kmb: Mipi DPHY initialization changes Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 39/59] drm/kmb: Fixed driver unload Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` Anitha Chrisanthus [this message]
2020-06-30 21:27 ` [Intel-gfx] [PATCH 40/59] drm/kmb: Added LCD_TEST config Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 41/59] drm/kmb: Changes for LCD to Mipi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 42/59] drm/kmb: Update LCD programming to match MIPI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 43/59] drm/kmb: Changed name of driver to kmb-drm Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 44/59] drm/kmb: Mipi settings from input timings Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 45/59] drm/kmb: Enable LCD interrupts Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 46/59] drm/kmb: Enable LCD interrupts during modeset Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 47/59] drm/kmb: Don’t inadvertantly disable LCD controller Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 48/59] drm/kmb: SWAP R and B LCD Layer order Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 49/59] drm/kmb: Disable ping pong mode Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 50/59] drm/kmb: Do the layer initializations only once Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 51/59] drm/kmb: Write to LCD_LAYERn_CFG " Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 52/59] drm/kmb: Cleaned up code Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 53/59] drm/kmb: disable the LCD layer in EOF irq handler Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 54/59] drm/kmb: Initialize uninitialized variables Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 55/59] drm/kmb: Added useful messages in LCD ISR Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 56/59] kmb/drm: Prune unsupported modes Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 57/59] drm/kmb: workaround for dma undeflow issue Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 58/59] drm/kmb: Get System Clock from SCMI Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 59/59] drm/kmb: work around for planar formats Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 22:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for Keem Bay DRM driver Patchwork
2020-07-01 3:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-01 6:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-07-01 7:01 ` [PATCH 00/59] " Sam Ravnborg
2020-07-01 7:01 ` [Intel-gfx] " Sam Ravnborg
2020-07-01 21:53 ` Chrisanthus, Anitha
2020-07-01 21:53 ` [Intel-gfx] " Chrisanthus, Anitha
2020-07-02 10:19 ` Neil Armstrong
2020-07-02 10:19 ` [Intel-gfx] " Neil Armstrong
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