From: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com,
bob.j.paauwe@intel.com, edmund.j.dea@intel.com
Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org,
rodrigo.vivi@intel.com
Subject: [PATCH 44/59] drm/kmb: Mipi settings from input timings
Date: Tue, 30 Jun 2020 14:27:56 -0700 [thread overview]
Message-ID: <1593552491-23698-45-git-send-email-anitha.chrisanthus@intel.com> (raw)
In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com>
Removed hardcoded timings, set timings based on the current mode's
input timings. Also calculate and set the lane rate based on the
timings.
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
---
drivers/gpu/drm/kmb/kmb_crtc.c | 9 +++-
drivers/gpu/drm/kmb/kmb_dsi.c | 93 +++++++++++++++++++++++-------------------
drivers/gpu/drm/kmb/kmb_dsi.h | 2 +-
3 files changed, 61 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index d9f6199..75e78d7 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -102,7 +102,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
int vsync_end_offset;
#endif
/* initialize mipi */
- kmb_dsi_hw_init(dev);
+ kmb_dsi_hw_init(dev, m);
+ DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n",
+ m->crtc_vsync_start - m->crtc_vdisplay,
+ m->crtc_vtotal - m->crtc_vsync_end,
+ m->crtc_vsync_end - m->crtc_vsync_start,
+ m->crtc_hsync_start - m->crtc_hdisplay,
+ m->crtc_htotal - m->crtc_hsync_end,
+ m->crtc_hsync_end - m->crtc_hsync_start);
#ifdef LCD_TEST
// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
vm.vfront_porch = 2;
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 3b3bb0a..3368e97 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -47,19 +47,12 @@ static int hw_initialized;
//#define MIPI_TX_TEST_PATTERN_GENERATION
//#define MIPI_DMA
//#define RTL_TEST
-//#define IMG_WIDTH_PX 640
-//#define IMG_HEIGHT_LINES 10
-
-#define LCD_BYTESPP 1
/*MIPI TX CFG*/
-//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782
-//#define MIPI_TX_LANE_DATA_RATE_MBPS 800
#define MIPI_TX_LANE_DATA_RATE_MBPS 891
-//#define MIPI_TX_LANE_DATA_RATE_MBPS 80
#define MIPI_TX_REF_CLK_KHZ 24000
-//#define MIPI_TX_REF_CLK_KHZ 23809
#define MIPI_TX_CFG_CLK_KHZ 24000
+#define MIPI_TX_BPP 24
/*DPHY Tx test codes*/
#define TEST_CODE_FSM_CONTROL 0x03
@@ -98,23 +91,12 @@ static struct mipi_dsi_host *dsi_host;
static struct mipi_dsi_device *dsi_device;
/*
- * These are added here only temporarily for testing,
- * these will eventually go to the device tree sections,
- * and can be used as a refernce later for device tree additions
+ * Default setting is 1080p, 4 lanes.
*/
-#define RES_1920x1080
-#ifdef RES_1920x1080
#define IMG_HEIGHT_LINES 1080
#define IMG_WIDTH_PX 1920
#define MIPI_TX_ACTIVE_LANES 4
-#endif
-//#define RES_1280x720
-#ifdef RES_1280x720
-#define IMG_HEIGHT_LINES 720
-#define IMG_WIDTH_PX 1280
-#define MIPI_TX_ACTIVE_LANES 2
-#endif
struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.width_pixels = IMG_WIDTH_PX,
.height_lines = IMG_HEIGHT_LINES,
@@ -124,7 +106,6 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.dma_packed = 0
};
-#ifdef RES_1920x1080
struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
.sections[0] = &mipi_tx_frame0_sect_cfg,
.sections[1] = NULL,
@@ -137,22 +118,6 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
.h_backporch = 148,
.h_frontporch = 88
};
-#endif
-
-#ifdef RES_1280x720
-struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
- .sections[0] = &mipi_tx_frame0_sect_cfg,
- .sections[1] = NULL,
- .sections[2] = NULL,
- .sections[3] = NULL,
- .vsync_width = 5,
- .v_backporch = 20,
- .v_frontporch = 5,
- .hsync_width = 40,
- .h_backporch = 220,
- .h_frontporch = 110,
-};
-#endif
struct mipi_tx_dsi_cfg mipitx_dsi_cfg = {
.hfp_blank_en = 0,
@@ -1740,10 +1705,58 @@ int kmb_kernel_read(struct file *file, loff_t offset,
return ret;
}
-int kmb_dsi_hw_init(struct drm_device *dev)
+int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode)
{
struct kmb_drm_private *dev_p = dev->dev_private;
+ u64 data_rate;
+
+ mipi_tx_init_cfg.active_lanes = MIPI_TX_ACTIVE_LANES;
+ if (mode != NULL) {
+ mipi_tx_frame0_sect_cfg.width_pixels = mode->crtc_hdisplay;
+ mipi_tx_frame0_sect_cfg.height_lines = mode->crtc_vdisplay;
+ mipitx_frame0_cfg.vsync_width =
+ mode->crtc_vsync_end - mode->crtc_vsync_start;
+ mipitx_frame0_cfg.v_backporch =
+ mode->crtc_vtotal - mode->crtc_vsync_end;
+ mipitx_frame0_cfg.v_frontporch =
+ mode->crtc_vsync_start - mode->crtc_vdisplay;
+ mipitx_frame0_cfg.hsync_width =
+ mode->crtc_hsync_end - mode->crtc_hsync_start;
+ mipitx_frame0_cfg.h_backporch =
+ mode->crtc_htotal - mode->crtc_hsync_end;
+ mipitx_frame0_cfg.h_frontporch =
+ mode->crtc_hsync_start - mode->crtc_hdisplay;
+ /*lane rate = (vtotal*htotal*fps*bpp)/4 / 1000000
+ * to convert to Mbps
+ */
+ DRM_INFO("htotal = %d vtotal=%d refresh=%d\n",
+ mode->crtc_htotal, mode->crtc_vtotal,
+ drm_mode_vrefresh(mode));
+ data_rate =
+ ((((u32)mode->crtc_vtotal * (u32)mode->crtc_htotal)
+ * (u32)(drm_mode_vrefresh(mode))
+ * MIPI_TX_BPP)/mipi_tx_init_cfg.active_lanes) / 1000000;
+ DRM_INFO("data_rate = %llu active_lanes=%d\n",
+ data_rate, mipi_tx_init_cfg.active_lanes);
+
+ /*when late rate < 800 - modeset fails with 4 lanes -
+ * so switch to 2 lanes
+ */
+ if (data_rate < 800) {
+ mipi_tx_init_cfg.active_lanes = 2;
+ mipi_tx_init_cfg.lane_rate_mbps = data_rate * 2;
+ } else {
+ mipi_tx_init_cfg.lane_rate_mbps = data_rate;
+ }
+ DRM_INFO("lane rate=%d\n", mipi_tx_init_cfg.lane_rate_mbps);
+ DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d lane-rate=%d\n",
+ mipitx_frame0_cfg.v_frontporch, mipitx_frame0_cfg.v_backporch,
+ mipitx_frame0_cfg.vsync_width,
+ mipitx_frame0_cfg.h_frontporch, mipitx_frame0_cfg.h_backporch,
+ mipitx_frame0_cfg.hsync_width,
+ mipi_tx_init_cfg.lane_rate_mbps);
+ }
if (hw_initialized)
return 0;
kmb_write_mipi(dev_p, DPHY_ENABLE, 0);
@@ -1826,15 +1839,13 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge)
drm_encoder_cleanup(encoder);
return ret;
}
-#endif
-#ifndef FCCTEST
DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__);
#endif
#ifdef FCCTEST
#ifndef LCD_TEST
- kmb_dsi_hw_init(dev);
+ kmb_dsi_hw_init(dev, NULL);
#endif
#endif
return 0;
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h
index ece4ee1..1d4ca8d 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.h
+++ b/drivers/gpu/drm/kmb/kmb_dsi.h
@@ -341,7 +341,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge);
void kmb_plane_destroy(struct drm_plane *plane);
void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p);
void kmb_dsi_host_unregister(void);
-int kmb_dsi_hw_init(struct drm_device *dev);
+int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode);
#define to_kmb_connector(x) container_of(x, struct kmb_connector, base)
#define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base)
--
2.7.4
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WARNING: multiple messages have this Message-ID (diff)
From: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com,
bob.j.paauwe@intel.com, edmund.j.dea@intel.com
Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 44/59] drm/kmb: Mipi settings from input timings
Date: Tue, 30 Jun 2020 14:27:56 -0700 [thread overview]
Message-ID: <1593552491-23698-45-git-send-email-anitha.chrisanthus@intel.com> (raw)
In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com>
Removed hardcoded timings, set timings based on the current mode's
input timings. Also calculate and set the lane rate based on the
timings.
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
---
drivers/gpu/drm/kmb/kmb_crtc.c | 9 +++-
drivers/gpu/drm/kmb/kmb_dsi.c | 93 +++++++++++++++++++++++-------------------
drivers/gpu/drm/kmb/kmb_dsi.h | 2 +-
3 files changed, 61 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index d9f6199..75e78d7 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -102,7 +102,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
int vsync_end_offset;
#endif
/* initialize mipi */
- kmb_dsi_hw_init(dev);
+ kmb_dsi_hw_init(dev, m);
+ DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n",
+ m->crtc_vsync_start - m->crtc_vdisplay,
+ m->crtc_vtotal - m->crtc_vsync_end,
+ m->crtc_vsync_end - m->crtc_vsync_start,
+ m->crtc_hsync_start - m->crtc_hdisplay,
+ m->crtc_htotal - m->crtc_hsync_end,
+ m->crtc_hsync_end - m->crtc_hsync_start);
#ifdef LCD_TEST
// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
vm.vfront_porch = 2;
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 3b3bb0a..3368e97 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -47,19 +47,12 @@ static int hw_initialized;
//#define MIPI_TX_TEST_PATTERN_GENERATION
//#define MIPI_DMA
//#define RTL_TEST
-//#define IMG_WIDTH_PX 640
-//#define IMG_HEIGHT_LINES 10
-
-#define LCD_BYTESPP 1
/*MIPI TX CFG*/
-//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782
-//#define MIPI_TX_LANE_DATA_RATE_MBPS 800
#define MIPI_TX_LANE_DATA_RATE_MBPS 891
-//#define MIPI_TX_LANE_DATA_RATE_MBPS 80
#define MIPI_TX_REF_CLK_KHZ 24000
-//#define MIPI_TX_REF_CLK_KHZ 23809
#define MIPI_TX_CFG_CLK_KHZ 24000
+#define MIPI_TX_BPP 24
/*DPHY Tx test codes*/
#define TEST_CODE_FSM_CONTROL 0x03
@@ -98,23 +91,12 @@ static struct mipi_dsi_host *dsi_host;
static struct mipi_dsi_device *dsi_device;
/*
- * These are added here only temporarily for testing,
- * these will eventually go to the device tree sections,
- * and can be used as a refernce later for device tree additions
+ * Default setting is 1080p, 4 lanes.
*/
-#define RES_1920x1080
-#ifdef RES_1920x1080
#define IMG_HEIGHT_LINES 1080
#define IMG_WIDTH_PX 1920
#define MIPI_TX_ACTIVE_LANES 4
-#endif
-//#define RES_1280x720
-#ifdef RES_1280x720
-#define IMG_HEIGHT_LINES 720
-#define IMG_WIDTH_PX 1280
-#define MIPI_TX_ACTIVE_LANES 2
-#endif
struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.width_pixels = IMG_WIDTH_PX,
.height_lines = IMG_HEIGHT_LINES,
@@ -124,7 +106,6 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.dma_packed = 0
};
-#ifdef RES_1920x1080
struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
.sections[0] = &mipi_tx_frame0_sect_cfg,
.sections[1] = NULL,
@@ -137,22 +118,6 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
.h_backporch = 148,
.h_frontporch = 88
};
-#endif
-
-#ifdef RES_1280x720
-struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
- .sections[0] = &mipi_tx_frame0_sect_cfg,
- .sections[1] = NULL,
- .sections[2] = NULL,
- .sections[3] = NULL,
- .vsync_width = 5,
- .v_backporch = 20,
- .v_frontporch = 5,
- .hsync_width = 40,
- .h_backporch = 220,
- .h_frontporch = 110,
-};
-#endif
struct mipi_tx_dsi_cfg mipitx_dsi_cfg = {
.hfp_blank_en = 0,
@@ -1740,10 +1705,58 @@ int kmb_kernel_read(struct file *file, loff_t offset,
return ret;
}
-int kmb_dsi_hw_init(struct drm_device *dev)
+int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode)
{
struct kmb_drm_private *dev_p = dev->dev_private;
+ u64 data_rate;
+
+ mipi_tx_init_cfg.active_lanes = MIPI_TX_ACTIVE_LANES;
+ if (mode != NULL) {
+ mipi_tx_frame0_sect_cfg.width_pixels = mode->crtc_hdisplay;
+ mipi_tx_frame0_sect_cfg.height_lines = mode->crtc_vdisplay;
+ mipitx_frame0_cfg.vsync_width =
+ mode->crtc_vsync_end - mode->crtc_vsync_start;
+ mipitx_frame0_cfg.v_backporch =
+ mode->crtc_vtotal - mode->crtc_vsync_end;
+ mipitx_frame0_cfg.v_frontporch =
+ mode->crtc_vsync_start - mode->crtc_vdisplay;
+ mipitx_frame0_cfg.hsync_width =
+ mode->crtc_hsync_end - mode->crtc_hsync_start;
+ mipitx_frame0_cfg.h_backporch =
+ mode->crtc_htotal - mode->crtc_hsync_end;
+ mipitx_frame0_cfg.h_frontporch =
+ mode->crtc_hsync_start - mode->crtc_hdisplay;
+ /*lane rate = (vtotal*htotal*fps*bpp)/4 / 1000000
+ * to convert to Mbps
+ */
+ DRM_INFO("htotal = %d vtotal=%d refresh=%d\n",
+ mode->crtc_htotal, mode->crtc_vtotal,
+ drm_mode_vrefresh(mode));
+ data_rate =
+ ((((u32)mode->crtc_vtotal * (u32)mode->crtc_htotal)
+ * (u32)(drm_mode_vrefresh(mode))
+ * MIPI_TX_BPP)/mipi_tx_init_cfg.active_lanes) / 1000000;
+ DRM_INFO("data_rate = %llu active_lanes=%d\n",
+ data_rate, mipi_tx_init_cfg.active_lanes);
+
+ /*when late rate < 800 - modeset fails with 4 lanes -
+ * so switch to 2 lanes
+ */
+ if (data_rate < 800) {
+ mipi_tx_init_cfg.active_lanes = 2;
+ mipi_tx_init_cfg.lane_rate_mbps = data_rate * 2;
+ } else {
+ mipi_tx_init_cfg.lane_rate_mbps = data_rate;
+ }
+ DRM_INFO("lane rate=%d\n", mipi_tx_init_cfg.lane_rate_mbps);
+ DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d lane-rate=%d\n",
+ mipitx_frame0_cfg.v_frontporch, mipitx_frame0_cfg.v_backporch,
+ mipitx_frame0_cfg.vsync_width,
+ mipitx_frame0_cfg.h_frontporch, mipitx_frame0_cfg.h_backporch,
+ mipitx_frame0_cfg.hsync_width,
+ mipi_tx_init_cfg.lane_rate_mbps);
+ }
if (hw_initialized)
return 0;
kmb_write_mipi(dev_p, DPHY_ENABLE, 0);
@@ -1826,15 +1839,13 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge)
drm_encoder_cleanup(encoder);
return ret;
}
-#endif
-#ifndef FCCTEST
DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__);
#endif
#ifdef FCCTEST
#ifndef LCD_TEST
- kmb_dsi_hw_init(dev);
+ kmb_dsi_hw_init(dev, NULL);
#endif
#endif
return 0;
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h
index ece4ee1..1d4ca8d 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.h
+++ b/drivers/gpu/drm/kmb/kmb_dsi.h
@@ -341,7 +341,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge);
void kmb_plane_destroy(struct drm_plane *plane);
void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p);
void kmb_dsi_host_unregister(void);
-int kmb_dsi_hw_init(struct drm_device *dev);
+int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode);
#define to_kmb_connector(x) container_of(x, struct kmb_connector, base)
#define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base)
--
2.7.4
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next prev parent reply other threads:[~2020-06-30 21:30 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-30 21:27 [PATCH 00/59] Add support for Keem Bay DRM driver Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 01/59] drm/kmb: Add support for KeemBay Display Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 02/59] drm/kmb: Added id to kmb_plane Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 03/59] drm/kmb: Set correct values in the LAYERn_CFG register Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 04/59] drm/kmb: Use biwise operators for register definitions Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 05/59] drm/kmb: Updated kmb_plane_atomic_check Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 06/59] drm/kmb: Initial check-in for Mipi DSI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 07/59] drm/kmb: Set OUT_FORMAT_CFG register Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 08/59] drm/kmb: Added mipi_dsi_host initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 09/59] drm/kmb: Part 1 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 10/59] drm/kmb: Part 2 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 11/59] drm/kmb: Use correct mmio offset from data book Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 12/59] drm/kmb: Part3 of Mipi Tx initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 13/59] drm/kmb: Part4 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 14/59] drm/kmb: Correct address offsets for mipi registers Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 15/59] drm/kmb: Part5 of Mipi Tx Intitialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 16/59] drm/kmb: Part6 of Mipi Tx Initialization Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 17/59] drm/kmb: Part7 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 18/59] drm/kmb: Part8 " Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 19/59] drm/kmb: Added ioremap/iounmap for register access Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 20/59] drm/kmb: Register IRQ for LCD Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 21/59] drm/kmb: IRQ handlers for LCD and mipi dsi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 23/59] drm/kmb: Additional register programming to update_plane Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 24/59] drm/kmb: Add ADV7535 bridge Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 25/59] drm/kmb: Display clock enable/disable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 26/59] drm/kmb: rebase to newer kernel version Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 27/59] drm/kmb: minor name change to match device tree Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 28/59] drm/kmb: Changed MMIO size Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 29/59] drm/kmb: Defer Probe Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 30/59] drm/kmb: call bridge init in the very beginning Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 31/59] drm/kmb: Cleanup probe functions Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 32/59] drm/kmb: Revert dsi_host back to a static variable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 33/59] drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 35/59] drm/kmb: Remove declaration of irq_lcd/irq_mipi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 36/59] drm/kmb: Enable MIPI TX HS Test Pattern Generation Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 37/59] drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 38/59] drm/kmb: Mipi DPHY initialization changes Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 39/59] drm/kmb: Fixed driver unload Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 40/59] drm/kmb: Added LCD_TEST config Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 41/59] drm/kmb: Changes for LCD to Mipi Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 42/59] drm/kmb: Update LCD programming to match MIPI Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 43/59] drm/kmb: Changed name of driver to kmb-drm Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` Anitha Chrisanthus [this message]
2020-06-30 21:27 ` [Intel-gfx] [PATCH 44/59] drm/kmb: Mipi settings from input timings Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 45/59] drm/kmb: Enable LCD interrupts Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 46/59] drm/kmb: Enable LCD interrupts during modeset Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:27 ` [PATCH 47/59] drm/kmb: Don’t inadvertantly disable LCD controller Anitha Chrisanthus
2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 48/59] drm/kmb: SWAP R and B LCD Layer order Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 49/59] drm/kmb: Disable ping pong mode Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 50/59] drm/kmb: Do the layer initializations only once Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 51/59] drm/kmb: Write to LCD_LAYERn_CFG " Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 52/59] drm/kmb: Cleaned up code Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 53/59] drm/kmb: disable the LCD layer in EOF irq handler Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 54/59] drm/kmb: Initialize uninitialized variables Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 55/59] drm/kmb: Added useful messages in LCD ISR Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 56/59] kmb/drm: Prune unsupported modes Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 57/59] drm/kmb: workaround for dma undeflow issue Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 58/59] drm/kmb: Get System Clock from SCMI Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 21:28 ` [PATCH 59/59] drm/kmb: work around for planar formats Anitha Chrisanthus
2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus
2020-06-30 22:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for Keem Bay DRM driver Patchwork
2020-07-01 3:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-01 6:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-07-01 7:01 ` [PATCH 00/59] " Sam Ravnborg
2020-07-01 7:01 ` [Intel-gfx] " Sam Ravnborg
2020-07-01 21:53 ` Chrisanthus, Anitha
2020-07-01 21:53 ` [Intel-gfx] " Chrisanthus, Anitha
2020-07-02 10:19 ` Neil Armstrong
2020-07-02 10:19 ` [Intel-gfx] " Neil Armstrong
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