From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Subject: [PATCH 18/27] drm/i915/gt: Expose reset stop timeout via sysfs Date: Tue, 12 Nov 2019 09:28:45 +0000 [thread overview] Message-ID: <20191112092854.869-18-chris@chris-wilson.co.uk> (raw) In-Reply-To: <20191112092854.869-1-chris@chris-wilson.co.uk> When we allow ourselves to sleep before a GPU reset after disabling submission, even for a few milliseconds, gives an innocent context the opportunity to clear the GPU before the reset occurs. However, how long to sleep depends on the typical non-preemptible duration (a similar problem to determining the ideal preempt-reset timeout or even the heartbeat interval). As this seems of a hard policy decision, punt it to userspace. The timeout can be adjusted using /sys/class/drm/card?/engine/*/stop_timeout_ms Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> --- drivers/gpu/drm/i915/Kconfig.profile | 3 ++ drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 40 ++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/i915/Kconfig.profile b/drivers/gpu/drm/i915/Kconfig.profile index b9060b023c51..d0fece34933b 100644 --- a/drivers/gpu/drm/i915/Kconfig.profile +++ b/drivers/gpu/drm/i915/Kconfig.profile @@ -63,6 +63,9 @@ config DRM_I915_STOP_TIMEOUT that the reset itself may take longer and so be more disruptive to interactive or low latency workloads. + This is adjustable via + /sys/class/drm/card?/engine/*/stop_timeout_ms + config DRM_I915_TIMESLICE_DURATION int "Scheduling quantum for userspace batches (ms, jiffy granularity)" default 1 # milliseconds diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c index 6d87529c64a7..2b65fed76435 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c @@ -232,6 +232,45 @@ timeslice_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) static struct kobj_attribute timeslice_duration_attr = __ATTR(timeslice_duration_ms, 0644, timeslice_show, timeslice_store); +static ssize_t +stop_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + struct intel_engine_cs *engine = kobj_to_engine(kobj); + unsigned long long duration; + int err; + + /* + * When we allow ourselves to sleep before a GPU reset after disabling + * submission, even for a few milliseconds, gives an innocent context + * the opportunity to clear the GPU before the reset occurs. However, + * how long to sleep depends on the typical non-preemptible duration + * (a similar problem to determining the ideal preempt-reset timeout + * or even the heartbeat interval). + */ + + err = kstrtoull(buf, 0, &duration); + if (err) + return err; + + if (duration > jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT)) + return -EINVAL; + + WRITE_ONCE(engine->props.stop_timeout_ms, duration); + return count; +} + +static ssize_t +stop_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct intel_engine_cs *engine = kobj_to_engine(kobj); + + return sprintf(buf, "%lu\n", engine->props.stop_timeout_ms); +} + +static struct kobj_attribute stop_timeout_attr = +__ATTR(stop_timeout_ms, 0644, stop_show, stop_store); + static void kobj_engine_release(struct kobject *kobj) { kfree(kobj); @@ -273,6 +312,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) &caps_attr.attr, &all_caps_attr.attr, &max_spin_attr.attr, + &stop_timeout_attr.attr, NULL }; -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 18/27] drm/i915/gt: Expose reset stop timeout via sysfs Date: Tue, 12 Nov 2019 09:28:45 +0000 [thread overview] Message-ID: <20191112092854.869-18-chris@chris-wilson.co.uk> (raw) Message-ID: <20191112092845.T2Lmcz4ZgQB9Xj0WLemkOlsP63wuWM91boHH7tJTAJU@z> (raw) In-Reply-To: <20191112092854.869-1-chris@chris-wilson.co.uk> When we allow ourselves to sleep before a GPU reset after disabling submission, even for a few milliseconds, gives an innocent context the opportunity to clear the GPU before the reset occurs. However, how long to sleep depends on the typical non-preemptible duration (a similar problem to determining the ideal preempt-reset timeout or even the heartbeat interval). As this seems of a hard policy decision, punt it to userspace. The timeout can be adjusted using /sys/class/drm/card?/engine/*/stop_timeout_ms Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> --- drivers/gpu/drm/i915/Kconfig.profile | 3 ++ drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 40 ++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/i915/Kconfig.profile b/drivers/gpu/drm/i915/Kconfig.profile index b9060b023c51..d0fece34933b 100644 --- a/drivers/gpu/drm/i915/Kconfig.profile +++ b/drivers/gpu/drm/i915/Kconfig.profile @@ -63,6 +63,9 @@ config DRM_I915_STOP_TIMEOUT that the reset itself may take longer and so be more disruptive to interactive or low latency workloads. + This is adjustable via + /sys/class/drm/card?/engine/*/stop_timeout_ms + config DRM_I915_TIMESLICE_DURATION int "Scheduling quantum for userspace batches (ms, jiffy granularity)" default 1 # milliseconds diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c index 6d87529c64a7..2b65fed76435 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c @@ -232,6 +232,45 @@ timeslice_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) static struct kobj_attribute timeslice_duration_attr = __ATTR(timeslice_duration_ms, 0644, timeslice_show, timeslice_store); +static ssize_t +stop_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + struct intel_engine_cs *engine = kobj_to_engine(kobj); + unsigned long long duration; + int err; + + /* + * When we allow ourselves to sleep before a GPU reset after disabling + * submission, even for a few milliseconds, gives an innocent context + * the opportunity to clear the GPU before the reset occurs. However, + * how long to sleep depends on the typical non-preemptible duration + * (a similar problem to determining the ideal preempt-reset timeout + * or even the heartbeat interval). + */ + + err = kstrtoull(buf, 0, &duration); + if (err) + return err; + + if (duration > jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT)) + return -EINVAL; + + WRITE_ONCE(engine->props.stop_timeout_ms, duration); + return count; +} + +static ssize_t +stop_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct intel_engine_cs *engine = kobj_to_engine(kobj); + + return sprintf(buf, "%lu\n", engine->props.stop_timeout_ms); +} + +static struct kobj_attribute stop_timeout_attr = +__ATTR(stop_timeout_ms, 0644, stop_show, stop_store); + static void kobj_engine_release(struct kobject *kobj) { kfree(kobj); @@ -273,6 +312,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) &caps_attr.attr, &all_caps_attr.attr, &max_spin_attr.attr, + &stop_timeout_attr.attr, NULL }; -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-12 9:29 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-12 9:28 [PATCH 01/27] drm/i915: Flush context free work on cleanup Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 02/27] drm/i915/gt: Try an extra flush on the Haswell blitter Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 03/27] drm/i915/gem: Silence sparse for RCU protection inside the constructor Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 04/27] drm/i915/selftests: Mock the engine sorting for easy validation Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 05/27] Revert "drm/i915: use a separate context for gpu relocs" Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 06/27] drm/i915: Use a ctor for TYPESAFE_BY_RCU i915_request Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 07/27] drm/i915: Drop GEM context as a direct link from i915_request Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 08/27] drm/i915: Push the use-semaphore marker onto the intel_context Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 09/27] drm/i915: Remove i915->kernel_context Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 10/27] drm/i915: Move i915_gem_init_contexts() earlier Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 11/27] drm/i915/uc: Use an internal buffer for firmware images Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 12/27] drm/i915/gt: Pull GT initialisation under intel_gt_init() Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 13/27] drm/i915/gt: Merge engine init/setup loops Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 14/27] drm/i915/gt: Expose engine properties via sysfs Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 15/27] drm/i915/gt: Expose engine->mmio_base " Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-21 13:18 ` Lionel Landwerlin 2019-11-21 13:18 ` [Intel-gfx] " Lionel Landwerlin 2019-11-21 13:23 ` Chris Wilson 2019-11-21 13:23 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 16/27] drm/i915/gt: Expose timeslice duration to sysfs Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 17/27] drm/i915/gt: Expose busywait " Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` Chris Wilson [this message] 2019-11-12 9:28 ` [Intel-gfx] [PATCH 18/27] drm/i915/gt: Expose reset stop timeout via sysfs Chris Wilson 2019-11-12 9:28 ` [PATCH 19/27] drm/i915/gt: Expose preempt reset " Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 20/27] drm/i915/gt: Expose heartbeat interval " Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 21/27] drm/i915: Flush idle barriers when waiting Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 22/27] drm/i915: Allow userspace to specify ringsize on construction Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 23/27] drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 24/27] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 14:13 ` Mika Kuoppala 2019-11-12 14:13 ` [Intel-gfx] " Mika Kuoppala 2019-11-12 14:39 ` Chris Wilson 2019-11-12 14:39 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 25/27] drm/i915/gt: Tidy up debug-warns for the mocs control table Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 26/27] drm/i915/gt: Refactor mocs loops into single control macro Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 17:02 ` Mika Kuoppala 2019-11-12 17:02 ` [Intel-gfx] " Mika Kuoppala 2019-11-12 18:12 ` Chris Wilson 2019-11-12 18:12 ` [Intel-gfx] " Chris Wilson 2019-11-12 9:28 ` [PATCH 27/27] drm/i915/selftests: Add coverage of mocs registers Chris Wilson 2019-11-12 9:28 ` [Intel-gfx] " Chris Wilson 2019-11-12 10:12 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/27] drm/i915: Flush context free work on cleanup Patchwork 2019-11-12 10:12 ` [Intel-gfx] " Patchwork 2019-11-12 10:23 ` ✗ Fi.CI.SPARSE: " Patchwork 2019-11-12 10:23 ` [Intel-gfx] " Patchwork 2019-11-12 10:33 ` ✗ Fi.CI.BAT: failure " Patchwork 2019-11-12 10:33 ` [Intel-gfx] " Patchwork 2019-11-12 14:23 ` [PATCH 01/27] " Mika Kuoppala 2019-11-12 14:23 ` [Intel-gfx] " Mika Kuoppala 2019-11-12 14:39 ` Chris Wilson 2019-11-12 14:39 ` [Intel-gfx] " Chris Wilson
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