From: Bjorn Helgaas <helgaas@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: "Naveen Naidu" <naveennaidu479@gmail.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
PCI <linux-pci@vger.kernel.org>,
linux-kernel-mentees@lists.linuxfoundation.org,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Pali Rohár" <pali@kernel.org>
Subject: Re: [PATCH 02/22] PCI: Unify PCI error response checking
Date: Wed, 13 Oct 2021 17:12:53 -0500 [thread overview]
Message-ID: <20211013221253.GA1928518@bhelgaas> (raw)
In-Reply-To: <CAL_JsqL0d4qOR+wsnpdRUc+EQ6_diUzPbMj3Tv-Ly29or6Asvw@mail.gmail.com>
On Wed, Oct 13, 2021 at 04:47:43PM -0500, Rob Herring wrote:
> Presumably, there could be some register somewhere where all 1s is
> valid? So I think we need the error values.
We have to assume ~0 is a valid value for any config registers except
the few defined by the spec that have bits required to be 0. There
can be all kinds of vendor-defined stuff in config space that can be
anything.
> Also, I seem to recall only the vendor/device IDs are defined to be
> all 1s for non-existent devices. Other errors are undefined?
I think this case is actually an instance of the PCI controller
fabricating ~0 because a PCI/PCIe error occurred (I think on PCI it's
a Master Abort when nothing responds; on PCIe the read terminates as
an Unsupported Request (PCIe r5.0, sec 2.3.2)).
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: linux-kernel-mentees@lists.linuxfoundation.org,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
PCI <linux-pci@vger.kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Pali Rohár" <pali@kernel.org>
Subject: Re: [PATCH 02/22] PCI: Unify PCI error response checking
Date: Wed, 13 Oct 2021 17:12:53 -0500 [thread overview]
Message-ID: <20211013221253.GA1928518@bhelgaas> (raw)
In-Reply-To: <CAL_JsqL0d4qOR+wsnpdRUc+EQ6_diUzPbMj3Tv-Ly29or6Asvw@mail.gmail.com>
On Wed, Oct 13, 2021 at 04:47:43PM -0500, Rob Herring wrote:
> Presumably, there could be some register somewhere where all 1s is
> valid? So I think we need the error values.
We have to assume ~0 is a valid value for any config registers except
the few defined by the spec that have bits required to be 0. There
can be all kinds of vendor-defined stuff in config space that can be
anything.
> Also, I seem to recall only the vendor/device IDs are defined to be
> all 1s for non-existent devices. Other errors are undefined?
I think this case is actually an instance of the PCI controller
fabricating ~0 because a PCI/PCIe error occurred (I think on PCI it's
a Master Abort when nothing responds; on PCIe the read terminates as
an Unsupported Request (PCIe r5.0, sec 2.3.2)).
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next prev parent reply other threads:[~2021-10-13 22:12 UTC|newest]
Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-11 17:35 [PATCH 00/22] PCI: Unify PCI error response checking Naveen Naidu
2021-10-11 17:35 ` Naveen Naidu
2021-10-11 17:35 ` Naveen Naidu
2021-10-11 17:35 ` Naveen Naidu
2021-10-11 17:35 ` Naveen Naidu
2021-10-11 17:35 ` Naveen Naidu
2021-10-11 17:37 ` [PATCH 01/22] PCI: Add PCI_ERROR_RESPONSE and it's related defintions Naveen Naidu
2021-10-11 17:37 ` Naveen Naidu
2021-10-11 17:37 ` Naveen Naidu
2021-10-11 17:37 ` Naveen Naidu
2021-10-11 17:37 ` Naveen Naidu
2021-10-11 17:37 ` Naveen Naidu
2021-10-11 17:38 ` [PATCH 02/22] PCI: Unify PCI error response checking Naveen Naidu
2021-10-11 17:38 ` Naveen Naidu
2021-10-11 22:05 ` Rob Herring
2021-10-11 22:05 ` Rob Herring
2021-10-12 16:21 ` Naveen Naidu
2021-10-12 16:21 ` Naveen Naidu
2021-10-12 18:02 ` Rob Herring
2021-10-12 18:02 ` Rob Herring
2021-10-12 22:52 ` Pali Rohár
2021-10-12 22:52 ` Pali Rohár
2021-10-13 2:43 ` Bjorn Helgaas
2021-10-13 2:43 ` Bjorn Helgaas
2021-10-13 13:06 ` Rob Herring
2021-10-13 13:06 ` Rob Herring
2021-10-13 17:16 ` Naveen Naidu
2021-10-13 17:16 ` Naveen Naidu
2021-10-13 17:54 ` Pali Rohár
2021-10-13 17:54 ` Pali Rohár
2021-10-13 18:48 ` Bjorn Helgaas
2021-10-13 18:48 ` Bjorn Helgaas
2021-10-13 21:47 ` Rob Herring
2021-10-13 21:47 ` Rob Herring
2021-10-13 22:03 ` Pali Rohár
2021-10-13 22:03 ` Pali Rohár
2021-10-13 22:12 ` Bjorn Helgaas [this message]
2021-10-13 22:12 ` Bjorn Helgaas
2021-10-11 17:45 ` [PATCH 03/22] PCI: thunder: Use SET_PCI_ERROR_RESPONSE() when device not found Naveen Naidu
2021-10-11 17:45 ` Naveen Naidu
2021-10-11 17:45 ` Naveen Naidu
2021-10-11 17:46 ` [PATCH 04/22] PCI: iproc: " Naveen Naidu
2021-10-11 17:46 ` Naveen Naidu
2021-10-11 17:46 ` Naveen Naidu
2021-10-11 17:51 ` [PATCH 05/22] PCI: mediatek: " Naveen Naidu
2021-10-11 17:51 ` Naveen Naidu
2021-10-11 17:51 ` Naveen Naidu
2021-10-11 17:51 ` Naveen Naidu
2021-10-11 17:52 ` [PATCH 06/22] PCI: exynos: " Naveen Naidu
2021-10-11 17:52 ` Naveen Naidu
2021-10-11 17:52 ` Naveen Naidu
2021-10-11 17:53 ` [PATCH 07/22] PCI: histb: " Naveen Naidu
2021-10-11 17:53 ` Naveen Naidu
2021-10-11 17:55 ` [PATCH 08/22] PCI: kirin: " Naveen Naidu
2021-10-11 17:55 ` Naveen Naidu
2021-10-11 17:56 ` [PATCH 09/22] PCI: aardvark: " Naveen Naidu
2021-10-11 17:56 ` Naveen Naidu
2021-10-11 17:56 ` Naveen Naidu
2021-10-11 18:08 ` Pali Rohár
2021-10-11 18:08 ` Pali Rohár
2021-10-11 18:08 ` Pali Rohár
2021-10-11 18:28 ` Naveen Naidu
2021-10-11 18:28 ` Naveen Naidu
2021-10-11 18:28 ` Naveen Naidu
[not found] ` <20211011182526.kboaxqofdpd2jjrl@theprophet>
2021-10-11 18:41 ` Pali Rohár
2021-10-11 18:41 ` Pali Rohár
2021-10-11 18:41 ` Pali Rohár
2021-10-12 15:59 ` Naveen Naidu
2021-10-12 15:59 ` Naveen Naidu
2021-10-12 15:59 ` Naveen Naidu
2021-10-13 2:13 ` Bjorn Helgaas
2021-10-13 2:13 ` Bjorn Helgaas
2021-10-13 2:13 ` Bjorn Helgaas
2021-10-13 17:59 ` Pali Rohár
2021-10-13 17:59 ` Pali Rohár
2021-10-13 17:59 ` Pali Rohár
2021-10-11 18:00 ` [PATCH 10/22] PCI: mvebu: " Naveen Naidu
2021-10-11 18:00 ` Naveen Naidu
2021-10-11 18:00 ` Naveen Naidu
2021-10-11 18:00 ` [PATCH 11/22] PCI: altera: " Naveen Naidu
2021-10-11 18:00 ` Naveen Naidu
2021-10-11 18:02 ` [PATCH 12/22] PCI: rcar: " Naveen Naidu
2021-10-11 18:02 ` Naveen Naidu
2021-10-11 18:02 ` [PATCH 13/22] PCI: rockchip: " Naveen Naidu
2021-10-11 18:02 ` Naveen Naidu
2021-10-11 18:02 ` Naveen Naidu
2021-10-11 18:02 ` Naveen Naidu
2021-10-11 18:04 ` [PATCH 14/22] PCI/ERR: Use RESPONSE_IS_PCI_ERROR() to check read from hardware Naveen Naidu
2021-10-11 18:04 ` Naveen Naidu
2021-10-11 18:06 ` [PATCH 15/22] PCI: vmd: " Naveen Naidu
2021-10-11 18:06 ` Naveen Naidu
2021-10-14 18:04 ` Jonathan Derrick
2021-10-14 18:04 ` Jonathan Derrick
2021-10-11 18:07 ` [PATCH 16/22] PCI: pciehp: " Naveen Naidu
2021-10-11 18:07 ` Naveen Naidu
2021-10-11 19:47 ` Lukas Wunner
2021-10-11 19:47 ` Lukas Wunner
2021-10-12 16:05 ` Naveen Naidu
2021-10-12 16:05 ` Naveen Naidu
2021-10-12 23:12 ` Pali Rohár
2021-10-12 23:12 ` Pali Rohár
2021-10-13 12:20 ` Lukas Wunner
2021-10-13 12:20 ` Lukas Wunner
2021-10-11 18:08 ` [PATCH 17/22] PCI/DPC: " Naveen Naidu
2021-10-11 18:08 ` Naveen Naidu
2021-10-11 18:08 ` Naveen Naidu
2021-10-11 18:10 ` [PATCH 18/22] PCI/PME: " Naveen Naidu
2021-10-11 18:10 ` Naveen Naidu
2021-10-11 18:11 ` [PATCH 19/22] PCI: cpqphp: " Naveen Naidu
2021-10-11 18:11 ` Naveen Naidu
2021-10-11 18:11 ` [PATCH 20/22] PCI: keystone: Use PCI_ERROR_RESPONSE to specify hardware error Naveen Naidu
2021-10-11 18:11 ` Naveen Naidu
2021-10-11 18:12 ` [PATCH 21/22] PCI: hv: Use PCI_ERROR_RESPONSE to specify hardware read error Naveen Naidu
2021-10-11 18:12 ` Naveen Naidu
2021-10-11 18:13 ` [PATCH 22/22] PCI: xgene: Use PCI_ERROR_RESPONSE to specify hardware error Naveen Naidu
2021-10-11 18:13 ` Naveen Naidu
2021-10-11 18:13 ` Naveen Naidu
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