From: Jisheng Zhang <jszhang@kernel.org> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Heiko Stuebner <heiko@sntech.de>, Andrew Jones <ajones@ventanamicro.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Date: Mon, 5 Dec 2022 01:46:31 +0800 [thread overview] Message-ID: <20221204174632.3677-13-jszhang@kernel.org> (raw) In-Reply-To: <20221204174632.3677-1-jszhang@kernel.org> From: Andrew Jones <ajones@ventanamicro.com> Switch has_svinval() from static branch to the new helper riscv_has_extension_unlikely(). Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- arch/riscv/kvm/tlb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c index 309d79b3e5cd..aa3da18ad873 100644 --- a/arch/riscv/kvm/tlb.c +++ b/arch/riscv/kvm/tlb.c @@ -15,8 +15,7 @@ #include <asm/hwcap.h> #include <asm/insn-def.h> -#define has_svinval() \ - static_branch_unlikely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_SVINVAL]) +#define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, gpa_t gpa, gpa_t gpsz, -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Heiko Stuebner <heiko@sntech.de>, Andrew Jones <ajones@ventanamicro.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Date: Mon, 5 Dec 2022 01:46:31 +0800 [thread overview] Message-ID: <20221204174632.3677-13-jszhang@kernel.org> (raw) In-Reply-To: <20221204174632.3677-1-jszhang@kernel.org> From: Andrew Jones <ajones@ventanamicro.com> Switch has_svinval() from static branch to the new helper riscv_has_extension_unlikely(). Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- arch/riscv/kvm/tlb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c index 309d79b3e5cd..aa3da18ad873 100644 --- a/arch/riscv/kvm/tlb.c +++ b/arch/riscv/kvm/tlb.c @@ -15,8 +15,7 @@ #include <asm/hwcap.h> #include <asm/insn-def.h> -#define has_svinval() \ - static_branch_unlikely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_SVINVAL]) +#define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, gpa_t gpa, gpa_t gpsz, -- 2.37.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-12-04 17:57 UTC|newest] Thread overview: 104+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-04 17:46 [PATCH v2 00/13] riscv: improve boot time isa extensions handling Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-04 17:46 ` [PATCH v2 01/13] riscv: fix jal offsets in patched alternatives Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 14:57 ` Andrew Jones 2022-12-05 14:57 ` Andrew Jones 2022-12-05 15:34 ` Jisheng Zhang 2022-12-05 15:34 ` Jisheng Zhang 2022-12-05 16:42 ` Jisheng Zhang 2022-12-05 16:42 ` Jisheng Zhang 2022-12-05 16:49 ` Jisheng Zhang 2022-12-05 16:49 ` Jisheng Zhang 2022-12-06 5:50 ` Andrew Jones 2022-12-06 5:50 ` Andrew Jones 2022-12-05 15:31 ` Heiko Stübner 2022-12-05 15:31 ` Heiko Stübner 2022-12-05 15:40 ` Jisheng Zhang 2022-12-05 15:40 ` Jisheng Zhang 2022-12-05 18:36 ` Conor Dooley 2022-12-05 18:36 ` Conor Dooley 2022-12-05 18:49 ` Heiko Stübner 2022-12-05 18:49 ` Heiko Stübner 2022-12-05 19:49 ` Conor Dooley 2022-12-05 19:49 ` Conor Dooley 2022-12-06 0:39 ` Heiko Stübner 2022-12-06 0:39 ` Heiko Stübner 2022-12-06 15:02 ` Jisheng Zhang 2022-12-06 15:02 ` Jisheng Zhang 2022-12-06 16:12 ` Conor Dooley 2022-12-06 16:12 ` Conor Dooley 2022-12-19 21:32 ` Conor Dooley 2022-12-19 21:32 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 02/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-04 21:52 ` Heiko Stübner 2022-12-04 21:52 ` Heiko Stübner 2022-12-05 15:16 ` Jisheng Zhang 2022-12-05 15:16 ` Jisheng Zhang 2022-12-05 15:31 ` Conor Dooley 2022-12-05 15:31 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 03/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 19:09 ` Conor Dooley 2022-12-05 19:09 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 04/13] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 18:53 ` Conor Dooley 2022-12-05 18:53 ` Conor Dooley 2022-12-22 22:58 ` Conor Dooley 2022-12-22 22:58 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 19:37 ` Conor Dooley 2022-12-05 19:37 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 06/13] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-06 20:25 ` Conor Dooley 2022-12-06 20:25 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 07/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-04 17:46 ` [PATCH v2 08/13] riscv: module: move find_section to module.h Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 15:25 ` Andrew Jones 2022-12-05 15:25 ` Andrew Jones 2022-12-06 20:44 ` Conor Dooley 2022-12-06 20:44 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 09/13] riscv: switch to relative alternative entries Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 0:51 ` Guo Ren 2022-12-05 0:51 ` Guo Ren 2022-12-05 15:18 ` Jisheng Zhang 2022-12-05 15:18 ` Jisheng Zhang 2022-12-06 4:34 ` Guo Ren 2022-12-06 4:34 ` Guo Ren 2022-12-06 14:50 ` Jisheng Zhang 2022-12-06 14:50 ` Jisheng Zhang 2022-12-06 21:43 ` Conor Dooley 2022-12-06 21:43 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 10/13] riscv: alternative: patch alternatives in the vDSO Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 1:56 ` Guo Ren 2022-12-05 1:56 ` Guo Ren 2022-12-05 15:23 ` Jisheng Zhang 2022-12-05 15:23 ` Jisheng Zhang 2022-12-06 4:29 ` Guo Ren 2022-12-06 4:29 ` Guo Ren 2023-01-11 14:12 ` Andrew Jones 2023-01-11 14:12 ` Andrew Jones 2022-12-04 17:46 ` [PATCH v2 11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 0:52 ` Guo Ren 2022-12-05 0:52 ` Guo Ren 2022-12-06 22:04 ` Conor Dooley 2022-12-06 22:04 ` Conor Dooley 2022-12-04 17:46 ` Jisheng Zhang [this message] 2022-12-04 17:46 ` [PATCH v2 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Jisheng Zhang 2022-12-05 0:52 ` Guo Ren 2022-12-05 0:52 ` Guo Ren 2022-12-04 17:46 ` [PATCH v2 13/13] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 0:53 ` Guo Ren 2022-12-05 0:53 ` Guo Ren 2022-12-06 22:16 ` Conor Dooley 2022-12-06 22:16 ` Conor Dooley
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