From: Jisheng Zhang <jszhang@kernel.org> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Heiko Stuebner <heiko@sntech.de>, Andrew Jones <ajones@ventanamicro.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 04/13] riscv: hwcap: make ISA extension ids can be used in asm Date: Mon, 5 Dec 2022 01:46:23 +0800 [thread overview] Message-ID: <20221204174632.3677-5-jszhang@kernel.org> (raw) In-Reply-To: <20221204174632.3677-1-jszhang@kernel.org> We will make use of ISA extension in asm files, so make the multi-letter RISC-V ISA extension IDs macros rather than enums and move them and those base ISA extension IDs to suitable place. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> --- arch/riscv/include/asm/hwcap.h | 43 ++++++++++++++++------------------ 1 file changed, 20 insertions(+), 23 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b22525290073..996884986fea 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -12,20 +12,6 @@ #include <linux/bits.h> #include <uapi/asm/hwcap.h> -#ifndef __ASSEMBLY__ -#include <linux/jump_label.h> -/* - * This yields a mask that user programs can use to figure out what - * instruction set this cpu supports. - */ -#define ELF_HWCAP (elf_hwcap) - -enum { - CAP_HWCAP = 1, -}; - -extern unsigned long elf_hwcap; - #define RISCV_ISA_EXT_a ('a' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') @@ -46,22 +32,33 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_BASE 26 /* - * This enum represent the logical ID for each multi-letter RISC-V ISA extension. + * These macros represent the logical ID for each multi-letter RISC-V ISA extension. * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter * extensions while all the multi-letter extensions should define the next * available logical extension id. */ -enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, - RISCV_ISA_EXT_SVPBMT, - RISCV_ISA_EXT_ZICBOM, - RISCV_ISA_EXT_ZIHINTPAUSE, - RISCV_ISA_EXT_SSTC, - RISCV_ISA_EXT_SVINVAL, - RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, +#define RISCV_ISA_EXT_SSCOFPMF 26 +#define RISCV_ISA_EXT_SVPBMT 27 +#define RISCV_ISA_EXT_ZICBOM 28 +#define RISCV_ISA_EXT_ZIHINTPAUSE 29 +#define RISCV_ISA_EXT_SSTC 30 +#define RISCV_ISA_EXT_SVINVAL 31 + +#ifndef __ASSEMBLY__ +#include <linux/jump_label.h> +/* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +#define ELF_HWCAP (elf_hwcap) + +enum { + CAP_HWCAP = 1, }; +extern unsigned long elf_hwcap; + /* * This enum represents the logical ID for each RISC-V ISA extension static * keys. We can use static key to optimize code path if some ISA extensions -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Heiko Stuebner <heiko@sntech.de>, Andrew Jones <ajones@ventanamicro.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 04/13] riscv: hwcap: make ISA extension ids can be used in asm Date: Mon, 5 Dec 2022 01:46:23 +0800 [thread overview] Message-ID: <20221204174632.3677-5-jszhang@kernel.org> (raw) In-Reply-To: <20221204174632.3677-1-jszhang@kernel.org> We will make use of ISA extension in asm files, so make the multi-letter RISC-V ISA extension IDs macros rather than enums and move them and those base ISA extension IDs to suitable place. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> --- arch/riscv/include/asm/hwcap.h | 43 ++++++++++++++++------------------ 1 file changed, 20 insertions(+), 23 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b22525290073..996884986fea 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -12,20 +12,6 @@ #include <linux/bits.h> #include <uapi/asm/hwcap.h> -#ifndef __ASSEMBLY__ -#include <linux/jump_label.h> -/* - * This yields a mask that user programs can use to figure out what - * instruction set this cpu supports. - */ -#define ELF_HWCAP (elf_hwcap) - -enum { - CAP_HWCAP = 1, -}; - -extern unsigned long elf_hwcap; - #define RISCV_ISA_EXT_a ('a' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') @@ -46,22 +32,33 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_BASE 26 /* - * This enum represent the logical ID for each multi-letter RISC-V ISA extension. + * These macros represent the logical ID for each multi-letter RISC-V ISA extension. * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter * extensions while all the multi-letter extensions should define the next * available logical extension id. */ -enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, - RISCV_ISA_EXT_SVPBMT, - RISCV_ISA_EXT_ZICBOM, - RISCV_ISA_EXT_ZIHINTPAUSE, - RISCV_ISA_EXT_SSTC, - RISCV_ISA_EXT_SVINVAL, - RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, +#define RISCV_ISA_EXT_SSCOFPMF 26 +#define RISCV_ISA_EXT_SVPBMT 27 +#define RISCV_ISA_EXT_ZICBOM 28 +#define RISCV_ISA_EXT_ZIHINTPAUSE 29 +#define RISCV_ISA_EXT_SSTC 30 +#define RISCV_ISA_EXT_SVINVAL 31 + +#ifndef __ASSEMBLY__ +#include <linux/jump_label.h> +/* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +#define ELF_HWCAP (elf_hwcap) + +enum { + CAP_HWCAP = 1, }; +extern unsigned long elf_hwcap; + /* * This enum represents the logical ID for each RISC-V ISA extension static * keys. We can use static key to optimize code path if some ISA extensions -- 2.37.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-12-04 17:57 UTC|newest] Thread overview: 104+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-04 17:46 [PATCH v2 00/13] riscv: improve boot time isa extensions handling Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-04 17:46 ` [PATCH v2 01/13] riscv: fix jal offsets in patched alternatives Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 14:57 ` Andrew Jones 2022-12-05 14:57 ` Andrew Jones 2022-12-05 15:34 ` Jisheng Zhang 2022-12-05 15:34 ` Jisheng Zhang 2022-12-05 16:42 ` Jisheng Zhang 2022-12-05 16:42 ` Jisheng Zhang 2022-12-05 16:49 ` Jisheng Zhang 2022-12-05 16:49 ` Jisheng Zhang 2022-12-06 5:50 ` Andrew Jones 2022-12-06 5:50 ` Andrew Jones 2022-12-05 15:31 ` Heiko Stübner 2022-12-05 15:31 ` Heiko Stübner 2022-12-05 15:40 ` Jisheng Zhang 2022-12-05 15:40 ` Jisheng Zhang 2022-12-05 18:36 ` Conor Dooley 2022-12-05 18:36 ` Conor Dooley 2022-12-05 18:49 ` Heiko Stübner 2022-12-05 18:49 ` Heiko Stübner 2022-12-05 19:49 ` Conor Dooley 2022-12-05 19:49 ` Conor Dooley 2022-12-06 0:39 ` Heiko Stübner 2022-12-06 0:39 ` Heiko Stübner 2022-12-06 15:02 ` Jisheng Zhang 2022-12-06 15:02 ` Jisheng Zhang 2022-12-06 16:12 ` Conor Dooley 2022-12-06 16:12 ` Conor Dooley 2022-12-19 21:32 ` Conor Dooley 2022-12-19 21:32 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 02/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-04 21:52 ` Heiko Stübner 2022-12-04 21:52 ` Heiko Stübner 2022-12-05 15:16 ` Jisheng Zhang 2022-12-05 15:16 ` Jisheng Zhang 2022-12-05 15:31 ` Conor Dooley 2022-12-05 15:31 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 03/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 19:09 ` Conor Dooley 2022-12-05 19:09 ` Conor Dooley 2022-12-04 17:46 ` Jisheng Zhang [this message] 2022-12-04 17:46 ` [PATCH v2 04/13] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang 2022-12-05 18:53 ` Conor Dooley 2022-12-05 18:53 ` Conor Dooley 2022-12-22 22:58 ` Conor Dooley 2022-12-22 22:58 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 19:37 ` Conor Dooley 2022-12-05 19:37 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 06/13] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-06 20:25 ` Conor Dooley 2022-12-06 20:25 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 07/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-04 17:46 ` [PATCH v2 08/13] riscv: module: move find_section to module.h Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 15:25 ` Andrew Jones 2022-12-05 15:25 ` Andrew Jones 2022-12-06 20:44 ` Conor Dooley 2022-12-06 20:44 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 09/13] riscv: switch to relative alternative entries Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 0:51 ` Guo Ren 2022-12-05 0:51 ` Guo Ren 2022-12-05 15:18 ` Jisheng Zhang 2022-12-05 15:18 ` Jisheng Zhang 2022-12-06 4:34 ` Guo Ren 2022-12-06 4:34 ` Guo Ren 2022-12-06 14:50 ` Jisheng Zhang 2022-12-06 14:50 ` Jisheng Zhang 2022-12-06 21:43 ` Conor Dooley 2022-12-06 21:43 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 10/13] riscv: alternative: patch alternatives in the vDSO Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 1:56 ` Guo Ren 2022-12-05 1:56 ` Guo Ren 2022-12-05 15:23 ` Jisheng Zhang 2022-12-05 15:23 ` Jisheng Zhang 2022-12-06 4:29 ` Guo Ren 2022-12-06 4:29 ` Guo Ren 2023-01-11 14:12 ` Andrew Jones 2023-01-11 14:12 ` Andrew Jones 2022-12-04 17:46 ` [PATCH v2 11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 0:52 ` Guo Ren 2022-12-05 0:52 ` Guo Ren 2022-12-06 22:04 ` Conor Dooley 2022-12-06 22:04 ` Conor Dooley 2022-12-04 17:46 ` [PATCH v2 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 0:52 ` Guo Ren 2022-12-05 0:52 ` Guo Ren 2022-12-04 17:46 ` [PATCH v2 13/13] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang 2022-12-04 17:46 ` Jisheng Zhang 2022-12-05 0:53 ` Guo Ren 2022-12-05 0:53 ` Guo Ren 2022-12-06 22:16 ` Conor Dooley 2022-12-06 22:16 ` Conor Dooley
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