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From: Conor Dooley <conor@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Andrew Jones <ajones@ventanamicro.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: Re: [PATCH v2 06/13] riscv: introduce riscv_has_extension_[un]likely()
Date: Tue, 6 Dec 2022 20:25:34 +0000	[thread overview]
Message-ID: <Y4+lPiF7CpJJjmWR@spud> (raw)
In-Reply-To: <20221204174632.3677-7-jszhang@kernel.org>

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Hey Jisheng,

Just a couple really minor bits here...

On Mon, Dec 05, 2022 at 01:46:25AM +0800, Jisheng Zhang wrote:
> Generally, riscv ISA extensions are fixed for any specific hardware
> platform, that's to say, the hart features won't change any more

s/that's to say, the hart/so a hart's/
s/any more//

> after booting, this chacteristic make it straightforward to use

"booting. This characteristic makes it"

> static branch to check one specific ISA extension is supported or not

"a static branch to check if a"

> to optimize performance.
> 
> However, some ISA extensions such as SVPBMT and ZICBOM are handled
> via. the alternative sequences.
> 
> Basically, for ease of maintenance, we prefer to use static branches
> in C code, but recently, Samuel found that the static branch usage in
> cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As
> Samuel pointed out, "Having a static branch in cpu_relax() is
> problematic because that function is widely inlined, including in some
> quite complex functions like in the VDSO. A quick measurement shows
> this static branch is responsible by itself for around 40% of the jump
> table."
> 
> Samuel's findings pointed out one of a few downsides of static branches
> usage in C code to handle ISA extensions detected at boot time:
> static branch's metadata in the __jump_table section, which is not
> discarded after ISA extensions are finalized, wastes some space.
> 
> I want to try to solve the issue for all possible dynamic handling of
> ISA extensions at boot time. Inspired by Mark[2], this patch introduces
> riscv_has_extension_*() helpers, which work like static branches but
> are patched using alternatives, thus the metadata can be freed after
> patching.
> 
> [1]https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/
> [2]https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/

Can you make these into Link: tags please (and drop the line between the
and the SoB)? So:

Link: https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/ [1]
Link: https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/ [2]
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Changes themselves look grand, no comments there :)

Thanks!
Conor.

> ---
>  arch/riscv/include/asm/hwcap.h | 37 ++++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 996884986fea..e2d3f6df7701 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -8,6 +8,7 @@
>  #ifndef _ASM_RISCV_HWCAP_H
>  #define _ASM_RISCV_HWCAP_H
>  
> +#include <asm/alternative-macros.h>
>  #include <asm/errno.h>
>  #include <linux/bits.h>
>  #include <uapi/asm/hwcap.h>
> @@ -96,6 +97,42 @@ static __always_inline int riscv_isa_ext2key(int num)
>  	}
>  }
>  
> +static __always_inline bool
> +riscv_has_extension_likely(const unsigned long ext)
> +{
> +	compiletime_assert(ext < RISCV_ISA_EXT_MAX,
> +			   "ext must be < RISCV_ISA_EXT_MAX");
> +
> +	asm_volatile_goto(
> +	ALTERNATIVE("j	%l[l_no]", "nop", 0, %[ext], 1)
> +	:
> +	: [ext] "i" (ext)
> +	:
> +	: l_no);
> +
> +	return true;
> +l_no:
> +	return false;
> +}
> +
> +static __always_inline bool
> +riscv_has_extension_unlikely(const unsigned long ext)
> +{
> +	compiletime_assert(ext < RISCV_ISA_EXT_MAX,
> +			   "ext must be < RISCV_ISA_EXT_MAX");
> +
> +	asm_volatile_goto(
> +	ALTERNATIVE("nop", "j	%l[l_yes]", 0, %[ext], 1)
> +	:
> +	: [ext] "i" (ext)
> +	:
> +	: l_yes);
> +
> +	return false;
> +l_yes:
> +	return true;
> +}
> +
>  unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
>  
>  #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
> -- 
> 2.37.2
> 

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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Andrew Jones <ajones@ventanamicro.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: Re: [PATCH v2 06/13] riscv: introduce riscv_has_extension_[un]likely()
Date: Tue, 6 Dec 2022 20:25:34 +0000	[thread overview]
Message-ID: <Y4+lPiF7CpJJjmWR@spud> (raw)
In-Reply-To: <20221204174632.3677-7-jszhang@kernel.org>


[-- Attachment #1.1: Type: text/plain, Size: 4023 bytes --]

Hey Jisheng,

Just a couple really minor bits here...

On Mon, Dec 05, 2022 at 01:46:25AM +0800, Jisheng Zhang wrote:
> Generally, riscv ISA extensions are fixed for any specific hardware
> platform, that's to say, the hart features won't change any more

s/that's to say, the hart/so a hart's/
s/any more//

> after booting, this chacteristic make it straightforward to use

"booting. This characteristic makes it"

> static branch to check one specific ISA extension is supported or not

"a static branch to check if a"

> to optimize performance.
> 
> However, some ISA extensions such as SVPBMT and ZICBOM are handled
> via. the alternative sequences.
> 
> Basically, for ease of maintenance, we prefer to use static branches
> in C code, but recently, Samuel found that the static branch usage in
> cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As
> Samuel pointed out, "Having a static branch in cpu_relax() is
> problematic because that function is widely inlined, including in some
> quite complex functions like in the VDSO. A quick measurement shows
> this static branch is responsible by itself for around 40% of the jump
> table."
> 
> Samuel's findings pointed out one of a few downsides of static branches
> usage in C code to handle ISA extensions detected at boot time:
> static branch's metadata in the __jump_table section, which is not
> discarded after ISA extensions are finalized, wastes some space.
> 
> I want to try to solve the issue for all possible dynamic handling of
> ISA extensions at boot time. Inspired by Mark[2], this patch introduces
> riscv_has_extension_*() helpers, which work like static branches but
> are patched using alternatives, thus the metadata can be freed after
> patching.
> 
> [1]https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/
> [2]https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/

Can you make these into Link: tags please (and drop the line between the
and the SoB)? So:

Link: https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/ [1]
Link: https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/ [2]
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Changes themselves look grand, no comments there :)

Thanks!
Conor.

> ---
>  arch/riscv/include/asm/hwcap.h | 37 ++++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 996884986fea..e2d3f6df7701 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -8,6 +8,7 @@
>  #ifndef _ASM_RISCV_HWCAP_H
>  #define _ASM_RISCV_HWCAP_H
>  
> +#include <asm/alternative-macros.h>
>  #include <asm/errno.h>
>  #include <linux/bits.h>
>  #include <uapi/asm/hwcap.h>
> @@ -96,6 +97,42 @@ static __always_inline int riscv_isa_ext2key(int num)
>  	}
>  }
>  
> +static __always_inline bool
> +riscv_has_extension_likely(const unsigned long ext)
> +{
> +	compiletime_assert(ext < RISCV_ISA_EXT_MAX,
> +			   "ext must be < RISCV_ISA_EXT_MAX");
> +
> +	asm_volatile_goto(
> +	ALTERNATIVE("j	%l[l_no]", "nop", 0, %[ext], 1)
> +	:
> +	: [ext] "i" (ext)
> +	:
> +	: l_no);
> +
> +	return true;
> +l_no:
> +	return false;
> +}
> +
> +static __always_inline bool
> +riscv_has_extension_unlikely(const unsigned long ext)
> +{
> +	compiletime_assert(ext < RISCV_ISA_EXT_MAX,
> +			   "ext must be < RISCV_ISA_EXT_MAX");
> +
> +	asm_volatile_goto(
> +	ALTERNATIVE("nop", "j	%l[l_yes]", 0, %[ext], 1)
> +	:
> +	: [ext] "i" (ext)
> +	:
> +	: l_yes);
> +
> +	return false;
> +l_yes:
> +	return true;
> +}
> +
>  unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
>  
>  #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
> -- 
> 2.37.2
> 

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  reply	other threads:[~2022-12-06 20:25 UTC|newest]

Thread overview: 104+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-04 17:46 [PATCH v2 00/13] riscv: improve boot time isa extensions handling Jisheng Zhang
2022-12-04 17:46 ` Jisheng Zhang
2022-12-04 17:46 ` [PATCH v2 01/13] riscv: fix jal offsets in patched alternatives Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-05 14:57   ` Andrew Jones
2022-12-05 14:57     ` Andrew Jones
2022-12-05 15:34     ` Jisheng Zhang
2022-12-05 15:34       ` Jisheng Zhang
2022-12-05 16:42     ` Jisheng Zhang
2022-12-05 16:42       ` Jisheng Zhang
2022-12-05 16:49       ` Jisheng Zhang
2022-12-05 16:49         ` Jisheng Zhang
2022-12-06  5:50         ` Andrew Jones
2022-12-06  5:50           ` Andrew Jones
2022-12-05 15:31   ` Heiko Stübner
2022-12-05 15:31     ` Heiko Stübner
2022-12-05 15:40     ` Jisheng Zhang
2022-12-05 15:40       ` Jisheng Zhang
2022-12-05 18:36       ` Conor Dooley
2022-12-05 18:36         ` Conor Dooley
2022-12-05 18:49         ` Heiko Stübner
2022-12-05 18:49           ` Heiko Stübner
2022-12-05 19:49           ` Conor Dooley
2022-12-05 19:49             ` Conor Dooley
2022-12-06  0:39             ` Heiko Stübner
2022-12-06  0:39               ` Heiko Stübner
2022-12-06 15:02               ` Jisheng Zhang
2022-12-06 15:02                 ` Jisheng Zhang
2022-12-06 16:12                 ` Conor Dooley
2022-12-06 16:12                   ` Conor Dooley
2022-12-19 21:32                   ` Conor Dooley
2022-12-19 21:32                     ` Conor Dooley
2022-12-04 17:46 ` [PATCH v2 02/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-04 21:52   ` Heiko Stübner
2022-12-04 21:52     ` Heiko Stübner
2022-12-05 15:16     ` Jisheng Zhang
2022-12-05 15:16       ` Jisheng Zhang
2022-12-05 15:31       ` Conor Dooley
2022-12-05 15:31         ` Conor Dooley
2022-12-04 17:46 ` [PATCH v2 03/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-05 19:09   ` Conor Dooley
2022-12-05 19:09     ` Conor Dooley
2022-12-04 17:46 ` [PATCH v2 04/13] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-05 18:53   ` Conor Dooley
2022-12-05 18:53     ` Conor Dooley
2022-12-22 22:58     ` Conor Dooley
2022-12-22 22:58       ` Conor Dooley
2022-12-04 17:46 ` [PATCH v2 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-05 19:37   ` Conor Dooley
2022-12-05 19:37     ` Conor Dooley
2022-12-04 17:46 ` [PATCH v2 06/13] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-06 20:25   ` Conor Dooley [this message]
2022-12-06 20:25     ` Conor Dooley
2022-12-04 17:46 ` [PATCH v2 07/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-04 17:46 ` [PATCH v2 08/13] riscv: module: move find_section to module.h Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-05 15:25   ` Andrew Jones
2022-12-05 15:25     ` Andrew Jones
2022-12-06 20:44   ` Conor Dooley
2022-12-06 20:44     ` Conor Dooley
2022-12-04 17:46 ` [PATCH v2 09/13] riscv: switch to relative alternative entries Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-05  0:51   ` Guo Ren
2022-12-05  0:51     ` Guo Ren
2022-12-05 15:18     ` Jisheng Zhang
2022-12-05 15:18       ` Jisheng Zhang
2022-12-06  4:34       ` Guo Ren
2022-12-06  4:34         ` Guo Ren
2022-12-06 14:50         ` Jisheng Zhang
2022-12-06 14:50           ` Jisheng Zhang
2022-12-06 21:43           ` Conor Dooley
2022-12-06 21:43             ` Conor Dooley
2022-12-04 17:46 ` [PATCH v2 10/13] riscv: alternative: patch alternatives in the vDSO Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-05  1:56   ` Guo Ren
2022-12-05  1:56     ` Guo Ren
2022-12-05 15:23     ` Jisheng Zhang
2022-12-05 15:23       ` Jisheng Zhang
2022-12-06  4:29       ` Guo Ren
2022-12-06  4:29         ` Guo Ren
2023-01-11 14:12   ` Andrew Jones
2023-01-11 14:12     ` Andrew Jones
2022-12-04 17:46 ` [PATCH v2 11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-05  0:52   ` Guo Ren
2022-12-05  0:52     ` Guo Ren
2022-12-06 22:04   ` Conor Dooley
2022-12-06 22:04     ` Conor Dooley
2022-12-04 17:46 ` [PATCH v2 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-05  0:52   ` Guo Ren
2022-12-05  0:52     ` Guo Ren
2022-12-04 17:46 ` [PATCH v2 13/13] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang
2022-12-04 17:46   ` Jisheng Zhang
2022-12-05  0:53   ` Guo Ren
2022-12-05  0:53     ` Guo Ren
2022-12-06 22:16   ` Conor Dooley
2022-12-06 22:16     ` Conor Dooley

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