From: Hal Feng <hal.feng@starfivetech.com> To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org> Cc: Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, "Daniel Lezcano" <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Date: Tue, 21 Feb 2023 10:46:34 +0800 [thread overview] Message-ID: <20230221024645.127922-9-hal.feng@starfivetech.com> (raw) In-Reply-To: <20230221024645.127922-1-hal.feng@starfivetech.com> From: Emil Renner Berthing <kernel@esmil.dk> We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're only ever accessed in pairs on 64bit boundaries. There are however other reset controllers for audio and video on the JH7100 SoC with only one status register that isn't 64bit aligned so 64bit I/O results in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- .../reset/starfive/reset-starfive-jh7100.c | 14 ++++----- .../reset/starfive/reset-starfive-jh71x0.c | 31 +++++++++---------- .../reset/starfive/reset-starfive-jh71x0.h | 2 +- 3 files changed, 23 insertions(+), 24 deletions(-) diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c index 5f06e5ae3346..2a56f7fd4ba7 100644 --- a/drivers/reset/starfive/reset-starfive-jh7100.c +++ b/drivers/reset/starfive/reset-starfive-jh7100.c @@ -30,16 +30,16 @@ * lines don't though, so store the expected value of the status registers when * all lines are asserted. */ -static const u64 jh7100_reset_asserted[2] = { +static const u32 jh7100_reset_asserted[4] = { /* STATUS0 */ - BIT_ULL_MASK(JH7100_RST_U74) | - BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | - BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | + BIT(JH7100_RST_U74 % 32) | + BIT(JH7100_RST_VP6_DRESET % 32) | + BIT(JH7100_RST_VP6_BRESET % 32), /* STATUS1 */ - BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | - BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), + BIT(JH7100_RST_HIFI4_DRESET % 32) | + BIT(JH7100_RST_HIFI4_BRESET % 32), /* STATUS2 */ - BIT_ULL_MASK(JH7100_RST_E24) | + BIT(JH7100_RST_E24 % 32), /* STATUS3 */ 0, }; diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c index a689f4730ed7..55bbbd2de52c 100644 --- a/drivers/reset/starfive/reset-starfive-jh71x0.c +++ b/drivers/reset/starfive/reset-starfive-jh71x0.c @@ -8,7 +8,6 @@ #include <linux/bitmap.h> #include <linux/device.h> #include <linux/io.h> -#include <linux/io-64-nonatomic-lo-hi.h> #include <linux/iopoll.h> #include <linux/reset-controller.h> #include <linux/spinlock.h> @@ -21,7 +20,7 @@ struct jh71x0_reset { spinlock_t lock; void __iomem *assert; void __iomem *status; - const u64 *asserted; + const u32 *asserted; }; static inline struct jh71x0_reset * @@ -34,12 +33,12 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { struct jh71x0_reset *data = jh71x0_reset_from(rcdev); - unsigned long offset = BIT_ULL_WORD(id); - u64 mask = BIT_ULL_MASK(id); - void __iomem *reg_assert = data->assert + offset * sizeof(u64); - void __iomem *reg_status = data->status + offset * sizeof(u64); - u64 done = data->asserted ? data->asserted[offset] & mask : 0; - u64 value; + unsigned long offset = id / 32; + u32 mask = BIT(id % 32); + void __iomem *reg_assert = data->assert + offset * sizeof(u32); + void __iomem *reg_status = data->status + offset * sizeof(u32); + u32 done = data->asserted ? data->asserted[offset] & mask : 0; + u32 value; unsigned long flags; int ret; @@ -48,15 +47,15 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev, spin_lock_irqsave(&data->lock, flags); - value = readq(reg_assert); + value = readl(reg_assert); if (assert) value |= mask; else value &= ~mask; - writeq(value, reg_assert); + writel(value, reg_assert); /* if the associated clock is gated, deasserting might otherwise hang forever */ - ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); + ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); spin_unlock_irqrestore(&data->lock, flags); return ret; @@ -90,10 +89,10 @@ static int jh71x0_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { struct jh71x0_reset *data = jh71x0_reset_from(rcdev); - unsigned long offset = BIT_ULL_WORD(id); - u64 mask = BIT_ULL_MASK(id); - void __iomem *reg_status = data->status + offset * sizeof(u64); - u64 value = readq(reg_status); + unsigned long offset = id / 32; + u32 mask = BIT(id % 32); + void __iomem *reg_status = data->status + offset * sizeof(u32); + u32 value = readl(reg_status); return !((value ^ data->asserted[offset]) & mask); } @@ -107,7 +106,7 @@ static const struct reset_control_ops jh71x0_reset_ops = { int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, void __iomem *assert, void __iomem *status, - const u64 *asserted, unsigned int nr_resets, + const u32 *asserted, unsigned int nr_resets, struct module *owner) { struct jh71x0_reset *data; diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h index ac9e80dd3f59..db7d39a87f87 100644 --- a/drivers/reset/starfive/reset-starfive-jh71x0.h +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h @@ -8,7 +8,7 @@ int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, void __iomem *assert, void __iomem *status, - const u64 *asserted, unsigned int nr_resets, + const u32 *asserted, unsigned int nr_resets, struct module *owner); #endif /* __RESET_STARFIVE_JH71X0_H */ -- 2.38.1
WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@starfivetech.com> To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org> Cc: Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, "Daniel Lezcano" <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Date: Tue, 21 Feb 2023 10:46:34 +0800 [thread overview] Message-ID: <20230221024645.127922-9-hal.feng@starfivetech.com> (raw) In-Reply-To: <20230221024645.127922-1-hal.feng@starfivetech.com> From: Emil Renner Berthing <kernel@esmil.dk> We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're only ever accessed in pairs on 64bit boundaries. There are however other reset controllers for audio and video on the JH7100 SoC with only one status register that isn't 64bit aligned so 64bit I/O results in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- .../reset/starfive/reset-starfive-jh7100.c | 14 ++++----- .../reset/starfive/reset-starfive-jh71x0.c | 31 +++++++++---------- .../reset/starfive/reset-starfive-jh71x0.h | 2 +- 3 files changed, 23 insertions(+), 24 deletions(-) diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c index 5f06e5ae3346..2a56f7fd4ba7 100644 --- a/drivers/reset/starfive/reset-starfive-jh7100.c +++ b/drivers/reset/starfive/reset-starfive-jh7100.c @@ -30,16 +30,16 @@ * lines don't though, so store the expected value of the status registers when * all lines are asserted. */ -static const u64 jh7100_reset_asserted[2] = { +static const u32 jh7100_reset_asserted[4] = { /* STATUS0 */ - BIT_ULL_MASK(JH7100_RST_U74) | - BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | - BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | + BIT(JH7100_RST_U74 % 32) | + BIT(JH7100_RST_VP6_DRESET % 32) | + BIT(JH7100_RST_VP6_BRESET % 32), /* STATUS1 */ - BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | - BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), + BIT(JH7100_RST_HIFI4_DRESET % 32) | + BIT(JH7100_RST_HIFI4_BRESET % 32), /* STATUS2 */ - BIT_ULL_MASK(JH7100_RST_E24) | + BIT(JH7100_RST_E24 % 32), /* STATUS3 */ 0, }; diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c index a689f4730ed7..55bbbd2de52c 100644 --- a/drivers/reset/starfive/reset-starfive-jh71x0.c +++ b/drivers/reset/starfive/reset-starfive-jh71x0.c @@ -8,7 +8,6 @@ #include <linux/bitmap.h> #include <linux/device.h> #include <linux/io.h> -#include <linux/io-64-nonatomic-lo-hi.h> #include <linux/iopoll.h> #include <linux/reset-controller.h> #include <linux/spinlock.h> @@ -21,7 +20,7 @@ struct jh71x0_reset { spinlock_t lock; void __iomem *assert; void __iomem *status; - const u64 *asserted; + const u32 *asserted; }; static inline struct jh71x0_reset * @@ -34,12 +33,12 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { struct jh71x0_reset *data = jh71x0_reset_from(rcdev); - unsigned long offset = BIT_ULL_WORD(id); - u64 mask = BIT_ULL_MASK(id); - void __iomem *reg_assert = data->assert + offset * sizeof(u64); - void __iomem *reg_status = data->status + offset * sizeof(u64); - u64 done = data->asserted ? data->asserted[offset] & mask : 0; - u64 value; + unsigned long offset = id / 32; + u32 mask = BIT(id % 32); + void __iomem *reg_assert = data->assert + offset * sizeof(u32); + void __iomem *reg_status = data->status + offset * sizeof(u32); + u32 done = data->asserted ? data->asserted[offset] & mask : 0; + u32 value; unsigned long flags; int ret; @@ -48,15 +47,15 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev, spin_lock_irqsave(&data->lock, flags); - value = readq(reg_assert); + value = readl(reg_assert); if (assert) value |= mask; else value &= ~mask; - writeq(value, reg_assert); + writel(value, reg_assert); /* if the associated clock is gated, deasserting might otherwise hang forever */ - ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); + ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); spin_unlock_irqrestore(&data->lock, flags); return ret; @@ -90,10 +89,10 @@ static int jh71x0_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { struct jh71x0_reset *data = jh71x0_reset_from(rcdev); - unsigned long offset = BIT_ULL_WORD(id); - u64 mask = BIT_ULL_MASK(id); - void __iomem *reg_status = data->status + offset * sizeof(u64); - u64 value = readq(reg_status); + unsigned long offset = id / 32; + u32 mask = BIT(id % 32); + void __iomem *reg_status = data->status + offset * sizeof(u32); + u32 value = readl(reg_status); return !((value ^ data->asserted[offset]) & mask); } @@ -107,7 +106,7 @@ static const struct reset_control_ops jh71x0_reset_ops = { int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, void __iomem *assert, void __iomem *status, - const u64 *asserted, unsigned int nr_resets, + const u32 *asserted, unsigned int nr_resets, struct module *owner) { struct jh71x0_reset *data; diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h index ac9e80dd3f59..db7d39a87f87 100644 --- a/drivers/reset/starfive/reset-starfive-jh71x0.h +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h @@ -8,7 +8,7 @@ int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, void __iomem *assert, void __iomem *status, - const u64 *asserted, unsigned int nr_resets, + const u32 *asserted, unsigned int nr_resets, struct module *owner); #endif /* __RESET_STARFIVE_JH71X0_H */ -- 2.38.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-02-21 2:47 UTC|newest] Thread overview: 143+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 01/19] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 04/19] reset: Create subdirectory for StarFive drivers Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:10 ` Conor Dooley 2023-02-21 17:10 ` Conor Dooley 2023-02-21 2:46 ` [PATCH v4 06/19] reset: starfive: Extract the " Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:13 ` Conor Dooley 2023-02-21 17:13 ` Conor Dooley 2023-02-21 2:46 ` [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:17 ` Conor Dooley 2023-02-21 17:17 ` Conor Dooley 2023-02-21 2:46 ` Hal Feng [this message] 2023-02-21 2:46 ` [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng 2023-02-21 2:46 ` [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:23 ` Conor Dooley 2023-02-21 17:23 ` Conor Dooley 2023-02-23 3:40 ` Hal Feng 2023-02-23 3:40 ` Hal Feng 2023-02-22 9:13 ` Krzysztof Kozlowski 2023-02-22 9:13 ` Krzysztof Kozlowski 2023-02-22 10:40 ` Conor Dooley 2023-02-22 10:40 ` Conor Dooley 2023-02-23 10:22 ` Hal Feng 2023-02-23 10:22 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:26 ` Conor Dooley 2023-02-21 17:26 ` Conor Dooley 2023-02-23 5:52 ` Hal Feng 2023-02-23 5:52 ` Hal Feng 2023-03-09 14:22 ` Geert Uytterhoeven 2023-03-09 14:22 ` Geert Uytterhoeven 2023-03-13 2:29 ` Hal Feng 2023-03-13 2:29 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 15:12 ` Conor Dooley 2023-02-21 15:12 ` Conor Dooley 2023-02-23 6:17 ` Hal Feng 2023-02-23 6:17 ` Hal Feng 2023-02-26 16:07 ` Emil Renner Berthing 2023-02-26 16:07 ` Emil Renner Berthing 2023-02-28 2:30 ` Hal Feng 2023-02-28 2:30 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on " Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-26 17:34 ` Emil Renner Berthing 2023-02-26 17:34 ` Emil Renner Berthing 2023-02-28 2:42 ` Hal Feng 2023-02-28 2:42 ` Hal Feng 2023-03-09 9:43 ` Hal Feng 2023-03-09 9:43 ` Hal Feng 2023-03-09 14:06 ` Emil Renner Berthing 2023-03-09 14:06 ` Emil Renner Berthing 2023-03-09 18:11 ` Conor Dooley 2023-03-09 18:11 ` Conor Dooley 2023-03-09 18:19 ` Emil Renner Berthing 2023-03-09 18:19 ` Emil Renner Berthing 2023-03-09 19:32 ` Palmer Dabbelt 2023-03-09 19:32 ` Palmer Dabbelt 2023-02-21 2:46 ` [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 15:33 ` Emil Renner Berthing 2023-02-21 15:33 ` Emil Renner Berthing 2023-02-21 16:34 ` Conor Dooley 2023-02-21 16:34 ` Conor Dooley 2023-02-23 6:48 ` Hal Feng 2023-02-23 6:48 ` Hal Feng 2023-02-23 6:29 ` Hal Feng 2023-02-23 6:29 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 14/19] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 11:38 ` Krzysztof Kozlowski 2023-02-21 11:38 ` Krzysztof Kozlowski 2023-02-21 15:10 ` Conor Dooley 2023-02-21 15:10 ` Conor Dooley 2023-02-21 2:46 ` [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:03 ` Conor Dooley 2023-02-21 17:03 ` Conor Dooley 2023-02-23 7:16 ` Hal Feng 2023-02-23 7:16 ` Hal Feng 2023-02-27 18:10 ` Conor Dooley 2023-02-27 18:10 ` Conor Dooley 2023-02-21 2:46 ` [PATCH v4 18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 15:03 ` Emil Renner Berthing 2023-02-21 15:03 ` Emil Renner Berthing 2023-02-23 8:50 ` Hal Feng 2023-02-23 8:50 ` Hal Feng 2023-02-27 18:12 ` Conor Dooley 2023-02-27 18:12 ` Conor Dooley 2023-02-27 20:00 ` Conor Dooley 2023-02-27 20:00 ` Conor Dooley 2023-02-28 2:58 ` Hal Feng 2023-02-28 2:58 ` Hal Feng 2023-02-22 15:00 ` [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC patchwork-bot+linux-riscv 2023-02-22 15:00 ` patchwork-bot+linux-riscv 2023-02-22 15:35 ` Conor Dooley 2023-03-03 19:08 ` Tommaso Merciai 2023-03-03 19:08 ` Tommaso Merciai 2023-03-06 3:29 ` Hal Feng 2023-03-06 3:29 ` Hal Feng 2023-03-06 10:22 ` Tommaso Merciai 2023-03-06 10:22 ` Tommaso Merciai 2023-03-07 8:36 ` Hal Feng 2023-03-07 8:36 ` Hal Feng 2023-03-07 8:51 ` Conor Dooley 2023-03-07 8:51 ` Conor Dooley 2023-03-07 10:08 ` Hal Feng 2023-03-07 10:08 ` Hal Feng 2023-03-08 12:28 ` Tommaso Merciai 2023-03-08 12:28 ` Tommaso Merciai 2023-03-08 13:36 ` Conor Dooley 2023-03-08 13:36 ` Conor Dooley 2023-03-09 16:49 ` Tommaso Merciai 2023-03-09 16:49 ` Tommaso Merciai 2023-03-09 17:52 ` Conor Dooley 2023-03-09 17:52 ` Conor Dooley 2023-03-09 18:58 ` Tommaso Merciai 2023-03-09 18:58 ` Tommaso Merciai 2023-03-09 19:03 ` Conor Dooley 2023-03-09 19:03 ` Conor Dooley 2023-03-10 7:48 ` Tommaso Merciai 2023-03-10 7:48 ` Tommaso Merciai
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