From: Hal Feng <hal.feng@starfivetech.com> To: Conor Dooley <conor@kernel.org> Cc: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>, Stephen Boyd <sboyd@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, "Emil Renner Berthing" <emil.renner.berthing@canonical.com>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Date: Thu, 23 Feb 2023 11:40:40 +0800 [thread overview] Message-ID: <25c01857-8f59-02ed-062d-a5e619258204@starfivetech.com> (raw) In-Reply-To: <Y/T+GNQAXLGyUtCH@spud> On Tue, 21 Feb 2023 17:23:36 +0000, Conor Dooley wrote: > Hey Hal, > > On Tue, Feb 21, 2023 at 10:46:35AM +0800, Hal Feng wrote: >> From: Emil Renner Berthing <kernel@esmil.dk> >> >> Add bindings for the system clock and reset generator (SYSCRG) on the >> JH7110 RISC-V SoC by StarFive Ltd. >> >> Reviewed-by: Rob Herring <robh@kernel.org> >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > >> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> new file mode 100644 >> index 000000000000..ec81504dcb27 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> @@ -0,0 +1,80 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive JH7110 System Clock and Reset Generator >> + >> +maintainers: >> + - Emil Renner Berthing <kernel@esmil.dk> >> + >> +properties: >> + compatible: >> + const: starfive,jh7110-syscrg >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Main Oscillator (24 MHz) >> + - description: GMAC1 RMII reference >> + - description: GMAC1 RGMII RX >> + - description: External I2S TX bit clock >> + - description: External I2S TX left/right channel clock >> + - description: External I2S RX bit clock >> + - description: External I2S RX left/right channel clock >> + - description: External TDM clock >> + - description: External audio master clock > > You didn't reply to the conversation I had with Krzysztof about how to > represent the optional nature of some of these clocks, contained in this > thread here: > https://lore.kernel.org/all/7a7bccb1-4d47-3d32-36e6-4aab7b5b8dad@starfivetech.com/ > > What happens to the gmac1 mux if only one of the input clocks is > provided? > And I mean what does the hardware do, not the software representation of > that mux in the driver. In hardware, just providing the required input clocks is enough. Refer to the following link for the required clocks. Thanks. https://lore.kernel.org/all/c0472d7f-56fe-3e91-e0a0-49ee51700b5d@starfivetech.com/ Best regards, Hal > >> + >> + clock-names: >> + items: >> + - const: osc >> + - const: gmac1_rmii_refin >> + - const: gmac1_rgmii_rxin >> + - const: i2stx_bclk_ext >> + - const: i2stx_lrck_ext >> + - const: i2srx_bclk_ext >> + - const: i2srx_lrck_ext >> + - const: tdm_ext >> + - const: mclk_ext
WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@starfivetech.com> To: Conor Dooley <conor@kernel.org> Cc: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>, Stephen Boyd <sboyd@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, "Emil Renner Berthing" <emil.renner.berthing@canonical.com>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Date: Thu, 23 Feb 2023 11:40:40 +0800 [thread overview] Message-ID: <25c01857-8f59-02ed-062d-a5e619258204@starfivetech.com> (raw) In-Reply-To: <Y/T+GNQAXLGyUtCH@spud> On Tue, 21 Feb 2023 17:23:36 +0000, Conor Dooley wrote: > Hey Hal, > > On Tue, Feb 21, 2023 at 10:46:35AM +0800, Hal Feng wrote: >> From: Emil Renner Berthing <kernel@esmil.dk> >> >> Add bindings for the system clock and reset generator (SYSCRG) on the >> JH7110 RISC-V SoC by StarFive Ltd. >> >> Reviewed-by: Rob Herring <robh@kernel.org> >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > >> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> new file mode 100644 >> index 000000000000..ec81504dcb27 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> @@ -0,0 +1,80 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive JH7110 System Clock and Reset Generator >> + >> +maintainers: >> + - Emil Renner Berthing <kernel@esmil.dk> >> + >> +properties: >> + compatible: >> + const: starfive,jh7110-syscrg >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Main Oscillator (24 MHz) >> + - description: GMAC1 RMII reference >> + - description: GMAC1 RGMII RX >> + - description: External I2S TX bit clock >> + - description: External I2S TX left/right channel clock >> + - description: External I2S RX bit clock >> + - description: External I2S RX left/right channel clock >> + - description: External TDM clock >> + - description: External audio master clock > > You didn't reply to the conversation I had with Krzysztof about how to > represent the optional nature of some of these clocks, contained in this > thread here: > https://lore.kernel.org/all/7a7bccb1-4d47-3d32-36e6-4aab7b5b8dad@starfivetech.com/ > > What happens to the gmac1 mux if only one of the input clocks is > provided? > And I mean what does the hardware do, not the software representation of > that mux in the driver. In hardware, just providing the required input clocks is enough. Refer to the following link for the required clocks. Thanks. https://lore.kernel.org/all/c0472d7f-56fe-3e91-e0a0-49ee51700b5d@starfivetech.com/ Best regards, Hal > >> + >> + clock-names: >> + items: >> + - const: osc >> + - const: gmac1_rmii_refin >> + - const: gmac1_rgmii_rxin >> + - const: i2stx_bclk_ext >> + - const: i2stx_lrck_ext >> + - const: i2srx_bclk_ext >> + - const: i2srx_lrck_ext >> + - const: tdm_ext >> + - const: mclk_ext _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-02-23 3:41 UTC|newest] Thread overview: 143+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 01/19] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 04/19] reset: Create subdirectory for StarFive drivers Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:10 ` Conor Dooley 2023-02-21 17:10 ` Conor Dooley 2023-02-21 2:46 ` [PATCH v4 06/19] reset: starfive: Extract the " Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:13 ` Conor Dooley 2023-02-21 17:13 ` Conor Dooley 2023-02-21 2:46 ` [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:17 ` Conor Dooley 2023-02-21 17:17 ` Conor Dooley 2023-02-21 2:46 ` [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:23 ` Conor Dooley 2023-02-21 17:23 ` Conor Dooley 2023-02-23 3:40 ` Hal Feng [this message] 2023-02-23 3:40 ` Hal Feng 2023-02-22 9:13 ` Krzysztof Kozlowski 2023-02-22 9:13 ` Krzysztof Kozlowski 2023-02-22 10:40 ` Conor Dooley 2023-02-22 10:40 ` Conor Dooley 2023-02-23 10:22 ` Hal Feng 2023-02-23 10:22 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:26 ` Conor Dooley 2023-02-21 17:26 ` Conor Dooley 2023-02-23 5:52 ` Hal Feng 2023-02-23 5:52 ` Hal Feng 2023-03-09 14:22 ` Geert Uytterhoeven 2023-03-09 14:22 ` Geert Uytterhoeven 2023-03-13 2:29 ` Hal Feng 2023-03-13 2:29 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 15:12 ` Conor Dooley 2023-02-21 15:12 ` Conor Dooley 2023-02-23 6:17 ` Hal Feng 2023-02-23 6:17 ` Hal Feng 2023-02-26 16:07 ` Emil Renner Berthing 2023-02-26 16:07 ` Emil Renner Berthing 2023-02-28 2:30 ` Hal Feng 2023-02-28 2:30 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on " Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-26 17:34 ` Emil Renner Berthing 2023-02-26 17:34 ` Emil Renner Berthing 2023-02-28 2:42 ` Hal Feng 2023-02-28 2:42 ` Hal Feng 2023-03-09 9:43 ` Hal Feng 2023-03-09 9:43 ` Hal Feng 2023-03-09 14:06 ` Emil Renner Berthing 2023-03-09 14:06 ` Emil Renner Berthing 2023-03-09 18:11 ` Conor Dooley 2023-03-09 18:11 ` Conor Dooley 2023-03-09 18:19 ` Emil Renner Berthing 2023-03-09 18:19 ` Emil Renner Berthing 2023-03-09 19:32 ` Palmer Dabbelt 2023-03-09 19:32 ` Palmer Dabbelt 2023-02-21 2:46 ` [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 15:33 ` Emil Renner Berthing 2023-02-21 15:33 ` Emil Renner Berthing 2023-02-21 16:34 ` Conor Dooley 2023-02-21 16:34 ` Conor Dooley 2023-02-23 6:48 ` Hal Feng 2023-02-23 6:48 ` Hal Feng 2023-02-23 6:29 ` Hal Feng 2023-02-23 6:29 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 14/19] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 11:38 ` Krzysztof Kozlowski 2023-02-21 11:38 ` Krzysztof Kozlowski 2023-02-21 15:10 ` Conor Dooley 2023-02-21 15:10 ` Conor Dooley 2023-02-21 2:46 ` [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 17:03 ` Conor Dooley 2023-02-21 17:03 ` Conor Dooley 2023-02-23 7:16 ` Hal Feng 2023-02-23 7:16 ` Hal Feng 2023-02-27 18:10 ` Conor Dooley 2023-02-27 18:10 ` Conor Dooley 2023-02-21 2:46 ` [PATCH v4 18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 2:46 ` [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng 2023-02-21 2:46 ` Hal Feng 2023-02-21 15:03 ` Emil Renner Berthing 2023-02-21 15:03 ` Emil Renner Berthing 2023-02-23 8:50 ` Hal Feng 2023-02-23 8:50 ` Hal Feng 2023-02-27 18:12 ` Conor Dooley 2023-02-27 18:12 ` Conor Dooley 2023-02-27 20:00 ` Conor Dooley 2023-02-27 20:00 ` Conor Dooley 2023-02-28 2:58 ` Hal Feng 2023-02-28 2:58 ` Hal Feng 2023-02-22 15:00 ` [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC patchwork-bot+linux-riscv 2023-02-22 15:00 ` patchwork-bot+linux-riscv 2023-02-22 15:35 ` Conor Dooley 2023-03-03 19:08 ` Tommaso Merciai 2023-03-03 19:08 ` Tommaso Merciai 2023-03-06 3:29 ` Hal Feng 2023-03-06 3:29 ` Hal Feng 2023-03-06 10:22 ` Tommaso Merciai 2023-03-06 10:22 ` Tommaso Merciai 2023-03-07 8:36 ` Hal Feng 2023-03-07 8:36 ` Hal Feng 2023-03-07 8:51 ` Conor Dooley 2023-03-07 8:51 ` Conor Dooley 2023-03-07 10:08 ` Hal Feng 2023-03-07 10:08 ` Hal Feng 2023-03-08 12:28 ` Tommaso Merciai 2023-03-08 12:28 ` Tommaso Merciai 2023-03-08 13:36 ` Conor Dooley 2023-03-08 13:36 ` Conor Dooley 2023-03-09 16:49 ` Tommaso Merciai 2023-03-09 16:49 ` Tommaso Merciai 2023-03-09 17:52 ` Conor Dooley 2023-03-09 17:52 ` Conor Dooley 2023-03-09 18:58 ` Tommaso Merciai 2023-03-09 18:58 ` Tommaso Merciai 2023-03-09 19:03 ` Conor Dooley 2023-03-09 19:03 ` Conor Dooley 2023-03-10 7:48 ` Tommaso Merciai 2023-03-10 7:48 ` Tommaso Merciai
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