From: <Conor.Dooley@microchip.com> To: <prabhakar.mahadev-lad.rj@bp.renesas.com>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <geert+renesas@glider.be> Cc: <anup@brainfault.org>, <linux-renesas-soc@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <prabhakar.csengg@gmail.com>, <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Date: Mon, 15 Aug 2022 19:00:05 +0000 [thread overview] Message-ID: <07342070-d96c-59fc-f9dd-b65cd742d97a@microchip.com> (raw) In-Reply-To: <20220815151451.23293-7-prabhakar.mahadev-lad.rj@bp.renesas.com> On 15/08/2022 16:14, Lad Prabhakar wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Enable the minimal blocks required for booting the Renesas RZ/Five > SMARC EVK with initramfs. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v1->v2 > * New patch > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/renesas/Makefile | 2 ++ > .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 ++++++++++ > .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 +++++++++++++ > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++ > 5 files changed, 73 insertions(+) > create mode 100644 arch/riscv/boot/dts/renesas/Makefile > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi Just to sort out some of my own confusion here - is the smarc EVK shared between your arm boards and the riscv ones? Or just the peripherals etc on the soc? If it is the forver, does the approach suggested here for the allwinner stuff make sense to also use for risc-v stuff with shared parts of devicetrees? https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/ Would at least be interesting in hearing more opinions from the dt people, Geert & Palmer. We have some SOM based stuff too with carriers so I am interested in seeing how the cross platform part of that works out. Thanks, Conor. > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..b0ff5fbabb0c 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -3,5 +3,6 @@ subdir-y += sifive > subdir-y += starfive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > subdir-y += microchip > +subdir-y += renesas > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile > new file mode 100644 > index 000000000000..2d3f5751a649 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > new file mode 100644 > index 000000000000..7428f643a9b3 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > @@ -0,0 +1,16 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SMARC EVK > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +/dts-v1/; > + > +#include "r9a07g043.dtsi" > +#include "rzfive-smarc.dtsi" > + > +/ { > + model = "Renesas SMARC EVK based on r9a07g043f01"; > + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043"; > +}; > diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > new file mode 100644 > index 000000000000..4a4acde6a2a7 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SMARC EVK SOM > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +/ { > + chosen { > + bootargs = "ignore_loglevel"; > + }; > + > + memory@48000000 { > + device_type = "memory"; > + /* first 128MB is reserved for secure area. */ > + reg = <0x0 0x48000000 0x0 0x38000000>; > + }; > +}; > + > +&extal_clk { > + clock-frequency = <24000000>; > +}; > diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi > new file mode 100644 > index 000000000000..4864a2a62d6b > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi > @@ -0,0 +1,32 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SMARC EVK carrier board > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > +#include "rzfive-smarc-som.dtsi" > + > +/ { > + aliases { > + serial0 = &scif0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&pinctrl { > + scif0_pins: scif0 { > + pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */ > + <RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */ > + }; > +}; > + > +&scif0 { > + pinctrl-0 = <&scif0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > -- > 2.25.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com> To: <prabhakar.mahadev-lad.rj@bp.renesas.com>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <geert+renesas@glider.be> Cc: <anup@brainfault.org>, <linux-renesas-soc@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <prabhakar.csengg@gmail.com>, <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Date: Mon, 15 Aug 2022 19:00:05 +0000 [thread overview] Message-ID: <07342070-d96c-59fc-f9dd-b65cd742d97a@microchip.com> (raw) In-Reply-To: <20220815151451.23293-7-prabhakar.mahadev-lad.rj@bp.renesas.com> On 15/08/2022 16:14, Lad Prabhakar wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Enable the minimal blocks required for booting the Renesas RZ/Five > SMARC EVK with initramfs. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v1->v2 > * New patch > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/renesas/Makefile | 2 ++ > .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 ++++++++++ > .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 +++++++++++++ > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++ > 5 files changed, 73 insertions(+) > create mode 100644 arch/riscv/boot/dts/renesas/Makefile > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi Just to sort out some of my own confusion here - is the smarc EVK shared between your arm boards and the riscv ones? Or just the peripherals etc on the soc? If it is the forver, does the approach suggested here for the allwinner stuff make sense to also use for risc-v stuff with shared parts of devicetrees? https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/ Would at least be interesting in hearing more opinions from the dt people, Geert & Palmer. We have some SOM based stuff too with carriers so I am interested in seeing how the cross platform part of that works out. Thanks, Conor. > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..b0ff5fbabb0c 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -3,5 +3,6 @@ subdir-y += sifive > subdir-y += starfive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > subdir-y += microchip > +subdir-y += renesas > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile > new file mode 100644 > index 000000000000..2d3f5751a649 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > new file mode 100644 > index 000000000000..7428f643a9b3 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > @@ -0,0 +1,16 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SMARC EVK > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +/dts-v1/; > + > +#include "r9a07g043.dtsi" > +#include "rzfive-smarc.dtsi" > + > +/ { > + model = "Renesas SMARC EVK based on r9a07g043f01"; > + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043"; > +}; > diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > new file mode 100644 > index 000000000000..4a4acde6a2a7 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SMARC EVK SOM > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +/ { > + chosen { > + bootargs = "ignore_loglevel"; > + }; > + > + memory@48000000 { > + device_type = "memory"; > + /* first 128MB is reserved for secure area. */ > + reg = <0x0 0x48000000 0x0 0x38000000>; > + }; > +}; > + > +&extal_clk { > + clock-frequency = <24000000>; > +}; > diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi > new file mode 100644 > index 000000000000..4864a2a62d6b > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi > @@ -0,0 +1,32 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SMARC EVK carrier board > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > +#include "rzfive-smarc-som.dtsi" > + > +/ { > + aliases { > + serial0 = &scif0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&pinctrl { > + scif0_pins: scif0 { > + pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */ > + <RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */ > + }; > +}; > + > +&scif0 { > + pinctrl-0 = <&scif0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > -- > 2.25.1 >
next prev parent reply other threads:[~2022-08-15 19:01 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-15 15:14 [PATCH v2 0/8] Add support for Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 15:14 ` [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:11 ` Conor.Dooley 2022-08-15 19:11 ` Conor.Dooley 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-18 14:55 ` Geert Uytterhoeven 2022-08-18 14:55 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:14 ` Conor.Dooley 2022-08-15 19:14 ` Conor.Dooley 2022-08-15 19:40 ` Lad, Prabhakar 2022-08-15 19:40 ` Lad, Prabhakar 2022-08-15 19:42 ` Conor.Dooley 2022-08-15 19:42 ` Conor.Dooley 2022-08-16 7:52 ` Krzysztof Kozlowski 2022-08-16 7:52 ` Krzysztof Kozlowski 2022-08-18 15:00 ` Geert Uytterhoeven 2022-08-18 15:00 ` Geert Uytterhoeven 2022-08-18 18:14 ` Lad, Prabhakar 2022-08-18 18:14 ` Lad, Prabhakar 2022-08-15 15:14 ` [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:10 ` Conor.Dooley 2022-08-15 19:10 ` Conor.Dooley 2022-08-15 19:57 ` Lad, Prabhakar 2022-08-15 19:57 ` Lad, Prabhakar 2022-08-15 20:05 ` Conor.Dooley 2022-08-15 20:05 ` Conor.Dooley 2022-08-15 21:44 ` Lad, Prabhakar 2022-08-15 21:44 ` Lad, Prabhakar 2022-08-18 15:16 ` Geert Uytterhoeven 2022-08-18 15:16 ` Geert Uytterhoeven 2022-08-18 18:19 ` Lad, Prabhakar 2022-08-18 18:19 ` Lad, Prabhakar 2022-08-18 18:53 ` Conor.Dooley 2022-08-18 18:53 ` Conor.Dooley 2022-08-19 7:35 ` Geert Uytterhoeven 2022-08-19 7:35 ` Geert Uytterhoeven 2022-08-19 7:59 ` Conor.Dooley 2022-08-19 7:59 ` Conor.Dooley 2022-08-15 15:14 ` [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-19 8:04 ` Geert Uytterhoeven 2022-08-19 8:04 ` Geert Uytterhoeven 2022-08-19 11:42 ` Lad, Prabhakar 2022-08-19 11:42 ` Lad, Prabhakar 2022-08-19 18:40 ` Conor.Dooley 2022-08-19 18:40 ` Conor.Dooley 2022-08-20 8:45 ` Geert Uytterhoeven 2022-08-20 8:45 ` Geert Uytterhoeven 2022-08-20 8:49 ` Conor.Dooley 2022-08-20 8:49 ` Conor.Dooley 2022-08-20 12:07 ` Geert Uytterhoeven 2022-08-20 12:07 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:00 ` Conor.Dooley [this message] 2022-08-15 19:00 ` Conor.Dooley 2022-08-15 20:16 ` Lad, Prabhakar 2022-08-15 20:16 ` Lad, Prabhakar 2022-08-19 8:25 ` Geert Uytterhoeven 2022-08-19 8:25 ` Geert Uytterhoeven 2022-08-19 11:39 ` Lad, Prabhakar 2022-08-19 11:39 ` Lad, Prabhakar 2022-08-19 18:15 ` Conor.Dooley 2022-08-19 18:15 ` Conor.Dooley 2022-08-19 8:11 ` Geert Uytterhoeven 2022-08-19 8:11 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-19 8:42 ` Geert Uytterhoeven 2022-08-19 8:42 ` Geert Uytterhoeven 2022-08-19 9:08 ` Lad, Prabhakar 2022-08-19 9:08 ` Lad, Prabhakar 2022-08-15 15:14 ` [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 18:52 ` Conor.Dooley 2022-08-15 18:52 ` Conor.Dooley 2022-08-15 19:44 ` Lad, Prabhakar 2022-08-15 19:44 ` Lad, Prabhakar 2022-08-15 19:49 ` Conor.Dooley 2022-08-15 19:49 ` Conor.Dooley 2022-08-19 8:46 ` Geert Uytterhoeven 2022-08-19 8:46 ` Geert Uytterhoeven
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