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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Conor Dooley <Conor.Dooley@microchip.com>,
	Anup Patel <anup@brainfault.org>,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically
Date: Mon, 15 Aug 2022 16:14:44 +0100	[thread overview]
Message-ID: <20220815151451.23293-2-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

Sort the CPU cores list alphabetically for maintenance.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v1->v2
* Included RB tag from Krzysztof
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 873dd12f6e89..2a1c5ae5b0aa 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,17 +27,17 @@ properties:
     oneOf:
       - items:
           - enum:
-              - sifive,rocket0
+              - canaan,k210
               - sifive,bullet0
               - sifive,e5
               - sifive,e7
               - sifive,e71
-              - sifive,u74-mc
-              - sifive,u54
-              - sifive,u74
+              - sifive,rocket0
               - sifive,u5
+              - sifive,u54
               - sifive,u7
-              - canaan,k210
+              - sifive,u74
+              - sifive,u74-mc
           - const: riscv
       - items:
           - enum:
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Conor Dooley <Conor.Dooley@microchip.com>,
	Anup Patel <anup@brainfault.org>,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically
Date: Mon, 15 Aug 2022 16:14:44 +0100	[thread overview]
Message-ID: <20220815151451.23293-2-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

Sort the CPU cores list alphabetically for maintenance.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v1->v2
* Included RB tag from Krzysztof
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 873dd12f6e89..2a1c5ae5b0aa 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,17 +27,17 @@ properties:
     oneOf:
       - items:
           - enum:
-              - sifive,rocket0
+              - canaan,k210
               - sifive,bullet0
               - sifive,e5
               - sifive,e7
               - sifive,e71
-              - sifive,u74-mc
-              - sifive,u54
-              - sifive,u74
+              - sifive,rocket0
               - sifive,u5
+              - sifive,u54
               - sifive,u7
-              - canaan,k210
+              - sifive,u74
+              - sifive,u74-mc
           - const: riscv
       - items:
           - enum:
-- 
2.25.1


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  reply	other threads:[~2022-08-15 15:16 UTC|newest]

Thread overview: 92+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-15 15:14 [PATCH v2 0/8] Add support for Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 15:14 ` Lad Prabhakar
2022-08-15 15:14 ` Lad Prabhakar [this message]
2022-08-15 15:14   ` [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2022-08-15 19:11   ` Conor.Dooley
2022-08-15 19:11     ` Conor.Dooley
2022-08-18 13:00   ` Geert Uytterhoeven
2022-08-18 13:00     ` Geert Uytterhoeven
2022-08-18 13:00   ` Geert Uytterhoeven
2022-08-18 13:00     ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-18 14:55   ` Geert Uytterhoeven
2022-08-18 14:55     ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-15 19:14   ` Conor.Dooley
2022-08-15 19:14     ` Conor.Dooley
2022-08-15 19:40     ` Lad, Prabhakar
2022-08-15 19:40       ` Lad, Prabhakar
2022-08-15 19:42       ` Conor.Dooley
2022-08-15 19:42         ` Conor.Dooley
2022-08-16  7:52   ` Krzysztof Kozlowski
2022-08-16  7:52     ` Krzysztof Kozlowski
2022-08-18 15:00   ` Geert Uytterhoeven
2022-08-18 15:00     ` Geert Uytterhoeven
2022-08-18 18:14     ` Lad, Prabhakar
2022-08-18 18:14       ` Lad, Prabhakar
2022-08-15 15:14 ` [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-15 19:10   ` Conor.Dooley
2022-08-15 19:10     ` Conor.Dooley
2022-08-15 19:57     ` Lad, Prabhakar
2022-08-15 19:57       ` Lad, Prabhakar
2022-08-15 20:05       ` Conor.Dooley
2022-08-15 20:05         ` Conor.Dooley
2022-08-15 21:44         ` Lad, Prabhakar
2022-08-15 21:44           ` Lad, Prabhakar
2022-08-18 15:16   ` Geert Uytterhoeven
2022-08-18 15:16     ` Geert Uytterhoeven
2022-08-18 18:19     ` Lad, Prabhakar
2022-08-18 18:19       ` Lad, Prabhakar
2022-08-18 18:53       ` Conor.Dooley
2022-08-18 18:53         ` Conor.Dooley
2022-08-19  7:35         ` Geert Uytterhoeven
2022-08-19  7:35           ` Geert Uytterhoeven
2022-08-19  7:59           ` Conor.Dooley
2022-08-19  7:59             ` Conor.Dooley
2022-08-15 15:14 ` [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-19  8:04   ` Geert Uytterhoeven
2022-08-19  8:04     ` Geert Uytterhoeven
2022-08-19 11:42     ` Lad, Prabhakar
2022-08-19 11:42       ` Lad, Prabhakar
2022-08-19 18:40   ` Conor.Dooley
2022-08-19 18:40     ` Conor.Dooley
2022-08-20  8:45     ` Geert Uytterhoeven
2022-08-20  8:45       ` Geert Uytterhoeven
2022-08-20  8:49       ` Conor.Dooley
2022-08-20  8:49         ` Conor.Dooley
2022-08-20 12:07         ` Geert Uytterhoeven
2022-08-20 12:07           ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-15 19:00   ` Conor.Dooley
2022-08-15 19:00     ` Conor.Dooley
2022-08-15 20:16     ` Lad, Prabhakar
2022-08-15 20:16       ` Lad, Prabhakar
2022-08-19  8:25       ` Geert Uytterhoeven
2022-08-19  8:25         ` Geert Uytterhoeven
2022-08-19 11:39         ` Lad, Prabhakar
2022-08-19 11:39           ` Lad, Prabhakar
2022-08-19 18:15           ` Conor.Dooley
2022-08-19 18:15             ` Conor.Dooley
2022-08-19  8:11   ` Geert Uytterhoeven
2022-08-19  8:11     ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-19  8:42   ` Geert Uytterhoeven
2022-08-19  8:42     ` Geert Uytterhoeven
2022-08-19  9:08     ` Lad, Prabhakar
2022-08-19  9:08       ` Lad, Prabhakar
2022-08-15 15:14 ` [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-15 18:52   ` Conor.Dooley
2022-08-15 18:52     ` Conor.Dooley
2022-08-15 19:44     ` Lad, Prabhakar
2022-08-15 19:44       ` Lad, Prabhakar
2022-08-15 19:49       ` Conor.Dooley
2022-08-15 19:49         ` Conor.Dooley
2022-08-19  8:46   ` Geert Uytterhoeven
2022-08-19  8:46     ` Geert Uytterhoeven

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