From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Conor Dooley <Conor.Dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Date: Thu, 18 Aug 2022 19:14:49 +0100 [thread overview] Message-ID: <CA+V-a8tSWshjoEqq=bwsY8eMfTe_QkZ-Uv+c3QBvZtD0XXgA+g@mail.gmail.com> (raw) In-Reply-To: <CAMuHMdUaketBpEfoSKeSJ4SuYwOTLoqJ_FCp=G8HmVudhv3zWw@mail.gmail.com> Hi Geert, Thank you for the review. On Thu, Aug 18, 2022 at 4:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Document Renesas RZ/Five (R9A07G043) SoC. > > > > More info about RZ/Five SoC: > > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > > @@ -415,11 +415,12 @@ properties: > > - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) > > - const: renesas,r9a06g032 > > > > - - description: RZ/G2UL (R9A07G043) > > + - description: RZ/Five and RZ/G2UL (R9A07G043) > > items: > > - enum: > > - renesas,smarc-evk # SMARC EVK > > - enum: > > + - renesas,r9a07g043f01 # RZ/Five (RISC-V core) > > Should we be consistent, and leave out the "(RISC-V core)" comment, > or add it everywhere? > Rather leave it for now ;) . If Rob agrees on your suggestion on splitting (renesas,{rmobile,rcar-gen[1234],rza,rzg,rzn,...}.yaml that would make it cleaner. > Note that several of the SoCs listed in this file have SuperH or > RealTime ARM cores, so going for the former means a lot of work. > Agreed. Cheers, Prabhakar
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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Conor Dooley <Conor.Dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Date: Thu, 18 Aug 2022 19:14:49 +0100 [thread overview] Message-ID: <CA+V-a8tSWshjoEqq=bwsY8eMfTe_QkZ-Uv+c3QBvZtD0XXgA+g@mail.gmail.com> (raw) In-Reply-To: <CAMuHMdUaketBpEfoSKeSJ4SuYwOTLoqJ_FCp=G8HmVudhv3zWw@mail.gmail.com> Hi Geert, Thank you for the review. On Thu, Aug 18, 2022 at 4:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Document Renesas RZ/Five (R9A07G043) SoC. > > > > More info about RZ/Five SoC: > > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > > @@ -415,11 +415,12 @@ properties: > > - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) > > - const: renesas,r9a06g032 > > > > - - description: RZ/G2UL (R9A07G043) > > + - description: RZ/Five and RZ/G2UL (R9A07G043) > > items: > > - enum: > > - renesas,smarc-evk # SMARC EVK > > - enum: > > + - renesas,r9a07g043f01 # RZ/Five (RISC-V core) > > Should we be consistent, and leave out the "(RISC-V core)" comment, > or add it everywhere? > Rather leave it for now ;) . If Rob agrees on your suggestion on splitting (renesas,{rmobile,rcar-gen[1234],rza,rzg,rzn,...}.yaml that would make it cleaner. > Note that several of the SoCs listed in this file have SuperH or > RealTime ARM cores, so going for the former means a lot of work. > Agreed. Cheers, Prabhakar _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-08-18 18:15 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-15 15:14 [PATCH v2 0/8] Add support for Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 15:14 ` [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:11 ` Conor.Dooley 2022-08-15 19:11 ` Conor.Dooley 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-18 14:55 ` Geert Uytterhoeven 2022-08-18 14:55 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:14 ` Conor.Dooley 2022-08-15 19:14 ` Conor.Dooley 2022-08-15 19:40 ` Lad, Prabhakar 2022-08-15 19:40 ` Lad, Prabhakar 2022-08-15 19:42 ` Conor.Dooley 2022-08-15 19:42 ` Conor.Dooley 2022-08-16 7:52 ` Krzysztof Kozlowski 2022-08-16 7:52 ` Krzysztof Kozlowski 2022-08-18 15:00 ` Geert Uytterhoeven 2022-08-18 15:00 ` Geert Uytterhoeven 2022-08-18 18:14 ` Lad, Prabhakar [this message] 2022-08-18 18:14 ` Lad, Prabhakar 2022-08-15 15:14 ` [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:10 ` Conor.Dooley 2022-08-15 19:10 ` Conor.Dooley 2022-08-15 19:57 ` Lad, Prabhakar 2022-08-15 19:57 ` Lad, Prabhakar 2022-08-15 20:05 ` Conor.Dooley 2022-08-15 20:05 ` Conor.Dooley 2022-08-15 21:44 ` Lad, Prabhakar 2022-08-15 21:44 ` Lad, Prabhakar 2022-08-18 15:16 ` Geert Uytterhoeven 2022-08-18 15:16 ` Geert Uytterhoeven 2022-08-18 18:19 ` Lad, Prabhakar 2022-08-18 18:19 ` Lad, Prabhakar 2022-08-18 18:53 ` Conor.Dooley 2022-08-18 18:53 ` Conor.Dooley 2022-08-19 7:35 ` Geert Uytterhoeven 2022-08-19 7:35 ` Geert Uytterhoeven 2022-08-19 7:59 ` Conor.Dooley 2022-08-19 7:59 ` Conor.Dooley 2022-08-15 15:14 ` [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-19 8:04 ` Geert Uytterhoeven 2022-08-19 8:04 ` Geert Uytterhoeven 2022-08-19 11:42 ` Lad, Prabhakar 2022-08-19 11:42 ` Lad, Prabhakar 2022-08-19 18:40 ` Conor.Dooley 2022-08-19 18:40 ` Conor.Dooley 2022-08-20 8:45 ` Geert Uytterhoeven 2022-08-20 8:45 ` Geert Uytterhoeven 2022-08-20 8:49 ` Conor.Dooley 2022-08-20 8:49 ` Conor.Dooley 2022-08-20 12:07 ` Geert Uytterhoeven 2022-08-20 12:07 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:00 ` Conor.Dooley 2022-08-15 19:00 ` Conor.Dooley 2022-08-15 20:16 ` Lad, Prabhakar 2022-08-15 20:16 ` Lad, Prabhakar 2022-08-19 8:25 ` Geert Uytterhoeven 2022-08-19 8:25 ` Geert Uytterhoeven 2022-08-19 11:39 ` Lad, Prabhakar 2022-08-19 11:39 ` Lad, Prabhakar 2022-08-19 18:15 ` Conor.Dooley 2022-08-19 18:15 ` Conor.Dooley 2022-08-19 8:11 ` Geert Uytterhoeven 2022-08-19 8:11 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-19 8:42 ` Geert Uytterhoeven 2022-08-19 8:42 ` Geert Uytterhoeven 2022-08-19 9:08 ` Lad, Prabhakar 2022-08-19 9:08 ` Lad, Prabhakar 2022-08-15 15:14 ` [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 18:52 ` Conor.Dooley 2022-08-15 18:52 ` Conor.Dooley 2022-08-15 19:44 ` Lad, Prabhakar 2022-08-15 19:44 ` Lad, Prabhakar 2022-08-15 19:49 ` Conor.Dooley 2022-08-15 19:49 ` Conor.Dooley 2022-08-19 8:46 ` Geert Uytterhoeven 2022-08-19 8:46 ` Geert Uytterhoeven
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