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From: <Conor.Dooley@microchip.com>
To: <prabhakar.mahadev-lad.rj@bp.renesas.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<geert+renesas@glider.be>
Cc: <anup@brainfault.org>, <linux-renesas-soc@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <prabhakar.csengg@gmail.com>,
	<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
Date: Mon, 15 Aug 2022 19:10:04 +0000	[thread overview]
Message-ID: <d9d0deef-92e1-05b4-a195-d2ca03801129@microchip.com> (raw)
In-Reply-To: <20220815151451.23293-5-prabhakar.mahadev-lad.rj@bp.renesas.com>

On 15/08/2022 16:14, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> of the Renesas drivers depend on this config option.

Hey Lad,

I think I said something similar on v1, but I said it again
to Samuel today so I may as well repost here too:
"I think this and patch 12/12 with the defconfig changes should be
deferred until post LPC (which still leaves plenty of time for
making the 6.1 merge window). We already have like 4 different
approaches between the existing SOC_FOO symbols & two more when
D1 stuff and the Renesas stuff is considered.

Plan is to decide at LPC on one approach for what to do with
Kconfig.socs & to me it seems like a good idea to do what's being
done here - it's likely that further arm vendors will move and
keeping the common symbols makes a lot of sense to me..."

Also, for the sake of my OCD could you pick either riscv or
RISC-V and use it for the whole series? Pedantic I guess, but
/shrug

Thanks,
Conor.

> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * No Change
> ---
>  arch/riscv/Kconfig.socs | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..91b7f38b77a8 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
> 
>  endif # SOC_CANAAN
> 
> +config ARCH_RENESAS
> +       bool
> +       select GPIOLIB
> +       select PINCTRL
> +       select SOC_BUS
> +
> +config SOC_RENESAS_RZFIVE
> +       bool "Renesas RZ/Five SoC"
> +       select ARCH_R9A07G043
> +       select ARCH_RENESAS
> +       select RESET_CONTROLLER
> +       help
> +         This enables support for Renesas RZ/Five SoC.
> +
>  endmenu # "SoC selection"
> --
> 2.25.1
> 

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com>
To: <prabhakar.mahadev-lad.rj@bp.renesas.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<geert+renesas@glider.be>
Cc: <anup@brainfault.org>, <linux-renesas-soc@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <prabhakar.csengg@gmail.com>,
	<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
Date: Mon, 15 Aug 2022 19:10:04 +0000	[thread overview]
Message-ID: <d9d0deef-92e1-05b4-a195-d2ca03801129@microchip.com> (raw)
In-Reply-To: <20220815151451.23293-5-prabhakar.mahadev-lad.rj@bp.renesas.com>

On 15/08/2022 16:14, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> of the Renesas drivers depend on this config option.

Hey Lad,

I think I said something similar on v1, but I said it again
to Samuel today so I may as well repost here too:
"I think this and patch 12/12 with the defconfig changes should be
deferred until post LPC (which still leaves plenty of time for
making the 6.1 merge window). We already have like 4 different
approaches between the existing SOC_FOO symbols & two more when
D1 stuff and the Renesas stuff is considered.

Plan is to decide at LPC on one approach for what to do with
Kconfig.socs & to me it seems like a good idea to do what's being
done here - it's likely that further arm vendors will move and
keeping the common symbols makes a lot of sense to me..."

Also, for the sake of my OCD could you pick either riscv or
RISC-V and use it for the whole series? Pedantic I guess, but
/shrug

Thanks,
Conor.

> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * No Change
> ---
>  arch/riscv/Kconfig.socs | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..91b7f38b77a8 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
> 
>  endif # SOC_CANAAN
> 
> +config ARCH_RENESAS
> +       bool
> +       select GPIOLIB
> +       select PINCTRL
> +       select SOC_BUS
> +
> +config SOC_RENESAS_RZFIVE
> +       bool "Renesas RZ/Five SoC"
> +       select ARCH_R9A07G043
> +       select ARCH_RENESAS
> +       select RESET_CONTROLLER
> +       help
> +         This enables support for Renesas RZ/Five SoC.
> +
>  endmenu # "SoC selection"
> --
> 2.25.1
> 


  reply	other threads:[~2022-08-15 19:11 UTC|newest]

Thread overview: 92+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-15 15:14 [PATCH v2 0/8] Add support for Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 15:14 ` Lad Prabhakar
2022-08-15 15:14 ` [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-15 19:11   ` Conor.Dooley
2022-08-15 19:11     ` Conor.Dooley
2022-08-18 13:00   ` Geert Uytterhoeven
2022-08-18 13:00     ` Geert Uytterhoeven
2022-08-18 13:00   ` Geert Uytterhoeven
2022-08-18 13:00     ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-18 14:55   ` Geert Uytterhoeven
2022-08-18 14:55     ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-15 19:14   ` Conor.Dooley
2022-08-15 19:14     ` Conor.Dooley
2022-08-15 19:40     ` Lad, Prabhakar
2022-08-15 19:40       ` Lad, Prabhakar
2022-08-15 19:42       ` Conor.Dooley
2022-08-15 19:42         ` Conor.Dooley
2022-08-16  7:52   ` Krzysztof Kozlowski
2022-08-16  7:52     ` Krzysztof Kozlowski
2022-08-18 15:00   ` Geert Uytterhoeven
2022-08-18 15:00     ` Geert Uytterhoeven
2022-08-18 18:14     ` Lad, Prabhakar
2022-08-18 18:14       ` Lad, Prabhakar
2022-08-15 15:14 ` [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-15 19:10   ` Conor.Dooley [this message]
2022-08-15 19:10     ` Conor.Dooley
2022-08-15 19:57     ` Lad, Prabhakar
2022-08-15 19:57       ` Lad, Prabhakar
2022-08-15 20:05       ` Conor.Dooley
2022-08-15 20:05         ` Conor.Dooley
2022-08-15 21:44         ` Lad, Prabhakar
2022-08-15 21:44           ` Lad, Prabhakar
2022-08-18 15:16   ` Geert Uytterhoeven
2022-08-18 15:16     ` Geert Uytterhoeven
2022-08-18 18:19     ` Lad, Prabhakar
2022-08-18 18:19       ` Lad, Prabhakar
2022-08-18 18:53       ` Conor.Dooley
2022-08-18 18:53         ` Conor.Dooley
2022-08-19  7:35         ` Geert Uytterhoeven
2022-08-19  7:35           ` Geert Uytterhoeven
2022-08-19  7:59           ` Conor.Dooley
2022-08-19  7:59             ` Conor.Dooley
2022-08-15 15:14 ` [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-19  8:04   ` Geert Uytterhoeven
2022-08-19  8:04     ` Geert Uytterhoeven
2022-08-19 11:42     ` Lad, Prabhakar
2022-08-19 11:42       ` Lad, Prabhakar
2022-08-19 18:40   ` Conor.Dooley
2022-08-19 18:40     ` Conor.Dooley
2022-08-20  8:45     ` Geert Uytterhoeven
2022-08-20  8:45       ` Geert Uytterhoeven
2022-08-20  8:49       ` Conor.Dooley
2022-08-20  8:49         ` Conor.Dooley
2022-08-20 12:07         ` Geert Uytterhoeven
2022-08-20 12:07           ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-15 19:00   ` Conor.Dooley
2022-08-15 19:00     ` Conor.Dooley
2022-08-15 20:16     ` Lad, Prabhakar
2022-08-15 20:16       ` Lad, Prabhakar
2022-08-19  8:25       ` Geert Uytterhoeven
2022-08-19  8:25         ` Geert Uytterhoeven
2022-08-19 11:39         ` Lad, Prabhakar
2022-08-19 11:39           ` Lad, Prabhakar
2022-08-19 18:15           ` Conor.Dooley
2022-08-19 18:15             ` Conor.Dooley
2022-08-19  8:11   ` Geert Uytterhoeven
2022-08-19  8:11     ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-19  8:42   ` Geert Uytterhoeven
2022-08-19  8:42     ` Geert Uytterhoeven
2022-08-19  9:08     ` Lad, Prabhakar
2022-08-19  9:08       ` Lad, Prabhakar
2022-08-15 15:14 ` [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 15:14   ` Lad Prabhakar
2022-08-15 18:52   ` Conor.Dooley
2022-08-15 18:52     ` Conor.Dooley
2022-08-15 19:44     ` Lad, Prabhakar
2022-08-15 19:44       ` Lad, Prabhakar
2022-08-15 19:49       ` Conor.Dooley
2022-08-15 19:49         ` Conor.Dooley
2022-08-19  8:46   ` Geert Uytterhoeven
2022-08-19  8:46     ` Geert Uytterhoeven

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