From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Conor Dooley <Conor.Dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Fri, 19 Aug 2022 12:42:12 +0100 [thread overview] Message-ID: <CA+V-a8tyvoVPctQU4Gz3FEQSCk0DBZ9=83qvh3P2UENJ5FSHAA@mail.gmail.com> (raw) In-Reply-To: <CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com> Hi Geert, On Fri, Aug 19, 2022 at 9:05 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhalar, > > On Mon, Aug 15, 2022 at 5:17 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > Single). > > > > Below is the list of IP blocks added in the initial SoC DTSI which can be > > used to boot via initramfs on RZ/Five SMARC EVK: > > - AX45MP CPU > > - CPG > > - PINCTRL > > - PLIC > > - SCIF0 > > - SYSC > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > > @@ -0,0 +1,121 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/Five SoC > > My first thought was: > > This should be arch/riscv/boot/dts/renesas/r9a07g043f01.dtsi, > including the common r9a07g043.dtsi, shared by > arch/arm64/boot/dts/renesas/r9a07g043u11.dtsi. > > Then I realized this is harder than it sounds, due: > Indeed, my initial thought after the comments from Conor was we could share the SoC dtsi, but that would be to messey due to PLIC. Cheers, Prabhakar > > + soc: soc { > > + compatible = "simple-bus"; > > + interrupt-parent = <&plic>; > > vs. "interrupt-parent = <&plic>;" for r9a07g043u11, but mostly > due to > > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + scif0: serial@1004b800 { > > + compatible = "renesas,scif-r9a07g043", > > + "renesas,scif-r9a07g044"; > > + reg = <0 0x1004b800 0 0x400>; > > + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, > > + <414 IRQ_TYPE_LEVEL_HIGH>, > > + <415 IRQ_TYPE_LEVEL_HIGH>, > > + <413 IRQ_TYPE_LEVEL_HIGH>, > > + <416 IRQ_TYPE_LEVEL_HIGH>, > > + <416 IRQ_TYPE_LEVEL_HIGH>; > > vs. "interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH> ..." on > r9a07g043u11. > Interestingly, the actual hardware interrupt numbers are the same, > but the GIC DT bindings abstracts the offset of 32 by using a second > cell and GIC_SPI. Unfortunately this cannot be handled by some CPP > magic, as dtc does not support arithmetic operations yet. > > I expect this or similar issues to pop up everywhere, when more > RISCV-V SoCs will appear that share the non-CPU parts with ARM SoCs. > > Ignoring this issue, which we probably can solve only later: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Conor Dooley <Conor.Dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Fri, 19 Aug 2022 12:42:12 +0100 [thread overview] Message-ID: <CA+V-a8tyvoVPctQU4Gz3FEQSCk0DBZ9=83qvh3P2UENJ5FSHAA@mail.gmail.com> (raw) In-Reply-To: <CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com> Hi Geert, On Fri, Aug 19, 2022 at 9:05 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhalar, > > On Mon, Aug 15, 2022 at 5:17 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > Single). > > > > Below is the list of IP blocks added in the initial SoC DTSI which can be > > used to boot via initramfs on RZ/Five SMARC EVK: > > - AX45MP CPU > > - CPG > > - PINCTRL > > - PLIC > > - SCIF0 > > - SYSC > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > > @@ -0,0 +1,121 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/Five SoC > > My first thought was: > > This should be arch/riscv/boot/dts/renesas/r9a07g043f01.dtsi, > including the common r9a07g043.dtsi, shared by > arch/arm64/boot/dts/renesas/r9a07g043u11.dtsi. > > Then I realized this is harder than it sounds, due: > Indeed, my initial thought after the comments from Conor was we could share the SoC dtsi, but that would be to messey due to PLIC. Cheers, Prabhakar > > + soc: soc { > > + compatible = "simple-bus"; > > + interrupt-parent = <&plic>; > > vs. "interrupt-parent = <&plic>;" for r9a07g043u11, but mostly > due to > > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + scif0: serial@1004b800 { > > + compatible = "renesas,scif-r9a07g043", > > + "renesas,scif-r9a07g044"; > > + reg = <0 0x1004b800 0 0x400>; > > + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, > > + <414 IRQ_TYPE_LEVEL_HIGH>, > > + <415 IRQ_TYPE_LEVEL_HIGH>, > > + <413 IRQ_TYPE_LEVEL_HIGH>, > > + <416 IRQ_TYPE_LEVEL_HIGH>, > > + <416 IRQ_TYPE_LEVEL_HIGH>; > > vs. "interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH> ..." on > r9a07g043u11. > Interestingly, the actual hardware interrupt numbers are the same, > but the GIC DT bindings abstracts the offset of 32 by using a second > cell and GIC_SPI. Unfortunately this cannot be handled by some CPP > magic, as dtc does not support arithmetic operations yet. > > I expect this or similar issues to pop up everywhere, when more > RISCV-V SoCs will appear that share the non-CPU parts with ARM SoCs. > > Ignoring this issue, which we probably can solve only later: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-08-19 11:42 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-15 15:14 [PATCH v2 0/8] Add support for Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 15:14 ` [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:11 ` Conor.Dooley 2022-08-15 19:11 ` Conor.Dooley 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-18 14:55 ` Geert Uytterhoeven 2022-08-18 14:55 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:14 ` Conor.Dooley 2022-08-15 19:14 ` Conor.Dooley 2022-08-15 19:40 ` Lad, Prabhakar 2022-08-15 19:40 ` Lad, Prabhakar 2022-08-15 19:42 ` Conor.Dooley 2022-08-15 19:42 ` Conor.Dooley 2022-08-16 7:52 ` Krzysztof Kozlowski 2022-08-16 7:52 ` Krzysztof Kozlowski 2022-08-18 15:00 ` Geert Uytterhoeven 2022-08-18 15:00 ` Geert Uytterhoeven 2022-08-18 18:14 ` Lad, Prabhakar 2022-08-18 18:14 ` Lad, Prabhakar 2022-08-15 15:14 ` [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:10 ` Conor.Dooley 2022-08-15 19:10 ` Conor.Dooley 2022-08-15 19:57 ` Lad, Prabhakar 2022-08-15 19:57 ` Lad, Prabhakar 2022-08-15 20:05 ` Conor.Dooley 2022-08-15 20:05 ` Conor.Dooley 2022-08-15 21:44 ` Lad, Prabhakar 2022-08-15 21:44 ` Lad, Prabhakar 2022-08-18 15:16 ` Geert Uytterhoeven 2022-08-18 15:16 ` Geert Uytterhoeven 2022-08-18 18:19 ` Lad, Prabhakar 2022-08-18 18:19 ` Lad, Prabhakar 2022-08-18 18:53 ` Conor.Dooley 2022-08-18 18:53 ` Conor.Dooley 2022-08-19 7:35 ` Geert Uytterhoeven 2022-08-19 7:35 ` Geert Uytterhoeven 2022-08-19 7:59 ` Conor.Dooley 2022-08-19 7:59 ` Conor.Dooley 2022-08-15 15:14 ` [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-19 8:04 ` Geert Uytterhoeven 2022-08-19 8:04 ` Geert Uytterhoeven 2022-08-19 11:42 ` Lad, Prabhakar [this message] 2022-08-19 11:42 ` Lad, Prabhakar 2022-08-19 18:40 ` Conor.Dooley 2022-08-19 18:40 ` Conor.Dooley 2022-08-20 8:45 ` Geert Uytterhoeven 2022-08-20 8:45 ` Geert Uytterhoeven 2022-08-20 8:49 ` Conor.Dooley 2022-08-20 8:49 ` Conor.Dooley 2022-08-20 12:07 ` Geert Uytterhoeven 2022-08-20 12:07 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:00 ` Conor.Dooley 2022-08-15 19:00 ` Conor.Dooley 2022-08-15 20:16 ` Lad, Prabhakar 2022-08-15 20:16 ` Lad, Prabhakar 2022-08-19 8:25 ` Geert Uytterhoeven 2022-08-19 8:25 ` Geert Uytterhoeven 2022-08-19 11:39 ` Lad, Prabhakar 2022-08-19 11:39 ` Lad, Prabhakar 2022-08-19 18:15 ` Conor.Dooley 2022-08-19 18:15 ` Conor.Dooley 2022-08-19 8:11 ` Geert Uytterhoeven 2022-08-19 8:11 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-19 8:42 ` Geert Uytterhoeven 2022-08-19 8:42 ` Geert Uytterhoeven 2022-08-19 9:08 ` Lad, Prabhakar 2022-08-19 9:08 ` Lad, Prabhakar 2022-08-15 15:14 ` [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 18:52 ` Conor.Dooley 2022-08-15 18:52 ` Conor.Dooley 2022-08-15 19:44 ` Lad, Prabhakar 2022-08-15 19:44 ` Lad, Prabhakar 2022-08-15 19:49 ` Conor.Dooley 2022-08-15 19:49 ` Conor.Dooley 2022-08-19 8:46 ` Geert Uytterhoeven 2022-08-19 8:46 ` Geert Uytterhoeven
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